Logic circuit design lab projectsSpring, 2015

Project rules:

1. Each 2 consecutive odd and even sections have to be subdivided into groups of five to six students. All the students in a group must be from these 2 sections only.

2. All groups will do the project of their sections as shown below. No group is allowed to choose a project of any other sections.

3. Any group has the option to freely replace their project with the additional project found at the end of this file.

4. Copied projects will be awarded a zero.5. During the submission of the project, all the group members must be present. Every student in

the group will be asked individually in the project details, codes and may be asked to do any task on the tools (ISE & ModelSim or ISIM).

6. Each group should prepare a report containing the steps of the design, the schematic of the system, the VHDL codes and the simulation results.

The steps of the design: you may have divided the circuit into smaller easy parts or decided to do a behavioral implementation, etc

The schematic: A schematic drawn by you on a software, and the RTL schematic from Xilinx ISE found under the synthesis process.

Simulation results: screen-shots with comments

7. Submission will be in the logic laboratory according to a timetable announced later starting from Saturday 9/5/2015, At least one laptop must be present at the discussion.

8. The project is to be discussed with two TAs, each TA is responsible for 6 sections:1) E. Yehia's sections: 1,2,3,4,11,122) E. Khalid's sections: 5,6,7,8,9,10

9. Each group will turn-in the project files and a soft-copy of the report on a flash drive at the discussion.

10. For E.Yehia's sections: Each group will handle a hardcopy report at the discussion. For E. Khalid's sections: Each group must send the report electronically before the discussion to k.e.elsayed+submission@gmail.com, with the title:logic_project seat_number_of_team_captain Example: logic_project 320

11. The project is to be done in VHDL. Verilog implementations will be awarded a bonus.12. Fill in this form with the team members' names and numbers, the first team member is the team

captain. The deadline for forming teams and filling the form is Sunday 3/5/2015, If you have a problem finding a team after that date then contact E. Khalid. You will be told your submission date sometime after you fill the form. It will be in your lab's time period. https://docs.google.com/forms/d/176EzKItjQfG2BV_sVNWlHCaPFPXildktypJN2h6lJko/viewform

I. Projects:Sections 1 & 2

Digital ClockIn this project, you will design a module of a digital clock. It has an input clk which is assumed to have frequency 1 Hz and 3 outputs. One output is for the seconds, another one isfor the minutes and the last one is for the hours. The first output (seconds) is incremented every 1 clk cycle until it reaches 59 and then returns back to 0 & also increments the output that represents the minute. When the minute output reaches 59, the next increment will return it to 0 & also increments the hour output. It also has another set of inputs to adjust theclock to a certain time before running the clock.

Sections 3 & 4

Digital Stop WatchYou will design a digital stop watch which counts downwards. It has 4 inputs: clk, min, sec & start_stop. The first input (clk) is an input clock which is assumed to have frequency 1 Hz. The inputs min & sec is the inputs to define the minutes and seconds from which it will start counting from. The start_stop input is used to start or stop the stop- watch count. It has 3 outputs: min_out, sec_out & finish. The first two outputs is used to show the counting value the stop watch are counting while the last output (finish) is used to determine the finish of counting. The user determines the required count the stop watch start with, through defining the 2 inputs min & sec. Then start the counting through the input start_stop. The stop watch starts to count down from these predefined values till reaching zero. When the counting reaches zero, the output (finish) will be logic 1.

Sections 5 & 6

Pulse width modulation circuitIn a square wave, the duty cycle is defined as the percentage of time that the signal is asserted as '1' in a period. For example, the duty cycle of a symmetric square wave is 50% since the signal is asserted as 1 half of the period. A PWM circuit generates an output pulse with an adjustable duty cycle. It is frequently used to control the on-off time of an external system.Consider a PWM circuit whose duty cycle can be adjusted in increments of 1/16, i.e., the duty cycle can be 1/16 , 2/16 , 3/16 , .., 15/16 , 16/16. A 4-bit control signal, w, which is interpreted as an unsigned integer, specifies the desired duty cycle. The duty cycle will be 16/16 when w is "0000", and will be w/16 otherwise.It has 2 inputs: clk & w and one output. This output is the square wave of period 16 times the clock period and with the adjustable duty cycle.

Sections 7 & 8

Serial Data transmitterSerial data transmitter is a circuit which takes in parallel data and transmits out serial data which certain constrains. It has a seven bits data input, din(6:0), and a control signal start_transmit. A clock signal clk is also needed at the input. It has one output, serial_out, which is a single bit used to send out the serial data. When no bits are sent, the serial_out is 0. The sent serial data consists of ten bits. The first bit is a start bit, which must be high to inform the receiver with presence of a new serial data. The next seven are the actual data bits, din, where the least significant bit of din is send first. The ninth bit is a parity bit, whose status must be 0 if the number of ones in data is even or 1 otherwise. Finally, the tenth is a stop bit, which must be sent high. When the start_transmit signal is asserted 1, the circuit reads the input data, din, calculate the parity bit and start sending the ten bits serially. A new bit is send at the rising edge of theclk. When finishing, the circuit must return the serial_out to 0 again.

Sections 9 & 10

Serial Data ReceiverThe diagram of a serial data receiver is shown below. It contains a serial data input, din, anda parallel data output, data(6:0). A clock signal is also needed at the input. Two supervision signals are generated by the circuit: err (error) and data_valid. When no bits are received, the din is 0. The input data train consists of ten bits. A new bit is received at the rising edge of the clock. The first bit is a start bit, which, when high, must cause the circuit to start receiving data. The next seven are the actual data bits. The ninth bit is a parity bit, whose status must be 0 if the number of ones in data is even or 1 otherwise. Finally, the tenth is a stop bit, which must be high if the transmission is correct. An error is detected when eitherthe parity does not check or the stop bit is not a 1. When reception is finished and if no error has been detected, then the data stored in the internal registers is transferred to the output data(6:0) and the output data_valid output is 1 .

Sections 11 & 12

8-bit Super Register (Universal Register/Counter) The super register is a register that can be used as a universal register or as a counter. As a universal shift register, it can load a parallel data word and perform shifting or rotating in either direction. As a counter, it can count up or down. So for the super register there are eight operations: load a new data, shift right, shift left, rotate right, rotate left, store the present data, count up and count down. It has 5 inputs: clk, data_in , control, data_sh_r and data_sh_l. The first input, clk, is the clock input where any new operation takes place at the rising edge of this clock signal. The second input, data_in, is an 8 bit input used to load a new data into our register. The third input, control, is a 3 bit input to determine which operation of the eight operations to be performed. The last two inputs, data_sh_r and data_sh_l, each is a 1 bit input used as a shift-in bit when shifting right or left respectively. It has two outputs. The first output is 8 bit representing the output data from the register, while the second output is a single bit which is 1 when the output of the register is either 00000000 or 11111111 and is 0 otherwise.

Additional Project

Digital Square VCOVCO stands for Voltage Controlled Oscillator. Oscillator is a circuit that produces periodic output such as sine wave or square wave without having input sine wave or square wave. A voltage controlled oscillator (VCO) is an oscillator which we can control the frequency of the output periodic wave through an input controlling voltage.We want to design a digital VCO whose output is a square wave. The frequency of this square wave can be controlled using input control bits. This circuit has 3 inputs: clk, control_freq and range. The first input is the clock signal whose frequency is 1 MHz. The second input (control_freq) is a 3 bit input which is used to control the frequency of our VCO. The user can choose between 8 different numbers for the frequency. The third input (range) is a single bit which determines the unit of the number, chosen by the control_freq, whether it is in Hz or in KHz. It has only one output which is the periodic square wave with 50% duty cycle. As an example, to understand the operation, when the user put 000on control_freq and put 0 on range, the output will be a square wave with freq 500 KHz, when the user put 001on control_freq and put 0 on range, the output will be a square wave with freq 250 KHz, when the user put 001on control_freq and put 1 on range, the output will be a square wave with freq 250 Hz and so on. You are free to choose the different eight values of the frequency.