Liechti Report 2004

8/8/2019 Liechti Report 2004

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DESIGN OF A HIGH-SPEED 12-BIT DIFFERENTIAL

PIPELINED A/D CONVERTER

Diploma Project

Thomas Liechti

February 2004

Assistant: Zeynep Toprak (LSM)

Professor: Yusuf Leblebici (LSM)

Microelectronic Systems Laboratory (LSM)

Swiss Federal Institute of Technology Lausanne


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Design of a High-Speed 12-bit Differential Pipelined A/D Converter

Table of Contents

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 Performance measures of A/D converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 A/D-Converter Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 A/D Converter Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4 ADC Pipeline Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.4.1 4-Stage Converter Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.4.2 Analog Pipeline Stage Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

1.4.3 Pipelined A/D Conversion and Digital Error Correction . . . . . . . . . . . . . . . . . . . . . . 6

1.4.4 Analysis of accuracy requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.4.5 Clocking scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2 4-bit Flash Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1 4-bit Flash A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92.1.1 Flash ADC Floorplan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 Differential Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2.1 Choice of Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2.2 Comparator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.2.3 Comparator Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3 Performance verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.1 Comparator Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.2 Flash ADC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3 4-bit Digital-to-Analog Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1 Current-steering D/A Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1.1 Continuous DAC Gain Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.1.2 DAC Floorplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2 Unit current cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2.1 Fournier-Senn [15] Current cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.2.2 Regulated Cascode Current Cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.3 Simulated Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4 Residue Amplifier and Sample-and-Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1 Switched Capacitor Residue Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1.1 Circuit Topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

4.1.2 Charge Injection of MOS Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

4.1.3 Capacitor and Switch Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

4.2 Differential OTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4.2.1 Mirrored cascode with class AB input stage with preamplifier . . . . . . . . . . . . . . . 28

5 Top-Level Floorplanning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.1 Analog Pipeline Stage Floorplan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

5.2 Floorplan of complete pipeline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

6 Conclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
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References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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1 Introduction

The goal of this d iploma project is to redesign an existing p ipelined 12-bit 200-MS/ s

single-end ed analog-to-digital converter [4] to make its analog signal path fully differential.

The converter has four 4-bit pipeline stages, each stage consisting of a Flashanalog-to-digital converter, a digital-to-analog converter, and a residue amplifier (Figure 2).

Only the blocks in the analog signal path have to be redesigned. The digital part consisting

of thermometric to binary encoders and digital error correction does not need to be

modified to make the converter differential. It is taken as is from the design presented in [4].

A prototype of a converter stage will be implemented on silicon. Some blocks will need to

be finished after this report h as been written.

Making the analog signal path of the converter fully d ifferential has several advantages:

Increased signal dynamic range, which isespecially important for low-voltage analog

designs. Even h armonics introduced by circuit non-linearities are cancelled, improving the

harmonic distortion characteristics of the system.

Immunity to common mode noise coming from the power supply or digital parts

residing on the same chip for examp le.

Errors due to MOS-switch charge inject ion and clock feedthrough can more easily be

cancelled as these errors are often common-mode signals. This is especially important

in high -precision switched-capacitor circuits.

These advantages make a fully differential signal path especially useful for mixed-signal

designs [1], where analog and (noisy) digital circuitry have to coexist on the same die, and

wh ere the low supply voltage is imp osed by the d igital process.

The ADC is designed as a block in a conventional logic 0.18 CMOS process so it can easilybe integrated into a digital system.As this process does not provide high precision resistors

and capacitors the d esign should rely as little as possible on the p recise matching of these

elements. Thus, using precisely m atched resistors and capacitors has to be avoided where

possible. Special care has to be taken wh en d rawing the layout of matched elements.

The design also has to cope w ith low-voltage and deep-subm icron technology issues. To

analog circuits, the down-scaling of minimum feature size is not as beneficial as to digital

circuits [8]:

The signal-to-noise ratio (SNR), i.e.the dynamic range between signal amplitude and

noise floor is inherently limited by the low supply voltage (imp osed by low

breakdown voltages) because a thermal noise floor is always present, and the supply

voltage imposes an upper bound on (voltage) signal amplitude.For very low voltage

designs, current mod e processing can thus be an interesting alternative to voltage

mod e processing as current is not d irectly limited by the sup ply voltage (and the

oxide breakdown voltage of the p rocess).

Many low voltage circuit topologies are inherently slower that their high-voltage

counterparts. Also, as oxide layers get thinner and features move closer together with

technology scaling, p arasitic capacitances get larger.

Short channel effects such as very high gds (drain-to-source conductance) degrade

transistor p erformance.


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The challenge of this project is thus to find and dimension fully differential

implementations of the functional blocks of the single-ended converter that satisfy the very

ambitious speed sp ecification (Section 1.3) despite th e technological limits.

App lications of ADC with performance specifications in this range are used for high

band wid th ap plications such as digital video and wireless comm un ication devices.

This report first gives a short summary ofcommonly used performance measures for A/ D

converters. Only a very short overview on converter architectures is given because a

pipelined architecture has already been chosen for this design. In Section 1.4 the converter

structure is described in d etail. The design of the Flash ADC is detailed in Section 2,

Section 3 describes the DAC design, and the Residu e Amp lifier is described in Section 4.

Finally top levelfloorplanning is discussed in Section 5. Section 6 summarizes the work that

has been d one and indicates the following steps in the d evelopm ent of the converter.

1.1 Performance measures of A/D converters

An analog-to-digital converter (Figure 1) transforms an analog signal (continuous in time

and amp litud e) to a d igital signal wh ich is discrete in time and amp litude. First, the inpu t

waveform is sampled at discrete time intervals (assumed equidistant)by a sample-and-hold

(S/ H) circuit. The S/ H output is a continuous-amplitude discrete-time signal proportional

to the input signals amplitude at the sampling instant. The n-bit A/ D converter quantizes

this signal into 2n discrete amp litud e levels, each one of wh ich is described by a n-bit

codeword.

The amplitud e quan tization introdu ces a quan tization error. For inpu t signals with

frequency content on ly below half the sampling rate, the systems accuracy ideally is only

limited by this error. However, in practical converters,other sources of errors such as circuitelement m ismatches and rand om n oise add to the total error, and limit the effective

accuracy that can be achieved.

The definitions used in this w ork of different performance measure of ADC systems are

sum marized next. More performance measures are described in [4].

The Differential Nonlinearity (DNL) error describes the difference between the ideal

step size (1 LSB) and the effective step sizes of the converter. For an A/ D converter,

Figure 1: Block diagram of an Analog-to-Digital Converter [5]

Digital Output

2

B1

B0

Bn3Bn2Bn1

nbit

A/D Converter

Sampled

Input

Analog

Input

S/H

B


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There is a large variety of architectures for Nyquist rate converters:

Flash (parallel) converter are very fast but the num ber of required comparators

increases exponentially with the number of bits, thus entailing large ICs (high cost,

difficult device matching), high power consum ption and h igh inpu t capacitance.

Time-interleaving converters: To or more converters work in parallel with shifted

clocks. High p ower d issipation.

Serial and successive app roximation converters: Convert an input samp le using a

number ofsequential steps.These converters can be very accurate and small,but slow

because several conversion steps n eed to be performed for each sam ple.

Because the architecture to be used for the converter is given, no study of other converter

architectures has been carried out. For high-speed Nyquist-rate A/ D converters a pipelined

architecture is very well suited because it allows to decouple conversion rate (sampling

rate) from conversion time. That is, through pu t can be increased by extending the latency

between the time the analog sample is taken and the time when th e correspond ing digital

value is available at the converters output (in many applications latency is not as critical as

through pu t.) The idea is to split the conversion into a nu mber of serially executed

low-resolution conversions. In one sampling interval, only a low resolution conversion has

to be achieved instead of a full resolution conversion. The low resolution conversion can be

much faster because the accuracy requirement of the comparators (in the flash ADC) is

relaxed, which allows faster comparator architectures to be used (trade accuracy for speed).

Another ad vantage is the reduced n um ber of comparators: The pipelined ADC uses less,

and less accurate comparators than a Flash ADC w ith the sam e resolution. The other

elements in the pipeline stage (DAC and residue amplifier, see Figure 3), however, need full

resolution accur acy, not just the p er-stage resolution accuracy (see Section 1.4.4).

1.3 A/D Converter Specifications

The A/ D Converter specifications are sum marized in Table 1. Note that no pow er spec is

given. The first objective is to reach th e 200 MHz sam pling sp eed, and not low pow er

consump tion. The design may th us trad e power for speed and accuracy.

The specifications in Table 1 are comparable to the performance of current state of the art

converters [10][4].

The 1 Volt peak-to-peak input signal swing has been set to 0.6 to 1.6 V, resulting in an analog

ground level of 1.1 V. The lower bound of 0.6 V allows using NMOSdifferential input pairs

(the nom inal threshold voltage being 0.5 V) while leaving 200 mV headroom for PMOS

current mirrors. The analog ground level stays the same throughout the analog pipeline.

Table 1: ADC Specifications

Stated Resolution

Voltage swing

12 bits

1Vpp (differential)

Sampling Rate 200 MHz

Architecture 4 pipelined 4-bit flash stages with bit overlapping

Technology UMC 0.18 logic CMOS (1.8 V)


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1.4 ADC Pipeline Architecture

1.4.1 4-Stage Converter Structure

Figure 2 show s the structure of the complete 4-stage converter p ipeline. It consists of a

horizontal analog pipeline and a vertical digital pipeline performing digital error correction

and assembling th e digital outpu ts of the four analog ADC stages. The same signal flow

structure is used in the layout of the converter (Section 5.2). It allows easy slicing of the

system into four almost identical parts that can simp ly be abutted to form th e whole

pipeline, thus reducing routing length between the stages.Another important benefit of this

arrangement of circuit blocks is that it clearly separates the analog part from the digital part.

This will minimize noise injected from the digital circuitry into the analog signal path.

Once the first stage is comp leted, the whole pip eline can be assembled very easily. Only

small modifications are needed in the encoder and digital part of the stages.

A front-end sample-and -hold circuit required at inp ut of first pipeline stage to hold the

input stable during the conversion cycle. For the following stages the residue amplifier (see

Section 1.4.2) in the p revious pipeline stage will act as sam ple and hold circuit. The

front-end sam ple-and -hold block has very stringent requ irements on sampling time

un certainty (apertu re jitter) because it samples an time-varying analog signal. Inside th e

pipeline stages, settled signals are samp led, and consequently sampling time jitter is less

critical there.

In [10] it is suggested th at aperture jitter is the d ominant limiting factor for the SNR of

current high-performance ADCs. Front-end sampling is thus very critical. In the prototype,

the front-end sample-and-hold circuit will be external to the chip and its design is not part

Figure 2: Block diagram of four-stage pipelined A/D converter [4]

DISCARDED

ENCODER 2 (smart)ENCODER 1 ENCODER 3 (smart) ENCODER 4 (smart)

ANALOG

PIPELINE STAGE 1

DAC 1

4

ADC 1

ANALOG

PIPELINE STAGE 2

A1 B1

DAC 2

3

ADC 2

ANALOG

PIPELINE STAGE 3

DAC 3ADC 3

3

ANALOG

PIPELINE STAGE 4

3

ADC 4

A2 B2 A3 B3

FA

FAFAFAFAFA

DFF DFF DFF DFFDFF

FAFAFAFAFA

DFF DFF DFF DFFDFF

DFF DFF DFF DFFDFF

DFF DFF DFF DFF

FAFAFAFA

FAFAFA

DFF DFF DFF

DFF DFF DFF

FAFAFA

DFF DFF DFF

FAFAFA

DFF DFF DFF

DFF DFF DFF DFF DFF DFF

Fron

tEn

d

S/H

(external)

0

B1

A1

A2

B2

A3

B3

B2

B3

B1

vinvin

OVERFLOW MSB LSB


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Figure 4: DC Characteristic of 4-bit Flash ADC and DAC connected in series

Table 2: Thermometric to binary code conversion table

Thermometer code

(decimal representation)

Binary code

(stage 1 encoder)

Binary code ofsmart encoders

(stages 2-4)

Over-flow

(a)

Under-flow

(b)

15 1111 011 1 0

14 1110 010 1 0

13 1101 001 1 0

12 1100 000 1 0

11 1011 111 0 0

10 1010 110 0 0

9 1001 101 0 0

8 1000 100 0 0

7 0111 011 0 0

6 0110 010 0 0

5 0101 001 0 0

+1Vvin

vout

0000

0001

0010

0011

0100

0101

0110

0111

1001

1011

1010

1000

1100

1101

1110

1111

1V

+1V

1V


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Bubble errors in the thermometric code (due to metastability or noise in the comparators for

example) are not corrected, but could cause gross errors (including short circuit)d epending

on the encoder. The encoder imp lementation proposed in [4] could cause short circuits by

connecting a bit line simu ltaneously to Vdd and ground because more than one decoder

row is activated.

1.4.4 Analysis of accuracy requirements

Thanks to bit overlapp ing the Flash ADC theoretically only needs to be 4 bit accurate. The

DAC and the Residue Amp lifier, however, need full 12-bit accur acy, at least in first stage.

Because all stages use the same bu ilding blocks, the blocks all have to fulfill the precision

requirements of the first stage.

Errors are most significant in first stage:DAC errors in the first stage are amplified 83 = 512

times before reaching the last pipeline stage. There they should still be smaller than 0.5 LSB

of the Flash converter. The error at the input of the first stages Residue Amplifier thus has

to be < 0.24 mV. Note that the last stage has an LSB of 250 mV (instead of 125 mV like the

other stages) because the LSB of its 3 outpu t bits can be d iscarded for a 12-bit outpu t (see

Figure 1).

The maximum allowable gain error of the first stage Residue Amplifier can be estimated as

follows: Everything in the converter is assumed ideal except for the first stage Residue

Amplifier which has a gain of8(1+). In the worst case the residue will be 0.5 LSB= 62.5 mV.Hence 8*62.5**82 < 125 m V=> < 2/ 83 = 0.004. The maximum allowable gain error is thusestimated to be a few p er mils.

In the presented design, calibration is only used where it is easily implementable and doesnot add m uch circuit comp lexity, or need man y add itional I/ O pins. A continuou s

calibration feedback is used to adjust DAC gain, but there is no calibration mechanism for

the Residu e Amp lifier gain.

1.4.5 Clocking scheme

The clocking scheme is kept as simp le as possible. Because of switched-capacitor Residue

Amp lifier, more clock phases are needed than in the single-ended design in [4]. Figure 5

shows the clocking scheme of the pipeline stage. The signal names refer to the clock phases

used in the comparator (Figure 11) and the Residu e Amplifier (Figure 26).

4 0100 000 0 0

3 0011 111 0 1

2 0010 110 0 1

1 0001 101 0 1

0 0000 100 0 1

Table 2: Thermometric to binary code conversion table

Thermometer code

(decimal representation)

Binary code

(stage 1 encoder)

Binary code of

smart encoders

(stages 2-4)

Over-

flow

(a)

Under-

flow

(b)


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There are three critical phases that cannot overlap and that have to fit inside the 5 ns

samp ling interva l: (1) reset of the Residue Amp lifier, (2) samp ling of the DAC outp ut an d

settling of the Residue Amplifier output, and (3) sampling and settling of input voltage.The

input to the stage (and thus to the comparators) can change as soon as the SR-latches of the

comparators (Figure 11) have switched. The comparator w ill be fully unbalanced, and its

stage can only change after it has been reset.

Four external triggers are needed , all other clocks can be triggered by other clock edges

(indicated in Figure 5 by d ashed arrow s): the beginning of the regeneration p hase of the

comparator, the end ofthe sampling of the input voltage, the end of the Residue Amplifier

reset, and th e end of the DAC outp ut sam pling. Making these four events evenly spaced

allows gen erating all clocks from two 90-degree shifted 200MHz clocks.

Note that the comparator reset timing is not critical. To reduce possible hysteresis due to

incomp lete reset between two cycles, the comp arator is reset for as long as p ossible.

Designing a self-contained clock generation circuit (using a PLL or DLL) is not necessary for

the first prototype. In fact, inputting two shifted 200 MHz clocks from the outside givesmore degrees of freedom (frequency, duty cycle) on the timing of the internal clock signals.

2 4-bit Flash Analog-to-Digital Converter

2.1 4-bit Flash A/D Converter

A Flash top ology is used for the 4-bit ADC as this top ology is very fast and quite compact

for a small num ber of bits. An N-bit Flash ADC needs 2N-1 comp arators, hence, for 4 bits,

15 comparators are needed . The 15 differential reference voltages are generated using a

Figure 5: Clocking Diagram for Pipeline Stages

time

reset

residue amp

reset

1a,b

PHI2

R

2a

2b

t=0 t=Ts

input/output stable input/output stable

sample DAC output

sample inputsample input

Residue Amp settled

DAC settled

SR latch switched

comprator


13/3610


resistive ladd er as shown in Figure 6 [6]. N+Polysilicon resistors are used for the resistor

ladd er because they p rovide reasonable matching and linearity.

The resistor ladder value has been set to 500 , resulting in a static current of 125 A.A largeresistor area (W*L) improves matching and helps stabilize the reference voltages thanks to

the large parasitic capacitance. The recovery time of the reference voltage nodes should be

short enou gh for the n odes potentials to fully recover from coup ling noise between two

sampling instants.

Two external p ins (vref_plus and vref_minus) are used to d efine signal range.

Figure 6: Flash Converter

Q14

vin+

vin

vref

vref+

vin+

vin

vref

vref+

vin+

vin

vref

vref+

vin+

vin

vref

vref+

vin+

vin

vref

vref+

vin+vin

vref

vref+

vin+

vin

vref

vref+

vin+

vin

vref

vref+

vin+

vin

vref

vref+

vin+

vin

vref

vref+

vin+

vin

vref

vref+

vin+

vin

vref

vref+

vin+

vin

vref

vref+

vin+

vin

vref

vref+

vref2

vin2

vref1

vin1

VBIAS

PHI2

PHI1

vin+vin

vref

vref+

PHI1

PHI2

VBIAS

R R

RR

R R

RR

RR

R

R

R

R

R

R Q1

Q1

Q2

Q2

Q3

Q4

Q5

Q3

Q4

Q5

Q6

Q7

Q6

Q7

Q8

Q8

Q9

Q10

Q11

Q11

Q10

Q9

Q12

Q13

Q12

Q13

Q15

Q15

Q14


14/3611


2.1.1 Flash ADC Floorplan

Figure 8 shows the floorplan of the 4-bit Flash ADC. The folded arrangement of resistorladd er causes mismatches to be symmetrical to the inpu t range m idpoint (first and last

resistor etc. are closely matched because ad jacent). The floorp lan ind icates a possible way

of laying ou t and connecting the 16 reference ladd er resistors. The p roposed arrangement

of 32 resistor elements can be mad e wide to stack to about the same height as th e 15

comparators (comp arator height is 15m). Wider resistors will improve matching an d theincreased parasitic capacitance will make the nodes less prone to capacitive coupling.

2.2 Differential Comparator

A differential comp arator compares a differential inpu t voltage to a d ifferential reference

voltage, i.e. it implements the following inequality:

(2)

One state of the binary comparator outp ut w ill indicate that (2) valuates to true, the other

one that it evaluates tofalse.

2.2.1 Choice of Topology

Inequality (2) ind icates that a d ifferential comp arator can be built as a differencing circuit

followed by a single-end ed comparator.

Figure 7: Ideal DC transfer characteristic of the 4-bit Flash ADC

10

levels

ideal code

midpoints

vin1V +1V

output code

2

3

4

5

9

8

7

6

1

0

15

14

13

12

11

ideal threshold

vin 1 vin 2( ) vre f1 vre f2( ) 0>


15/3612


A topology based on two cross-coupled flip-flops [11] and two differential pairs [12] has

finally been chosen (briefly mention other topologies that have been considered?). The cross

coupled flip-flops (Figure 9(b)) provide fast decision: The small input difference (output of

the differencing circuit)is quickly regenerated to a rail-to-rail signal by the high (nonlinear)

gain of the regeneration flip-flops. The two differential pairs (Figure 9(a)) imp lement a

(nonlinear) d ifferential difference amp lifier:

(3)

Because f(I,v) is monotonic in v (and in this particular case also I), (2) an d (3) alwaysevaluate to the sam e logic value if Ia and Ib are the same.

Note that (2) can also be written as

(4)

The second view (4) is better for the input range requirements ofthe differential pairs.When

crossing thresholds, the differential inputs should be as close as possible to the origin of the

transfer curves of the differential pairs because there the gain is highest, leading to smaller

Figure 8: Floorplan of 4-bit Flash ADC

Res

istor

ladder

0100110011010011010101

001100110 00 00 01 11 11 1

0 00 01 11 10 00 01 11 10 00 00 01 11 11 10 00 01 11 10 00 01 11 1

00110 00 00 01 11 11 10 00 00 01 11 11 10 00 01 11 10 00 00 01 11 11 10 00 01 11 1 0 00 00 01 11 11 1

0 00 01 11 100110 00 01 11 10 00 01 11 10 00 00 01 11 11 10 00 01 11 10 00 01 11 10 00 01 11 10 00 01 11 10 00 00 01 11 11 10 00 00 01 11 11 10 00 01 11 10 00 00 01 11 11 1 Comparator 1

Comparator 15

Comparator 2

Comparator 14

Comparator 7

Comparator 9

Comparator 8

Clock

digita

lou

tpu

tstoenco

de

ran

dDAC

analog inputreference input

referencevo

ltages

f Ia vin 1 vre f1,( ) f Ib vin 2 vre f2,( ) 0>

vin 1 vre f1( ) vin 2 vre f2( ) 0>


16/3613


resolvable voltage d ifferences. Far aw ay from the origin, the d ifferential gain of the pairs

goes to zero, no d ecision can be mad e.

A topology consisting of the th ree parts show n in Figure 9 was finally adop ted: (a) two

differential inpu t pairs (differencing circuit), (b) a clocked cross-coupled latch (the actual

comparator), and (c) an SR-latch to hold the comparator output until the next clock cycle.

Three different versions of the comparator were examined. All have N MOS input pairs

since PMOS transistors wou ld have to be very large to allow a 0.6 to 1.6 V input range.

1. PMOS pu ll-up, inverters, NAND-based SR latch

2. current mirrors, NMOS pu ll-dow n, NAND-based SR latch

3. PMOS pu ll-up, NOR-based SR latch

NMOS pull-down (for setting or resetting the SR-latch) provides faster response time than

PMOS pu ll-up. Inverters at the outpu t for the regenerative flip-flops ad d d elay but at the

same tim e buffer the cross-coup led latchs outpu t. Finally, the NAND-based SR latch is

faster than NOR-based equivalent because the NOR version has PMOStransistors in series,

while in the NAND version, the NMOS transistors are stacked; also, the NOR causes low

output crossing point, which is not useful when using NMOS current switches in the DAC

(see Section 3.1).

Version 2 ofthe comparator proved to perform the best. A useful side effect ofmirroring the

current from the differencing circuit before injecting it into the regeneration stage is that

there is less switching induced n oise injected into reference ladd er.

2.2.2 Comparator circuit

The compar ator circuit in Figure 11 works as follows: During reset, the switches M5a and

M5b disconnect S and R ofthe SR latch from the sensing nodes (aaan d bb). The inputs of the

latch are pulled up to Vdd by M6a and M6b, causing the latch to keep its state.M7 is closed,

equalizing th e sensing node voltages. A mismatch between th e two differential inpu t

voltages causes an u nequal am oun t of current to be injected into th e sensing nodes. When

switch M7 is released, the first regeneration ph ase starts, and the small current imbalance

will cause thecross coupled transistors M3a and M3b to pulld own oneof thesensing nodes.

Then M5a and M5b are opened, and either S or R is pulled to ground, switching the sta te of

(a) (b) (c)Figure 9: Comparator Elements: NMOS Input Pairs (a), Regenerative Flip-Flops (b), SR-Latch (c)

vref2vin1

vbias

iout2

iout1

vref1 vin2

vout2

phi1

phi1phi1

phi2

Vdd

iin2

iin1

vout1

Vdd

Q

S

R Q


17/3614


the SR-latch. The comparator can then be reset again withou t d isturbing its ou tpu t state.

The two n on-overlapp ing clock phases controlling th e comparator are show n in Figure 10.

Making the first regeneration phase longer speeds up the second phase as the second phase

starts with larger difference voltage. However, since the first regeneration phase also adds

to the total comparator response time, making it too long w ill actually slow d own

comparator response. A value of 200ps has been chosen.-

The complete comparator circuit it given in Figure 11. A bias current of 10 A has beenchosen. Trad e-offs exist for the switch sizing: making M5a and M5b large helps p ulling

down the active branch quickly, but increases the glitch size when switching on. The size of

the transistors has to be kept small enough to prevent the glitches from feeding through the

Figure 10: Comparator Timing

Table 3: Transistor aspect ratios and fingering for the comparator circuit (Figure 11)

Transistor W (total) [m] L [m] Number of Fingersa

a. num ber of fingers per transistor in layout of the comparator cell

M0a, M0b, M0c, M0d 1.5 1 2

M1a, M1b 6 2.5 4

M2a, M2b, M2c, M2d 3.6 0.18 4

M3a, M3b 3 0.18 2

M4a, M4b 1 0.18 2

M5a, M5b 1 0.18 2

M6a, M6b 0.24 0.18 1

M7 0.5 0.18 1

M8a, M8b 2 0.18 1

M9a, M9b 2.5 0.18 1

M10a, M10b 3 0.18 1

M11a, M11b 0.24 0.18 1

100 ps

PHI1

PHI2

Reset

5 ns

200 ps


18/36


19/36


20/3617


2.3.2 Flash ADC Performance

Mismatch in the resistor ladder has been mod eled by using normally distributed resistor

values with m ean 500 and 5% stand ard d eviation (). The resistor matching rep ortindicates that N+Poly resistor values will have a of less than 1%. We used 5% tocompensate for the fact that this m odel assum es that th e values of adjacent resistors are

uncorrelated, which is certainly not true on silicon.

Resistor ladder mismatch ( = 5%) has not been included in the INL and DNL plots, as it isdominating the INL and DNL due to the comparators. Its effect on INL and DNL is shown

as dashed lines in Figure 18.

To construct the DNL and INL plots of the 4-bit Flash the mean of the rising and falling

offset with 1 ns reset time has been u sed as effective offset. The hysteresis is assum ed to

introduce a constant difference between rising and falling threshold. The mean value of the

Figure 14: Comparator Offsets in Best Case (1 ns Reset Time)

Figure 15: Comparator Offset Improvement for extended reset time of 1.5 ns

1 2 3 4 5 6 7 8 9 10 11 12 13 14 156

4

2

0

2

4

6Schematic, Best case

Thermometric code

Offse

t[mV]

1.0 V1.05 V1.1 V1.15 V1.2 V

1 2 3 4 5 6 7 8 9 10 11 12 13 14 151.5

1

0.5

0

0.5

1

1.5

2Postlayout, Best case

Thermometric code

Offse

t[mV]

1.1 V

1 2 3 4 5 6 7 8 9 10 11 12 13 14 1515

10

5

0

5

10

15Postlayout, Typical case, 1.5 ns reset

Thermometric code

Offse

t[mV]

1.0 V1.05 V1.1 V1.15 V1.2 V

1 2 3 4 5 6 7 8 9 10 11 12 13 14 1525

20

15

10

5

0

5

10

15

20

25Postlayout, Worst case, 1.5 ns reset

Thermometric code

Offse

t[mV]

1.0 V1.05 V1.1 V1.15 V1.2 V


21/36


22/3619


To find the maximum sampling frequency of the 4-bit DAC, the sampling frequency has to

be swept for a fixed input frequency (wh ich has to be lower than h alf the lowest sampling

frequency tested ). The samp ling frequency at which the SNR decreases by 3 dB can be

regarded as th e converter s maximum sampling speed. Because the comparator response

time (Figure 16) and reset t ime sum up to almost 2 ns, this maximum frequency is expected

to be around 500 MHz. In the pipeline, how ever, only the response time is critical, as the

comparators can be reset while the DAC and the Residue Amplifier are working (Figure 5).

For a more complete characterization of the converter, SNR as a function of inpu t signal

amp litude (at constant input an d sampling frequencies) does also have to be simulated.These simulations have not yet been d one.

Figure 18: 4-bit Flash DNL and INL (post-layout simulation)

Figure 19: 4-bit Flash SNR for Typical case (post-layout)

2 3 4 5 6 7 8 9 10 11 12 13 14 150.04

0.03

0.02

0.01

0

0.01

0.02

0.03

0.04

0.05

0.06Flash DNL (post layout simulation)

Thermometric code

DNL[LSB]

Typcial caseWorst caseBest caseResistor ladder

2 3 4 5 6 7 8 9 10 11 12 13 14 150.05

0.04

0.03

0.02

0.01

0

0.01

0.02

0.03

0.04

0.05Flash INL (post layout simulation)

Thermometric code

INL[LSB]

Typcial caseWorst caseBest caseResistor ladder

11 22 33 44 55 66 77 88 9919

20

21

22

23

24

25

26SNR of Flash ADC

Input frequency [MHz]

SNR[dB]

SNR of ADCQuantization Noise Limit


23/3620


3 4-bit Digital-to-Analog Converter

Because there are no accurate capacitors available, the DAC is not implem ented as an

MDAC as in [4], but as a current-steering DAC. Using a current steering DAC will greatly

increase the power consump tion of the converter compared to an imp lementation using acapacitive MDAC (which has no static current consum ption).

Matching of unit-current cells is very critical because DAC linearity directly depends on the

matching of the unit currents. Special care has to be taken when layout out the current cells

(see Section 3.1.2). Since the gain is controlled by the absolute values of the unit current and

the load resistors, a calibration feedback is absolutely needed.

Using non-weighted current cells simplifies design as the flash output can directly be used

for controlling the current cells. Depending on the current cell, a simple deglitching circuit

may have to be employed: when sw itching the current between the outpu t branches

(Figure 20), there must always be a path for the current d rawn by the current source

transistor. If the current path is blocked, the transistor will leave saturation; reestablishingthe current w ill then take som e time, causing a glitch in the outp ut voltage.

The DAC output needs bu ffering because it mu st drive the large input capacitance of the

Residu e Amp lifier. The bu ffer needs precise gain of 1 and large ou tput sw ing. Since the

OTA(s) in the buffer will be used in unit gain configuration, the OTA(s) will also need large

input signal swing.

A resistor ladd er DAC was also tested , but then rejected because of insu fficient resistor

matching accuracy, and because it wou ld have n eeded to introd uce an encoder into the

analog signal path, thu s increasing d elay.

3.1 Current-steering D/A Converter

The schematicof the current-steering DAC is given in Figure 20. Its output voltage is given

by:

(5)

(6)

wh ere n is the therm ometric outpu t value of the Flash, R the load resistance, I0 the unit

current, and N = 15. I1 is a DC cur rent used to adjust the common mode level of the output

voltage. R and I0 have to be chosen to obtain the required gain. The values used here are R

= 1250 , I0 = 50 A, and I1 = 185 A.

3.1.1 Continuous DAC Gain Calibration

Continuou s calibration on ly needs to regu late a DC level and can thus be slow. However,

the slow feedback will also take a long time to recover from glitches injected on the reference

node.

Calibration is done u sing a unit current cell and du mm y resistor identical to load resistors

to set the n ominal voltage of the vref control p in to Vdd-0.5LSB (1.7375 V). Due to voltage

vod vou t1 vou t2 RI0 2n N( )= =

voc

vou t1 vou t2+

2------------------------------- Vdd

N I0

2RI1

+

2----------------------------= =


24/3621


drops in the power rails and feedback amplifier offset, this voltage will have to be adjusted

to obtain a gain of precisely 8.

No h igh gain needed in the feedback amp lifier since Vdd seen by du mm y resistor is

different from the external Vdd due to resistive voltage drops. Vref will have to be adjusted

from the outside anyway, so static offset at amplifier input not a problem. Because the inputs

of the amp lifier are very close to Vdd, an NMOS input pair w ith folded cascode has been

chosen, which does not need a diode connected tran sistor as load at drains of inp ut

transistors. Only one stage is used to simplify stabilizing the feedback loop: The current

source gate node va has a large capacitive load (4-5pF), and thus has to be the dominant pole

node. A two stage folded cascode opamp would provide higher gain but would be hard to

compensate.

Figure 20: Current-steering DAC with continuous gain calibration

Figure 21: Feedback amplifier for continuous DAC calibration

va

Q1Q1

I0

Q2

I0

Q2 0 01 1 0 01 1 01 Q15I0Q15+

0 0 0 0 0 0 0 0 0 01 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 01 1 1 1 1 1 1 1 10 0 0 0 0 0 0 0 01 1 1 1 1 1 1 1 1I01 0 I1 I1

vout1

vout2

Unit Current Cells

Rdummy

R R

vref

vcasc

Ibias

M7b

M8a M8b

vout

M6a M6b

M5a M5b

vrefvinM0a M0b

M1

M7aM4

M3M2

vcasc


25/36


26/36


27/36


28/3625


matching. No gain calibration m echanism is imp lemented. A simple mechanism u sing

capacitor banks w ould require too many external pins for the first prototype

implementation of the converter stage.

4.1 Switched Capacitor Residue Amplifier

4.1.1 Circuit Topology

The circuit topology in Figure 26 has been chosen because it allows holding the ou tpu t

voltage while sampling the first differential voltage. This is important because the output of

Figure 25: DNL and INL of current-steering DAC

Figure 26: Topology of Switched-Capacitor Residue Amplifier and Sample-and-Hold Circuit

1 2 3 4 5 6 7 8 9 10 11 12 13 14 154

2

0

2

4

6

8

10

12x 10

4 DAC DNL

Thermometric code

INL[LSB]

Typical caseWorst caseBest case

1 2 3 4 5 6 7 8 9 10 11 12 13 14 155

0

5

10

15

20x 10

3 DAC INL

Thermometric code

DNL[LSB]

Typical caseWorst caseBest case

1a

+

+

C1a

C1b

vout1

vout2

C2a

R

C2b

R

2b

2b

1bvbias

1a2a

1b

2a

vdac2

v2

vdac1

v1

vbias


29/3626


the Residue Amplifier is connected to the analog input of the next pipeline stage,w hile one

ofthe inputs of the Residue Amplifier has to sample the output value ofthe previous stage.

It it thus necessary to sample the inpu t voltage while holding the ou tpu t voltage constant

for the next stage.

The differential and common-mode output voltages under ideal cond itions (no charge

injection) are given in Equations (7) an d (8). v0 represents the analog ground voltage used

while sampling v1 and v2 (vbias in Figure 26), an d v0 represents the virtual analog ground

voltages imp osed by th e negative feedback around the OTA. Ideally v0 and v0 should be

equal. Two separate voltages have been introduced for the derivation of Equations (7) and

(8) in order to study the effect of mismatch between vbias and th e OTA outpu t comm on

mod e voltage.

(7)

(8)

If capacitors C1a and C1b, and C2a and C2b are perfectly matched, Equations (7) and (8)

simplify to the expressions given by (9) and (10). It is interesting to note that un der th ese

conditions, a mismatch betw een v0 and v0 only has an influ ence on the comm on-mode

output signal only. The differential output voltage is unaffected. This means that the

common m ode feedback of the OTA (see Section 4.2) doesnt not need to align the outp ut

common m ode to analog ground with very high p recision. This greatly simplifies the

high-speed common-mod e feedback design, as high gain is not required.

(9)

(10)

The circuit in Figure 26 uses a conventional differencing circuit to form the difference of the

two differential input voltages. As seen in (10), this circuit d oes not reject the differential

common-mode inpu t voltage (i.e. the d ifference between th e common-mod es of the two

differential inputs). A configuration based on the differencing circuit proposed in [14]

would provide better common-mode rejection but require more switches and clock phases.

Because the common mod es of the inpu t signals are app roximately aligned, and the

following stage (Flash ADC) provides some common mode-rejection, common-moderejection is not critical in the Residu e Amp lifier. The simp le conventiona l circuit is thus

used . The clocking schem e for this circuit is includ ed in Figure 5.

4.1.2 Charge Injection of MOS Switches

Equations (7) and (8) are derived using charge conservation in the sampling capacitors. The

switches are assum ed n ot to absorb or release any charge when tu rned on or off. For

switches imp lemented w ith MOS transistors, however, this assump tion is not true. The

charge forming the transistor s channel when in on-state is released w hen to source, drain

and bulk (substrate) node of the transistor, potentially d isturbing the voltage levels on the

sampling capacitors. How the charge is distributed betw een these nodes depend s on the

vod vou t1 vou t2C

1a

C2a

--------- v1

vda c1 v0 v0+( )C

1b

C2b

--------- v2

vda c2 v0 v0+( )= =

vocvou t1 vou t2+

2------------------------------- v

0 C1a

2C2a

------------ v1

vda c1 v0 v0+( )C1b

2C2b

------------ v2

vda c2 v0 v0+( )+ += =

vod vou t1 vou t2

C1

C2------

v1 vda c1

v2

vda c2+

( )= =

voc

vou t1 vou t2+

2------------------------------- v

0

C1

C2

------v

1v

2+

2----------------

vda c1 vda c2+

2-------------------------------- v

0 v

0+

+= =


30/3627


impedance of these nodes seen by the transistor, the rise or fall time of the gate voltage, and

on the source and drain potential of the switch. Charge injection is thus difficult to predict,

and because it is signal dep end ent, it is difficult to cancel its effects even u sing fully

differential circuits.

Note that high speed (small time constant C/ g) entails large amoun ts of injected charge

because the amount of injected charge and the switch on-resistance are linked (Equation

(11)).

(11)

Note that ideally, the switches should only introduce common mode charge injection errors

wh ich w ill be rejected by the inpu t stage of the comparators of the next p ipeline stage.

However, because the amount of injected charge is signal dependent, differential errors will

still occur.

Techniques for charge injection cancellation:

Use shorted d umm y transistors on high imped ance node side to absorb the injected

charge. The dum my transistor has to be turned on when the switch transistor is

turn ed off.

Use bootst rapped switches [8]: this makes the injected charge almost independent of

signal level. Thu s, if the circuit topology is such that all injected charge results in a

common mode error, this may allowing at least partial error cancellation; however,

bootstrapped sw itches are comp lex to implement

Choose large capacitors to reduce effect of injected charge on voltage. However, to

keep th e speed of the circuit constan t, this also requires scaling of the switch

transistors, resulting in more injected charge.

Bottom plate sampling (series samp ling): sample against a constant potential to

reduce signal dependency of error [8].

4.1.3 Capacitor and Switch Sizing

From Equation 9 it can be seen that the rat io of C1/ C2 needs to be 8 for a gain of 8. The

capacitors should be large enough to allow precise matching of C1 and C2, and small

enough to keep the Residu e Amp lifier settling time short enough for 200 MHz samp ling

rate (ideally less than 2 ns only). A value of100 fF has been chosen for C1, requir ing in C2 =

800 fF.

CMOSswitches are used to implement all switches in Figure 26. This allows the switches to

work properly over the wh ole signal range. The gate overdrive of the switch tran sistors in

on-state is small due to the relatively low Vdd of 1.8 V. This results in large on-resistance of

the sw itches, which in tu rn requires the switch transistors to be large. Large transistors,

however, will aggravate charge injection errors and increase the parasiticcapacitances in the

switched-capacitor circuit. Bootstrapped switches [8] could ease this problem but ad d

complexity. The idea of bootstrap ped switches is to boost the gate voltage of the switch

transistor so its gate overdrive is always Vdd-Vth when in on-state. This reduces the signal

dependency of on-resistance and injected charge, and allows use of smaller switch

transistors for a given required on-resistance (the amount of injected charge is not reduced

by the bootstrap ping technique, as can be seen from (1)).

gonQ

L2

--------=


31/3628


The effects of different capacitor and switch sizes will have to be investigated further, as

these parameters are very critical for Residue Amplifier speed and accuracy.

4.2 Differential OTA

Switched capacitor residu e amp lifier needs fully d ifferential Opamp with high GBW and

slew rate. A class ABtopology is thus used instead ofinstead ofclass A amplifier. However,

the conventional class ABoutput stage push-pull source followers do not work because of

the low supply voltage. Since the nom inal outpu t range of the residue amp lifier is limited

to half the 1 V peak-to-peak r ange (du e to bit overlapp ing), the differential OTA does not

necessarily need a rail-to-rail outp ut stage, but can u se cascodes, allowing h igh gain an d

large GBW with few stages. However, especially PMOScascodes are critical,since they need

to be large because there is only about 400 mV headroom to Vdd , and since the carrier

mobility in PMOS transistors is much lower than in NMOS transistors.

Single stage amp lifier are an interesting choice because they can have only one high

imped ance node at the outpu t. The load capacitance will then slow d own th e dominan t

pole, improving stability. In a classical two stage op-amp, the load capacitance affects the

non-dom inant pole that one w ishes to push to high frequency.

To speed up a switched-capacitor circuit one has to increase both Gm and Islew (or decrease

C, which is bad for noise). An OTA GBW requirement estimation formu la is presented see

[8]. The simple first order mod el used there predicts a required GBW of around 10GHz,

which is not p ractical. With a m ore complex circuit topology, it is hop ed to achieve fast

settling even w ith a significantly lower GBW of only ap proximately 1 GHz. Because the

OTA in theResidue Amplifier is used with a feedback factor f < 1, the phase margin required

for stability is not the phase at the unit gain frequency, but at the frequency corresponding

to a gain of 1/ f. This simp lifies achieving a su fficient p hase margin.

The slew rate requirement on the OTA is tightened by the fact that the output is reset in each

cycle. The output voltage may have to change by up to half the output peak-to-peak value

(here: Vmax = 250mV).

(12)

The required slewing current can be estimated from (12), where ISR is the slewing current

available, Ts is the time available for settling, and Vmax the voltage swing. If a third of the

settling time is used for slewing, k=3.

4.2.1 Mirrored cascode with class AB input stage with preamplifier

Simple Folded Cascode and Mirrored Cascode topologies have been evaluated, but found

to either provide insufficient slewing current or a too small GBW. Finally, a topology using

a class ABinput stage [9] was adopted since the required voltage swing at the OTA input is

small.

A low-gain high-speed input am plifier (Figure 29) is used as a p reamplifier to the OTA to

take advan tage of AB inpu t stage. The inp ut signal has very limited swing, which p ermits

ISRk V ma xCL

TS--------------------------=


32/3629


not folding the amplifier, but also doesnt fully unbalance the input pair to take advantage

of the class AB structure.

Figure 29 (b) shows the imp lementation of the common-mod e feedback am plifier.

Figure 27: Overall structure of the Residue Amplifier differential OTA

Figure 28: Low-Voltage differential class-AB mirrored cascode OTA

(a) Preamplifier (c) Common-mode feedback amplifier

Figure 29: Preamplifier and common-mode feedback amplifier for differential class-AB OTA

Residue Amplifier OTA

+

+

classAB

OTA

+

+

pre

Amplifier

Commonmode

feedback amplifier

vout

vout+

in2

vin1

vin+

vin cm

fb

vout

M4b

M7a

M6avp

vnM5a

M4a

M11b

M9a

M11b

M8a

M1a

M10a

M2a

M0a M0b

M2b

M3a M3b

vinvin+

cmfb

vout+

M10b

M1b

M8b

vbias2vbias2

vbias1 vbias1M9b

vp

vnM5b

M6b

M7b

M1c

M0a M0b

vin+ vin

vout+vout

Rc

Cc

Rc

Cc

M1bM1aM1d

M1bvout

M3vbias

vin2M0bM0a

M1a

M0c M0d

vcmref

M2a M2b

vin1

M4


33/3630


5 Top-Level Floorplanning

Since the design is only a first p rototyp e, no self-conta ined b iasing circuitry has been

designed. An external pin is used to adjust the bias current levels, another p in is used to

observe the current. Since all bias currents u sed are multip les of 10uA, they can easily bederived from the externally controlled reference current.

5.1 Analog Pipeline Stage Floorplan

Figure 30shows the placement of the different blocks in the analog pipeline stage. Note that

the encoder is not in the analog signal path, but has been put between Flash ADC and DAC

to minimize routing.

5.2 Floorplan of complete pipeline

Figure 31shows the floorplan of the complete converter pipeline. The structure from [4] has

been preserved. Note that analog and digital I/ Os lie on opp osite sides of the block.

Figure 30: Floorplan of analog pipeline stage

Clock

analog

input

analog

output

binary

output

Enco

der

Currentsteering DACFlash ADC SC Residue Amplifier

DAC Output Buffer

1

ref. input

Clock


34/3631


Figure 31: Overall floorplan of the pipelined ADC

DIGITAL I/O

Flas

hADC

Enco

der

Enco

der

Currentsteering DAC

DAC Output Buffer

Residue Amplifier

Flas

hADC

Enco

der

Currentsteering DAC

DAC Output Buffer

Residue Amplifier

Flas

hADC

Enco

der

Currentsteering DAC

DAC Output Buffer

Residue Amplifier

Flas

hADC

Digital Error

Correction Block

Clock distribution and buffering

Digital Error Correction BlockDigital Error Correction Block

Digital Error Correction Block

Analog Pipeline Stage 3 Analog Stage 4Analog Pipeline Stage 2Analog Pipeline Stage 1

ANALOG I/O

POWERan

dCLOCK

POWERan

dCLOCK


35/3632


6 Conclusions

In the limited time available for this project only a part of the ADC could be redesigned.

Circuit design ofthe 4-bit ADC and DAC has been finished, and floorplans for the layout of

these blocks have been elaborated. The layout of the comparator used in the Flash has beencompleted and post-layout simu lations have been carried out to verify the design.

A switched-capacitor topology for the Residue Amplifier has been chosen, but the required

OTA is still in the d esign phase. The correct switch and capacitor sizes also yet have to be

found . First simulation results on th e Residue Amp lifier circuit indicate that the sam pling

speed specification may have to be relaxed.

For the p rototype of the p ipeline stage, at least the Flash and ADC converter will be

finished. If a Residue Am plifier is to be included , a DAC output buffer has to be d esigned

as well.

As only one stage will be implemented, only the thermometric-to-binary encoder will haveto be included , the error correction using at least two pipeline stages.

The full design of a high-speed pipelined differential ADC clearly exceeded the amount of

work that could be don e in only 4 month s time. Especially because a large portion was

needed to learn how to use the software tools.Many important aspects ofa thorough design

have not been addressed. For example, no noise analysis for the different circuit blocks has

been carried ou t.

Lausanne, February 20, 2004

Thomas Liechti


36/36


References

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Documents

Liechti Report 2004