LETTER IEICE Electronics Express, Vol.10, No.20, 1 9 ... · supply reference clock are high-power consumption. The power consump-tions of conventional phase locked loop (PLL), and

Design of low-power clockgenerator synchronizedwith AC power for adiabaticdynamic CMOS logic

Seung-Il Cho1a), Seong-Kweon Kim2, Tomochika Harada1,and Michio Yokoyama11 Graduate School of Science and Engineering Yamagata University4–3–16 Jonan Yonezawa Yamagata 992–8510 Japan2 Department of Electronic and IT Media Engineering Seoul National University ofScience and Technology 138 Gongneunggil Nowongu Seoul 139–743 Koreaa) chosiyzyamagatauacjp

Abstract: To reduce the power dissipation in conventional CMOS

logic and to maintain adiabatic charging and discharging with low

power for the adiabatic dynamic CMOS logic (ADCL), the clock

signal of logic circuits should be synchronized with the AC power

source. In this paper, the low-power clock generator synchronized

with the AC power signal is proposed for ADCL system. From the

simulation result, summation of power consumption of the designed

wave shaping circuit (WSC) and asymmetry duty ratio divider

(ADD) was estimated with approximately 1.197μW and 58.1μW at

3 kHz and 10MHz, respectively.

Keywords: synchronization, low-power clock generator, adiabatic

dynamic CMOS logic (ADCL), wave shaping circuit (WSC),

asymmetry duty ratio divider (ADD)

Classification: Integrated circuits

References

[1] W. C. Athas, L. J. Svensson, J. G. Koller, N. Tzartzains and E. Y. C.

Chou: IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2 [4] (1994) 398.

[2] A. G. Dickinson and J. S. Dencker: IEEE J. Solid-State Circuits 30 [3]

(1995) 311.

[3] S.-I. Cho and M. Yokoyama: Proc. 2nd Int. Symp. GCSS2012 (2012) 27.

[4] S.-I. Cho, T. Harada and M. Yokoyama: IEICE Electron. Express 9 [20]

(2012) 1576.

[5] Z. Xianwen, W. Zhigong, X. Jian and T. Lu: Proc. 12th Conf. IEEE ICCT

(2010) 1027.

[6] J. Lim, K. Lee and K. Cho: Proc. ESSCIRC (2010) 274.

[7] D. Sheng, C.-C. Chung and C.-Y. Lee: IEEE Trans. Circuits Syst. II, Exp.

Briefs 54 [11] (2007) 954.

[8] W.-M. Lin, C.-C. Chen and S.-I. Liu: Proc. Int. Symp. VLSI-DAT ’09

(2009) 251.

[9] M.-J. Kim and L.-S. Kim: IEEE Trans. Circuits Syst. II, Exp. Briefs 58 [8]

(2011) 477.

IEICE Electronics Express, Vol.10, No.20, 1–9

1

© IEICE 2013DOI: 10.1587/elex.10.20130716Received September 13, 2013Accepted September 27, 2013Publicized October 09, 2013Copyedited October 25, 2013

LETTER

[10] J. Choi, S. T. Kim, W. Kim, K.-W. Kim, K. Lim and J. Laskar: IEEETrans. Very Large Scale Integr. (VLSI) Syst. 19 [4] (2011) 701.

1 Introduction

The demand for research of consumer products; personal digital assistant(PDA), smart phone, table PC, etc has been growing up by the

development of a high rate data communication (HRD) and a large scale

integrated circuits (LSI). A lot of studies have been performed for a high

integration and low-power consumption due to the portability and the

limitation of battery capacity.

　 The adiabatic logics have been studied to reduce the power dissipation

in conventional CMOS logic for low-power design of logic circuits [1, 2]. In

particular, the adiabatic dynamic CMOS logic circuit (ADCL) achieves

ultra low energy dissipation by restricting current to flow across devices

with low voltage drop and by recycling the energy stored on their

capacitors [3, 4]. It is known that output voltage of the ADCL gates is

synchronized with the power supply voltage.

　 In reference [4], a low-power synchronizer circuit was proposed using the

designed ADCL buffer when an alternate current (AC) power supply and a

clock generator are designed respectively. On the other hand, a low-powerclock generator synchronized with the AC power signal is proposed for

ADCL system using defined synchronization conditions and phase margin

between clock and AC power by ADCL architecture in this paper.

　 The AC power supply, clock generator, and synchronous circuit are

needed in power part of ADCL system. The oscillation circuits or

temperature compensate crystal oscillator (TCXO) commonly used to

supply reference clock are high-power consumption. The power consump-tions of conventional phase locked loop (PLL), and delay locked loop

(DLL) used for the synchronization of signals are very large [8, 9, 10].

However, proposed circuit that makes AC power signal into clock signal

synchronized with the AC power signal reduces power consumption of

power part in ADCL system by decreasing the number of generators and

using simple circuit instead of conventional PLL and DLL.

2 Adiabatic logic

2.1 Adiabatic chargingDuring a sudden transition between high and low levels of input voltage, a

load capacitor cannot be charged and discharged immediately. A power

dissipation is incurred by resistive component of logic circuit in the

conventional CMOS logic, because this logic circuit uses a constant voltage;direct current (DC) power supply. In order to minimize the power

dissipation, an adiabatic charging is one of promising candidates with AC

power which has slower rising/falling time than charge/discharge time

constant [1, 2, 3, 4].

　 Figure 1 shows operations at a normal RC circuit with DC signal,

adiabatic charging, and unsynchronization. Input signal vI(t), voltage drop

of resistance vR(t) and power dissipation PR(t) at Fig. 1 (a) are


2


vI tð Þ ¼ VI

�tþ �ð Þ u tð Þ � u t� � � �ð Þð Þ½ � þ VI u t� � � �ð Þð Þ½ �; (1)

vR tð Þ ¼ RCVI

�1� e�

tCR

� �� 1� e�

t� ��ð ÞCR

� �u t� � � �ð Þð Þ

h i

þ VI�

�e�

tCR ;

(2)

PR tð Þ ¼ R

�CVI

�1� e�

tCR

� �� 1� e�

t� ��ð ÞCR

� �u t� � � �ð Þð Þ

h i

þ VI�

�Re�

tCR

�2 (3)

where τ is rising time of input, � is unsynchronized period and u tð Þ is unitstep function [4].

　 In the case of DC signal(� ¼ �) at input signal, large power dissipation

is shown in Fig. 1 (b). However, in the case of AC signal(� ¼ 0) at input

signal, adiabatic charging and little power dissipation are shown in

Fig. 1 (c). The region of adiabatic charging is decreased by increment of �

of AC signal as shown in Fig. 1 (d).

2.2 Adiabatic dynamic CMOS logic (ADCL)The ADCL circuits consist of CMOS logic, AC power and two diodes to

keep high and low levels [3, 4]. An ADCL inverter gate is shown in Fig. 2. In

this circuit, since the output voltage of ADCL gate is synchronized with

power supply Vphi, operating speed of the ADCL circuits is determined by

frequency of Vphi. In addition to adiabatic charging, charge reuse is also

effective to low-power consumption in ADCL. The charge can be reused

because the charge reverts to the power source at discharging of load C.

　 In order to maintain the output voltage level, the ADCL has two diodes

per a logic gate. ADCL has the following characteristics by those diodes; 1)swing width of the output signal is reduced to VI�(VD1+VD2) by cut-in

Fig. 1. (a) RC circuit, (b) DC signal, (c) adiabatic

charging, (d) unsynchronization


3


voltage VD of those diodes. 2) At the load capacitor, the charge and

adiabatic operation begin when AC power is higher than VD.

　 As shown in Fig. 3 (a), although pull-up network has been become by

input signal, the adiabatic charging doesn’t begin when AC power is less

than VD1+VD2. However, the adiabatic charging begins when AC power is

higher than VD1+VD2. On the other hand, as shown in Fig. 3 (b), although

pull-down network has been become by input signal, the adiabatic

discharging doesn’t begin when AC power is higher than VI�(VD1+VD2).

However, the adiabatic charging begins when AC power is less than VI�(VD1+VD2).

　 In the ADCL, synchronization conditions between input signal and AC

power are following; AC power is increased from VD1+VD2 at pull-upnetwork where input signal changes to low from high level. And AC power

is lowered from VI�(VD1+VD2) at pull-down network where input signal

changes to high from low level.

　 There is no power consumption because no current flows when AC

power is smaller than VD1+VD2 at pull-up network. Hence, there is no effect

anywhere on the output signal and the power consumption of the region

where it is less than VD1+VD2, even though present is the pull-up network

as shown in Fig. 4 (a), (b). However, adiabatic charging period has reduced

and non-adiabatic period appears, if synchronization conditions are not

satisfied as shown in Fig. 4 (c). This leads to high power consumption.

　 The region without effect on the change of output signals and power

consumption would be defined as the margin of the synchronization. The

range of region, �m is

Fig. 2. (a) input: H → L, (b) input: L → H, (c) Operation

waveforms

Fig. 3. Waveforms (a) Adiabatic charging at pull-upnetwork (b) Adiabatic discharging at pull-downnetwork


4


�VD1 þ VD2

VI� � �m � VD1 þ VD2

VI� (4)

Conventional rigid synchronization conditions between input signal and

AC power are changed to simple one using phase margin of synchroniza-tion. Furthermore it is possible to determine design specifications of

synchronizer flexibly.

2.3 Power source of ADCL systemA synchronous circuit is needed for adiabatic charging when an AC power

supply and a clock generator are individually designed as shown in

Fig. 5 [4]. Conventional PLL and DLL are used for the synchronization of

signals. However, the power consumptions of them are very large; dozens ofmW [8, 9, 10]. Hence, the power source which has both synchronization and

low-power consumption should be used for the ADCL system.

3 Design of low-power clock generator for ADCL system

In this section, a low-power clock generator synchronized with the AC

power supply is proposed for ADCL system. The minimum energy

consumption in an ADCL is realized when relation between AC power

supply and the clock signal satisfies synchronization conditions and phase

margin as explained in section 2. In this case of synchronization, the

adiabatic charging and low power can be achieved in the ADCL.

　 Figure 6 shows the proposed low-power clock generator using the

designed wave shaping circuit (WSC) and asymmetry duty ratio divider

(ADD) for the ADCL system. While the output of a separate clock

generator is synchronized with the output of individual AC power supply

by synchronizer circuit as shown in Fig. 5, that separate clock generator is

unnecessary in the proposed generator because it makes output signal of

AC power supply into clock signal synchronized with AC power signal. The

proposed circuit reduces power consumption of power part in ADCL

Fig. 4. Waveforms at pull-up network (a) synchronization

0 � � � �mþ (b) synchronization �m� � � � 0 (c)

non-synchronization � > �mþ

Fig. 5. The power source using a synchronizer for ADCL


5


system by decreasing the number of generators and using simple circuit

instead of conventional PLL and DLL.

　 In order to replace unnecessarily separate clock generator, the WSC is

designed, which makes the AC power signal into clock signal using

synchronization conditions and phase margin of ADCL. When the input

voltage is higher than a certain chosen threshold voltage

Vtþ � VI � VD1 þ VD2ð Þ, the output becomes high. When the input is

below a lower chosen threshold voltage Vt� � VD1 þ VD2, the output is low.

When the input is between Vt+ and Vt�, the output retains its value as

shown in Fig. 7.

　 The ADD is designed to divide frequency of clock signal ; output signalof the WSC. Frequency ratio between the AC power signal and clock signal

should be ‘odd:1’ for the ADCL as shown Fig. 8 (a). The output signal of

WSC should be a divide-by-odd. However, an odd-divider is usually very

complex and has large power consumption. Therefore, ADD is proposed,

which controls a duty ratio of the output signal to be 4.5:5.5, by using

positive edge and negative edge divider of a divide-by-even. The ADD is

designed using 306 MOS transistors whose sizes are 0.22μm/0.18μm(W/L)

Fig. 6. The proposed low-power clock generator synchro-nized with the AC power signal for ADCL system

Fig. 7. Input and output signal of WSC

Fig. 8. (a) odd:1 (duty ratio 5.5:5.5), (b) the asymmetry

duty ratio divider (duty ratio 4.5:5.5)


6


for all transistors. This leads to simple structure and low-power operation.Figure 8 (b) shows timing chart of designed ADD. The output of ADD is

found to synchronize with AC signal at rising and falling of the output for

adiabatic charging.

4 Simulation result and evaluation

The proposed low-power clock generator synchronized with the AC power

signal for the ADCL has been simulated using a 0.18μm standard CMOS

technology and hspice. Figure 9 shows the result of simulation. The

operations of designed WSC and ADD have been confirmed by simulation

in Fig. 9 (b) and (c). Furthermore, the clock signal synchronized with the

AC power signal was confirmed for the ADCL as show in Fig. 9 (d).

　 In order to confirm operation of total ADCL system with the proposed

clock generator, it and the ADCL 3-bit PWM of Ref. [3] are simulated using

a 0.18μm standard CMOS technology and hspice as shown in Fig. 10.

Operation of proposed clock generator and the ADCL system has been

confirmed as shown in Fig. 11.

　 Power consumption of the proposed low-power clock generator for the

ADCL is compared with that of other clock generators having synchroni-zation. Table I summarizes several specifications of clock generators in

Clock Gen. group and synchronous circuits in Sync. circuit group. It shows

that the power consumption of proposed low-power clock generator in this

Fig. 9. Output waveforms (a) AC power supply,

(b) designed WSC, (c) ADD, (d) An overlap

between (a) and (c)

Fig. 10. ADCL 3-bit PWM system with proposed clock

generator


7


work is lower than summation of power consumption both the lowest in

Clock Gen. group; 0.36μW [6] and the lowest in Sync. circuit group using a

PLL or a DLL; 16mW [9]. However, the power consumption of clock

generators with proposed synchronization for only ADCL in Ref. [4] instead

of a PLL or a DLL is lower than that of this work. Although, proposed

clock generator has a demerit in way of power consumption it has more

merits than individually designed types as shown in Fig. 5 like the

following;1) To design a separate clock generator is unnecessary, because the WSC

of proposed generator makes output signal of AC power supply into clock

signal clock synchronized with AC power signal.

2) It is possible not only to change the clock frequency as to change the

frequency of AC power supply but also to satisfy synchronization

conditions of ADCL in the proposed generator, because clock is made into

1/10 frequency of AC power signal, while oscillation frequency of Ref. [6] is

fixed

3) To be flexible in dealing with ADCL applications is possible due to

changing the clock frequency.

4) The size of proposed generator that consists of both WSC of simple

architecture and ADD having 308 MOS transistors is smaller than that of

Ref. [4] and [6] having big size capacitors.

Fig. 11. Output waveforms (a) OSC core, (b) the

proposed low-power clock generator, (c) ADCL

3-bit PWM (input bit 100), (d) ADCL 3-bitPWM (input bit 110)

Table I. Comparison of power consumptions


8


5 Conclusion

A proposed low-power clock generator synchronized with the AC power

signal has been proposed for ADCL system. The WSC has been designed,

which makes the AC power signal into clock signal and can synchronize for

adiabatic charging. Furthermore, the ADD has been designed to divide

frequency of output signal of the WSC for ADCL. The power consumption

of proposed low-power clock generator was approximately 58.1μW at

10MHz. Proposed clock generator was found to be less power consumption

than the other clock generators with a PLL or a DLL. Furthermore, it was

found to have many merits, although power consumption of it was larger

than that of clock generators with proposed synchronization for only

ADCL in Ref. [4].

Acknowledgments

The VLSI chip in this study has been fabricated in the chip fabrication

program of VLSI Design and Education Center (VDEC), the University of

Tokyo in collaboration with Rohm Corporation and Toppan Printing

Corporation.


9


Documents

LETTER IEICE Electronics Express, Vol.10, No.20, 1 9 ... · supply reference clock are high-power consumption. The power consump-tions of conventional phase locked loop (PLL), and