Highly Reliable, High Speed and Low Power NAND Flash Memory Based Solid State Drives (SSDs) 2012 IEICE Electronics Express

REVIEW PAPER IEICE Electronics Express, Vol.9, No.8, 779–794

Highly reliable, high speedand low power NAND flashmemory-based Solid StateDrives (SSDs)

Ken Takeuchia), Teruyoshi Hatanaka, and Shuhei TanakamaruDepartment of Electrical Engineering and Information Systems,

Graduate School of Engineering, University of Tokyo,

7–3–1 Hongo, Bunkyo-ku, Tokyo 113–8656, Japan

a) [email protected]

Abstract: SSDs and emerging storage class non-volatile semicon-ductor memories such as PCRAM, FeRAM, RRAM and MRAM haveenabled innovations in various nano-scale VLSI memory systems forpersonal computers, multimedia applications and enterprise servers.This paper provides a comprehensive review on various state-of-the-art memory system architectures and related memory circuits for thehighly reliable, high speed and low power NAND flash memory basedSSDs.Keywords: SSD, NAND flash memory, storage class memory, ECC,signal processingClassification: Integrated circuits

References

[1] K. Takeuchi, “Novel Co-design of NAND Flash Memory and NANDFlash Controller Circuits for sub-30nm Low-Power High-Speed Solid-StateDrives (SSD),” IEEE J. Solid-State Circuits, pp. 1227–1234, 2009.

[2] S. Tanakamaru, C. Hung, A. Esumi, M. Ito, K. Li, and K. Takeuchi,“95%-Lower-BER 43%-Lower-Power Intelligent Solid-State Drive (SSD)with Asymmetric Coding and Stripe Pattern Elimination Algorithm,” Int.Solid-State Circuits Conference (ISSCC ), pp. 204–205, 2011.

[3] S. Tanakamaru, A. Esumi, M. Ito, K. Li, and K. Takeuchi, “Post-manufacturing, 17-times Acceptable Raw Bit Error Rate Enhancement,Dynamic Codeword Transition ECC Scheme for Highly Reliable Solid-State Drives, SSDs,” International Memory Workshop (IMW ), pp. 88–91,2010.

[4] M. Fukuda, K. Higuchi, S. Tanakamaru, and K. Takeuchi, “3.6-TimesHigher Acceptable Raw Bit Error Rate, 97% Lower-Power, NV-RAM& NAND Integrated Solid-State Drives (SSDs) with Adaptive CodewordECC,” Int. Conf. Solid State Devices and Materials (SSDM ), pp. 1166–1167, 2010.

[5] K. Ishida, T. Yasufuku, S. Miyamoto, H. Nakai, M. Takamiya, T. Sakurai,and K. Takeuchi, “1.8 V Low-Transient-Energy Adaptive Program-VoltageGenerator Based on Boost Converter for 3D-Integrated NAND,” IEEE J.Solid-State Circuits, pp. 1478–1487, 2011.

c© IEICE 2012DOI: 10.1587/elex.9.779Received February 16, 2012Accepted March 12, 2012Published April 25, 2012

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IEICE Electronics Express, Vol.9, No.8, 779–794

[6] T. Hatanaka, K. Ishida, T. Yasufuku, S. Miyamoto, H. Nakai, M.Takamiya, T. Sakurai, and K. Takeuchi, “A 60% Higher Write Speed,4.2 Gbps, 24-Channel 3D-Solid State Drive (SSD) with NAND FlashChannel Number Detector and Intelligent Program-Voltage Booster,”Symp. VLSI Circuits, pp. 233–234, 2010.

[7] T. Hatanaka and K. Takeuchi, “4-Times Faster Rising VPASS (10 V), 15%Lower Power VPGM (20 V), Wide Output Voltage Range Voltage Gener-ator System for 4-Times Faster 3D-integrated Solid-State Drives,” Symp.VLSI Circuits, pp. 200–201, 2011.

[8] K. Takeuchi, Y. Kameda, S. Fujimura, H. Otake, K. Hosono, H. Shiga,Y. Watanabe, T. Futatsuyama, Y. Shindo, M. Kojima, M. Iwai, M.Shirakawa, M. Ichige, K. Hatakeyama, S. Tanaka, T. Kamei, J. Y. Fu,A. Cernea, Y. Li, M. Higashitani, G. Hemink, S. Sato, K. Oowada, S. C.Lee, N. Hayashida, J. Wan, J. Lutze, S. Tsao, M. Mofidi, K. Sakurai, N.Tokiwa, H. Waki, Y. Nozawa, K. Kanazawa, and S. Ohshima, “A 56 nmCMOS 99 mm2 8 Gb Multi-level NAND Flash Memory with 10 MB/sProgram Throughput,” Int. Solid-State Circuits Conference (ISSCC ),pp. 144–145, 2006.

1 Introduction

The widespread use of NAND flash memories in SSDs (Solid-state drives) hasunleashed new avenues of innovation for the enterprise and client computing.The system-wide architectural changes are required to make full use of theadvantages of SSDs in terms of performance, reliability and power as shownin Fig. 1. Especially, the emerging storage class memories (SCM) such asPCRAM, FeRAM, RRAM and MRAM are becoming a viable alternative tocommonly used volatile and nonvolatile memories. Being bit-alterable likeDRAM and nonvolatile like a flash memory together with CMOS-processcompatibility, these non-volatile random access memories have a potential torevolutionize various aspects of the computing platform architectures.

This paper introduces low power, highly-reliable and high performancememory system technologies.

Fig. 1. Conventional and future SCM & NAND flashmemory hybrid memory system [1, 2].


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2 NAND flash memory and Solid-State Drive (SSD)

Fig. 2 shows the NAND flash memory cell and the chip architecture. In theprogramming, electrons are injected to the floating gate by applying highvoltage to the control gate. As a result, threshold voltage (VTH) of thememory cell increases. In the erase, electrons are ejected from the floatinggate by applying high voltage to the P-well. As a result, VTH decreases.Read voltage (VRead) is applied to the control gate to read the data. A blockconsists of many pages. The page is the programming unit and the block isthe erasure unit of the NAND flash memory.

Fig. 3 shows the hardware architecture of the SSD [1]. SSD consistsof many NAND flash memories, a DRAM and a NAND controller. TheNAND controller manages the data transfer between the host and the NANDflash memory. For example, error correction and interleaving is performedin the NAND controller. Interleaving is the parallel read/write technique toenhance the SSD performance. Increasing the interleaving number resultsin large power consumption. The reliability of the NAND flash memory hasbeen degraded as the scaling. Both reliability and power consumption issuesshould be solved.

Fig. 2. NAND flash memory cell and the chip architec-ture.

Fig. 3. Hardware architecture of SSD.

3 Highly-reliable and low power signal processing

An intelligent Solid-State Drives, SSDs, which decrease memory errors by95% and reduce the power consumption by 43% is proposed [2].


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Fig. 4 shows the proposed Randomizing Coding and Asymmetric Cod-ing. All “10”-data is the worst case for the reliability due to the large pro-gram/erase stress and high electric field during retention. Considering thedata retention error is over 100-times more than the program disturb error,the proposed coding improves the data retention by increasing “1”- and “0”-data of the lower and upper pages, respectively. As a result, the “10”-datais reduced to 16%. The total retention error decreases by 95% (Fig. 5).

Fig. 6 shows the Stripe Pattern Elimination Algorithm (SPEA). Whenthe column-stripe pattern (1010. . . ) is programmed, all of the inter bit-linecapacitance is charged, which results in large power consumption. On theother hand, when all “1”-data is programmed, all of the inter bit-line capac-itance is eliminated and thus the power consumption is minimized. Fig. 7shows a waveform of the drawing current of NAND flash memories. WithSPEA, the program peak current of 4Xnm and 3Xnm NAND decreases by35% and 43%, respectively. SPEA is more effective in the scaled NAND be-cause as the memory cell size decreases, the bit-line capacitance as well as

Fig. 4. Proposed Asymmetric Coding. The program dataof NAND is modified to decrease the populationof “10” and “00”.

Fig. 5. Measured reliability improvement of AsymmetricCoding.


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Fig. 6. Proposed Stripe Pattern Elimination Algorithm(SPEA).

Fig. 7. Measured program peak current reduction withSPEA.

Fig. 8. Photograph, block diagram and key features ofthe proposed SSD.

the power increase.Fig. 8 shows the photograph of the proposed SSD. Besides the on-board

16 NAND chips, another NAND is implemented in the daughter board for


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the reliability/power test. Asymmetric Coding reduces memory cell errorsby 95% and realizes the highest reliability by working with advanced ECC(Error correcting code) such as LDPC (Low-density parity-check). SPEAdecreases the program current by 43%.

4 Dynamic codeword ECC scheme

Fig. 9 shows the proposed dynamic codeword transition ECC scheme [3]. Inthe conventional scheme, the ECC codeword is fixed at 512 Byte. In theproposed scheme, to keep the BER after ECC below 10−15 and secure thehigh reliability of SSD in the market, the error number or W/E cycles aremonitored. Then, the ECC codeword is adaptively changed from 512 Byteto 1 KByte, 2 KByte, and so on, when the BER after ECC exceeds 10−15.

Fig. 10 (a) shows the BER after ECC vs. the raw BER before ECC wherethe ECC codeword is in the range between 512 Byte and 32 KByte. 104-bitparity per 512 Byte codeword is assumed. Below 10−15 BER after ECC isrequired in the market.

In the proposed scheme, the ECC codeword adaptively increases. Theacceptable raw BER before ECC becomes larger and thus the product lifetimeincreases. The acceptable raw BER before ECC is shown in Fig. 10 (b).In the proposed 32 KByte codeword ECC, the acceptable raw BER beforeECC is 17-times higher than the conventional fixed 512 Byte codeword ECC.

Fig. 9. Proposed dynamic codeword transition ECCscheme.

Fig. 10. (a) BER after ECC before ECC. (b) Acceptableraw BER before ECC.


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Fig. 11. (a) ECC circuit power consumption per ECCchannel vs. ECC codeword. (b, c, d) SSD readspeed and ECC circuit area vs. ECC codewordfor three types of applications, mobile phone (b)(single channel), MP3 player, digital-still cameraand high-speed memory card (dual channel) (c),and the SSD application (8 channels).

Fig. 11 (a) shows the ECC circuit power consumption per channel. The ECCcircuit power consumption is well below 10% of that of the NAND Flashmemory and satisfies the ECC circuit power requirements. Fig. 11 (b–d)shows the sequential read speed and the ECC circuit area.

5 SCM and NAND flash hybrid memory system

An adaptive codeword ECC (Error Correcting Code) for NV-RAM (NonVolatile RAM) and NAND flash memory integrated SSD is proposed in [4] toimprove the memory cell reliability by 3.6-times. In the proposed SSD, NV-RAM such as RRAM, PRAM and MRAM is used as write buffers (Fig. 12).16 NAND channels operate at the same time while single NV-RAM chipoperates. At 10 Gbps, the proposed SSD decreases the power consumptionby 97%. In the proposed ECC, errors of both NV-RAM and NAND arecorrected without circuit area overhead by sharing ECC circuits. The ECCcodeword, the data unit where ECC is performed, is adaptively optimizedfor NV-RAM and NAND. The ECC codeword is 32 KByte for NV-RAM and2 KByte for NAND. The acceptable raw bit error rate before ECC increasesby 3.6-times without ECC circuit area/power consumption penalty.

Fig. 13 compares the SSD power consumption. The paper [4] proposesthe integrated ECC for NV-RAM and NAND which corrects errors of both


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Fig. 12. (a) Proposed NV-RAM & NAND-integrated SSD.16 NAND channels operate at the same time whilesingle NV-RAM chip operates. (b) Write opera-tion. First, the write data is stored in NV-RAM at10 Gbps. Then, data are transferred to NAND at2.6 Gbps. (c) Read operation. Data are directlyread from NAND to the controller at 10 Gbps.

Fig. 13. Power consumption trend of SSD. At 10 Gbps, theproposed SSD decreases the power consumptionby 97%.

NV-RAM and NAND. The proposed ECC is implemented in the NV-RAM/NAND controller (Fig. 12). The ECC encoding, that is, the parity generationoperates before data is written to NV-RAM. In the ECC decoding, errorsare corrected for data output from NAND. ECC is required for each memorychannel [3]. For 16 NAND channels, 16 ECC circuits are required.

The paper [4] also proposes the adaptive codeword ECC (Fig. 14). Theerror correction is performed twice for NV-RAM and NAND. The ECC code-word of NV-RAM is larger than that of NAND to achieve a higher reliability.As the ECC codeword is larger, the acceptable raw bit error rate before ECCis larger (Fig. 15). As a drawback, the circuit area and the power consump-tion of the ECC decoder increase. Thus, the ECC codeword is maximized toenhance the reliability under the constraint of the circuit area and the powerconsumption [3].

For the ECC of NAND, because 16 NAND channels operate to achievea 10 Gbps read, 16 ECC circuits are required. The codeword of NAND is2 KByte. On the other hand, in the ECC of NV-RAM, only one NV-RAMchip operates because the required speed is 2.6 Gbps which is restricted by


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Fig. 14. Proposed adaptive codeword ECC. The ECCcodeword for NV-RAM and NAND is 32 KByteand 2 KByte, respectively. The numbering of thewrite/read flows show the order of the flows.

Fig. 15. Bit error rate after ECC vs. acceptable raw biterror rate before ECC. In the proposed adaptivecodeword ECC, the acceptable raw bit error ratebefore ECC of NV-RAM increases by 2.6 times byincreasing the codeword from 2K to 32 KByte.

the 16 channel NAND write (Fig. 14). The codeword of NV-RAM is extendedto 32 KByte. As a result, the acceptable raw bit error rate before ECC ofNV-RAM increases by 2.6-times (Fig. 15).

An adaptive codeword ECC is proposed for the NV-RAM and NANDintegrated SSD. Errors of NV-RAM and NAND are most efficiently correctedand the reliability improves by 3.6-times without circuit area overhead. Byusing NV-RAM as write buffers, the 10 Gbps write is achieved with a 97%power reduction.

6 Program voltage booster system for 3D-SSD

In this section, the low power and high speed program voltage booster sys-c© IEICE 2012

DOI: 10.1587/elex.9.779Received February 16, 2012Accepted March 12, 2012Published April 25, 2012

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tem for 3D-SSD is introduced. Fig. 16 shows the concept and fabricated chipphotograph of the 3D-SSD with the program voltage booster system. NANDflash memories, NAND controller, DRAM and the boost converter with theboost converter controller are integrated with SiP. The boost converter con-sists of an inductor in an interposer, the high voltage MOS, and low voltageMOS. Decreasing power consumption is the key design issue of SSD. To re-duce the power consumption, the 3D-SSD with a low power boost converterhas been proposed in [5]. By using the boost converter as the high-voltagebooster instead of charge pumps, the energy consumption of NAND flashmemories is decreased by 68% [5].

Further power reduction and rising time enhancement techniques are pro-posed in [6, 7] for the program voltage booster. The load condition of theprogram voltage booster is summarized in Fig. 17. Figs. 17 (a), (b) show thesimplified timing diagram of the NAND flash memory during auto-programoperation. In the actual SSD write operation, the number of channels dy-namically changes depending on the data size. When the Ready/Busy-signal(R/B) of each channel is low, the NAND is in the auto-program operation.

Fig. 16. (a) Concept of the 3D-SSD with the program volt-age booster system. (b) Chip photograph.

Fig. 17. Load condition of the program voltage booster.c© IEICE 2012DOI: 10.1587/elex.9.779Received February 16, 2012Accepted March 12, 2012Published April 25, 2012

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This means that the load condition of the program voltage booster changesdynamically. Thus, the program voltage booster should be dynamically op-timized for each number of channels to enhance the performance as well asminimize the power consumption. However, the conventional NAND con-troller cannot define the number of channels in a feed forward way becausethe program time cannot be exactly predicted due to the bit-by-bit verifyoperation. The write time also fluctuates by more than 200%, depending onthe page location in the NAND string. Therefore, the NAND channel num-ber detector is proposed in [6] to precisely detect the change of the activeNAND channel number.

As shown in Figs. 17 (c), (d), during the programming of NAND flashmemories, VPGM, 20 V, and VPASS, 10 V, are biased to selected and unselectedword-lines. The key challenge is that the load condition is drastically differ-ent between VPGM and VPASS. VPGM is applied to a single word-line whileVPASS is biased to 31–63 word-lines. Thus, for VPASS, the voltage boosteroperates in the lower VOUT, 10 V, and larger COUT, 1 nF per NAND chip,condition. Contrarily, for VPGM, the voltage booster operates in the higherVOUT, 20 V, and smaller COUT, 100 pF per NAND chip, condition. Espe-cially, if 16 NAND chips operate simultaneously to increase the system-levelSSD performance, COUT of VPASS is as much as 16 nF and the rising timeincrease to an unacceptably long time, 15.4µs. To reduce the rising time,the two-stage boost converter for VPASS is proposed in [7].

Fig. 18 (a) shows the block diagram of the integrated boost convertersystem that generates VPGM and VPASS. The fabricated chip is best optimizedby using three technologies. The boost converter controller with NANDchannel number detector which drives both VPASS and VPGM boosters operate

Fig. 18. (a) Schematic diagram of the program voltagebooster. (b) Intelligent TON/TOFF control scheme.


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at 1.2–1.8 V is fabricated with the 0.18µm standard CMOS. The 1st stage ofVPASS booster is made with the low voltage MOS of the NAND flash memoryprocess. Finally, the 2nd stage of VPASS and VPGM boosters are fabricatedwith the high voltage MOS of the NAND flash memory process. The NANDchannel number detector dynamically detects the number of channels. Basedon the number of channels, the boost converter adaptively selects the optimalturn-on and turn-off period of the clock, TON/TOFF at each boosting clockcycle as shown in Fig. 18 (b). TON and TOFF are changed separately basedon the measured optimal TON and TOFF.

If the data size is small e.g. the number of channels is smaller than 15,TON/TOFF minimizing energy is selected (energy saving mode). As the pump-ing time is short, the booster operates to minimize the energy of the booster.On the other hand, if the data size is large, 16–24 channels operate simulta-neously to enhance the write speed. As a result, the load capacitance of theprogram voltage booster increases. To decrease the boosting time, TON/TOFF

minimizing rising time is selected (high speed mode).Fig. 19 shows the measured rising time and the energy consumption of

the booster which are optimized for each number of channels. In the writeoperation with 1–15 channels, the proposed boost converter operates in anenergy saving mode to decrease the energy of the booster by 32%. In thewrite operation with 16–24 channels, the boost converter operates in a highspeed mode to accelerate the boosting. In the conventional 3D-SSD [5], themaximum number of channels is 15 to satisfy the rising time requirement. Inthe proposed scheme, the maximum number of channels is enhanced by 60%.

The conventional boost converter [5] is composed of the high voltageMOS of the NAND flash memory process. The high resistance or low ID ofthe high voltage MOS restricts the power delivery efficiency and causes theunacceptable long rising time. Contrarily, although the low voltage MOShas the benefit of the low resistance and high ID, leading to a better powerdelivery, it cannot be used because 10 V exceeds its bread-down voltage. Theproposed two-stage boost converter is the best mix and match of the lowvoltage and high voltage MOS. In the 1st stage that generates 3.6–5 V from

Fig. 19. Measured (a) rising time and (b) energy consump-tion of the booster per NAND channel for VPGM.c© IEICE 2012


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Fig. 20. Measured (a) rising time and (b) energy consump-tion during boosting of the two-stage boost con-verter for VPASS.

VDD (1.8 V), the low voltage MOS of the NAND flash memory process is usedto enhance the power efficiency from 35% to 51%. In the 2nd stage, the highvoltage MOS of the NAND flash memory process is used to generate VPASS

(10 V) as well as satisfy the break-down voltage limitation.Fig. 20 shows the measured rising time and energy consumption during

boosting for VPASS. The 16 NAND chip parallel operation, the rising timeof the 2nd stage boost converter decreases by 76%. Considering the energyconsumption at the 1st stage, the proposed scheme realizes the 4-times fastrising without the total power increase. Compared with the conventionalcharge pump, the energy decreases by 27% (Fig. 20 (b)). The MOS circuitarea is only 3.6% of the conventional charge pump. Thanks to the fast risingof VPASS, the number of NAND chips operating in parallel increases from 4to 16. As a result, the SSD performance increases by 4 times.

7 NAND controller design with intelligent interleaving scheme

As the capacity of NAND flash memories drastically increases, SSD that usesNAND as a mass storage of PC is attracting much attention. To realize alow power high speed SSD, co-design of NAND flash memory and NANDcontroller circuits are essential [1].

As the NAND cell is scaled down, the bit-line capacitance drasticallyincreases (Fig. 21 (a)). The total bit-line capacitance in a chip exceeds200 nF and the current to precharge the huge bit-line capacitance increases(Fig. 21 (b)). For sub-30nm generation, number of NAND chips operated inparallel should be smaller and the SSD speed drastically degrades as shownin Fig. 21 (c). To overcome this problem, low power circuit technologies areproposed in [1].

As shown in the current waveform of the NAND chip (Fig. 22), a currentpeak appears during the bit-line precharge and the charge pump ramp-up [8].In the interleaving, if the current peak of two or more NAND chips occursat the same time, huge current flows in SSD and the power supply drops bymore than 0.3 V.


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Fig. 21. (a) Bit-line capacitance trend of a NAND flashmemory. (b) Operation current trend of a NANDflash memory. (c) System-level performance trendof SSD.

Fig. 22. Current wave form of the intelligent interleaving.

To avoid this power supply noise and realize a both reliable and high-speed program, an intelligent interleaving is proposed in [1]. The interleavingoperation in the SSD operates the multiple NAND flash memory chips inparallel to enhance the SSD performance. In the proposed scheme, the PD(Power Detect)-signal is added. PD is connected with wired-or configurationas shown in Fig. 23 (a). If one of the NAND chips starts a bit-line prechargeor a charge pump ramp-up that causes a current peak, the NAND chip pullsdown the PD-signal. When PD is low, the NAND controller does not issue awrite command to avoid the noise. To monitor the status of each NAND chip,the R/B (Ready/Busy) signal is connected between the NAND controller andeach NAND chip. R/B is low if the NAND chip operates a read, programor erase. When both PD and R/B is high, Program Enable-signal in thecontroller shown in Fig. 23 (b) becomes low.

Since there is no current peak and the NAND chip is ready, the NANDcontroller issues a write command to the NAND chip and the program starts.By using the intelligent interleaving, multiple NAND chips are programmedat the same time without causing a power supply noise (Fig. 22). Therefore,a highly reliable and high speed operation of SSD is achieved.c© IEICE 2012


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Fig. 23. (a) Block diagram of the NAND flash memory andthe NAND controller. (b) Intelligent interleavingcontrol circuit in the NAND controller.

8 Conclusion

SCM and NAND flash memory hybrid SSD system and related technolo-gies are reviewed. SCM and SSD enabled innovations in various nano-scaleVLSI memory systems for personal computers, multimedia applications andenterprise servers. State-of-the-art memory system architectures and mem-ory circuits such as signal processing, hybrid memory architecture and 3D-integrated circuits are required to realize the low power and high performancecomputing.


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Ken Takeuchi

is currently an Associate Professor at the Department of Electrical Engi-

neering and Information Systems, Graduate School of Engineering of the

University of Tokyo. He is now working on the VLSI circuit design and

device especially on the emerging non-volatile memories, 3D-integrated

SSDs, low-power 3D-LSI circuits and ultra low-voltage SRAMs for

Green-IT. He received the B.S. and M.S. degrees in Applied Physics and

the Ph.D. degree in Electric Engineering from the University of Tokyo in

1991, 1993 and 2006, respectively. In 2003, he also received the M.B.A.

degree from Stanford University. Since he joined Toshiba in 1993, he had

been leading Toshiba’s NAND flash memory circuit design for fourteen

years. He designed six world’s highest density NAND flash memory prod-

ucts such as 0.7 um 16 Mbit, 0.4 um 64 Mbit, 0.25 um 256 Mbit, 0.16 um

1 Gbit, 0.13 um 2 Gbit and 56 nm 8 Gbit NAND flash memories. He holds

204 patents worldwide including 107 U.S. patents. Especially, with his in-

vention, “multipage cell architecture,” presented at Symposium on VLSI

Circuits in 1997, he successfully commercialized world’s first multi-level

cell NAND flash memory in 2001. He has authored numerous technical

papers, one of which won the Takuo Sugano Award for Outstanding Pa-

per at ISSCC 2007. He has served on the program committee member of

International Solid-State Circuits Conference (ISSCC), Asian Solid-State

Circuits Conference (A-SSCC), International Memory Workshop (IMW)

and Non-Volatile Memory Technology Symposium (NVMTS). He served

as a tutorial speaker at ISSCC 2008, a SSD forum organizer at ISSCC

2009, a 3D-LSI forum organizer at ISSCC 2010, Ultra-low voltage LSI fo-

rum organizer at ISSCC 2011 and Robust VLSI system forum organizer

at ISSCC 2012.

Teruyoshi Hatanaka

received the B.S. and M.S. degree in electronic engineering from Tokyo

Institute of Technology, Japan in 2008 and the University of Tokyo,

Japan in 2010, respectively. He is currently working toward a Ph.D.

degree. His research interests include emerging non-volatile memories

and dc-dc converter circuit design for low-power 3D-integrated SSD.

Shuhei Tanakamaru

received the B.E. and M.E. degrees in engineering in 2009 and 2011 from

the University of Tokyo, Tokyo, Japan, where he is currently working

toward the Ph.D. degree. He has been engaged in a research on low

power DRAM, SRAM and highly reliable solid-state drive (SSD). He has

received the IEEE EDS Japan Chapter Student Award and IEEE SSCS

Japan Chapter Academic Research Award in 2009 and 2011, respectively.


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Highly Reliable, High Speed and Low Power NAND Flash Memory Based Solid State Drives (SSDs) 2012 IEICE Electronics Express