Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Embedded Fault Diagnosis

Lehrstuhl Technische Informatik - Computer Engineering

Brandenburg University of Technology Cottbus

SignalProcessingPoznan 2007

Embedded Fault Diagnosis for Digital Logic Exploiting Regularity

R. Kothe, H. T. Vierhaus


Computer Science Department

Computer Engineering Group




Outline

1. Introduction: Fault Diagnosis - when and what for?

2. Scan Test and Pattern Compaction

3. How Fault Diagnosis is Done

4. Embedded Fault Diagnosis Based on Regularity

5. Summary and Conclusions




1. Introduction

Fault diagnosis becomes a must for production test of ICs and for self-test „in the field“.




Test-Technology-Traditionally

Prototype test

Production test

In-field test

Time

Cost

Quantity

Destructive often never never

Diagnosis yes hardly little

hours to days seconds to minutes seconds to minutes

1000-10000$ cents to a few $ (none)

5 to 100 thousands to millions (individual test)




Test Technology for Nano-Technologies

Prototype test

Production test

In-field test

Time

cost

quantity

Destructive often never never

Diagnosis yes yes, must be yes, must be

hours to days seconds to minutes seconds to minutes

1000-10000$ cents to a few $ (none)

5 to 100 thousands to millions (individual test)

for yieldoptimization

for self-repairfor repair




New Problems with Nano-Technologies

Lightsource

mask (reticle)

wafer

resist

exposed resist

Wave length: 193 nm

Feature size: down to 45 nm




Layout Correction

Modified layoutfor compensationof mapping faults

Compensation is critical and non-ideal

Faults are not random but correlated !

Requires fast fault diagnosis




Built-in Self Repair (BISR)

f

Logic blocks

r

backup / replacement blocks

Logic test mustidentify the faultyblock before repair / replacement !

Problem:There is no powerfultest machine available !




Why Diagnostic Test is NeededTraditional IC production test does not care for fault diagnosis.

Fabrication in nanometer technologies uses exposure wavelengths that are up to5 times longer than the minimum feature size.

All layout features need an „advanced“ correction to compensatefor mapping faults. This correction is non-ideal.

Diagnostic test is required to find faulty layout corrections for fast „ramp up“ in production yield.

Built- in Self Repair (BISR) for long-time dependable systemsrequires „built-in“ diagnostic test as a pre-condition!




Basic Questions

Can diagnosis be done on top-of production testtechnology with massive test data compression ?

How good can the diagnostic resolution be ?

Is a fine – grain diagnosis as a pre-condition forbuilt- in self repair possible „in the field“ at reasonable cost / overhead ?

Note: All answers are „yes“ for regular structures such as memory blocks !

Can production test technology be compatible within-field testing ?




2. Scan Test and Pattern Compaction

The workhorse of test technology has to do a varietyof jobs never thought of by the it inventors.




Scan-Based IC Test

Comb.Logic

(pseudo-)inputs

(pseudo-)outputs

Inputvector

Outputvector

ff

ff

ff

ff

ff

ffff

ff

ff

ff

ff

scan-in scan-out




Essentials of Scan Testing

Multiple scan paths (100 to 1000).

No whatsoever usage of functional features.

Scan path allocation / partitioning without making any useof logic regularity.

Test sets are strictly minimized, no specific patterns forfault diagnosis.Fault diagnosis has to come combined with or „on top“ of compaction mechanisms.

Identical problems for compaction / diagnosis for external testor built-in self test (logic BIST).




Multi-Scan Path IC Test

Pattern Generator(LFSR)

control

Multipleparallelscan paths

MISRCompactedtest response

External TesterTest

Processor

encoded testpatterns

(optionalfor „embedded“scan test)

PatternMemory




Data Compression / Compaction

Pattern Generator(LFSR)

control


Time comp. (MISR)

External TesterTest

Processor

encoded testpatterns

ATPGCOMP

Off-line

Compactionrate: 50-500

Space Compactor (XOR-tree) Compaction rate:100-1000

PatternMemory

On-line




Advanced Scan Test RequirementsFast scan-test for production test without fault diagnosis.

Fast scan test for production with additional (off-line)fault diagnosis.

Scan output analysis with detailed on-chip diagnosisfor „silicon debug“.

Scan output analysis with high-resolution diagnosis as apre-process for logic self repair.

Diagnosis may be done:

In parallel with fault detection

Selectively after fault detection

Encoding / parity bits?

MISR-based compactionand analysis?




3. How Fault Diagnosis is Done

Fault Diagnosis has to be combined with test outputcompaction / compression.Compaction can be done in space and in time, butloss of diagnostic information is a problem.




Space-Compaction and Fault Masking

Comb.Logic

(pseudo-)inputs

(pseudo-)outputs

Inputvector

Outputvector

+

+

+

+

+out

Avoid multiple outputpaths by ATPG!

f

ffault

Fault is „absorbed“

Remedy:




Fault Detection by Direct Comparison

Comb.logic

(pseudo-)inputs

(pseudo-)outputs

Inputvector Scan

path

clock

Ref-Pattern

„Good“ outputs ordered, number of appearances noted

COMPARE

Test Processor

Ref-out

ordered by„good“ response

Compareupondetected fault

fault




Error Detection Using Compressed Outputs

Logic

SP1

SPn

MISRTestprocessorRef.MISR

CompareReference

Pattern

Scan paths

Does not yetidentify the faulty scan path !

SPs1ton




MISR-Based Compaction in Time

A multi-input signature register (MISR) can do a compaction„in time“.

FF + FF + FF + FF +

In case of multiple fault events, fault masking is also possibledue to „aliasing errors“.




Diagnosis by Variable MISR Allocation

Sub-Circuit n Sub-Circuit k

Scan chains

serving overlapregion

MISR n

MISR n‘MISR k‘

MISR k

faultfaultfault




Coding-Based DiagnosisScan Input Generator(De-Compactor)

& & & & & & &

MISR

d0 d1 d3 d4 d5 d6d2storage

scan clock

Backup MISRRead-outfor external analysis

Code-word

Applicationof multiplecode-wordsto the samescan output




Top Compaction & Diagnosis Technologists

• Janusz Rajski (Mentor Graphics, formerly PUT) and Jerzy Tyszer ( PUT)

• Michael Gössel, Jan Rzeha (Univ. of Potsdam)

• Ralf Pöhl, Andreas Leininger (Infineon Technologies, Munich)




Coding-Based Diagnosis

Scan Input Generator(De-Compactor)

& & & & & & &

MISRRef.

MISR

compare

d0 d1 d3 d4 d5 d6d2d-valuestorage

scan clock

MISR clock: k * scan-clock

aStop / activate MISR feedback

Patented by Infineon Technologies AG and U. Potsdam, 2004




How the Scheme WorksIn the „normal“ test mode, all d-inputs are set to „1“. The MISR will indicate that a fault has occurred after compaction of oneor more full test responses.

In the diagnosis mode, the test for the faulty vector is re-applied again.Then the output is encoded in k steps with k being the number neededto implement a fault detecting code for the n scan path outputs.

For collecting the diagnosis output, the MISR is operated as a shift registerwithout feedback. The d-inputs are set according to the rules of the code.

After k cycles of a local MISR clock, the diagnosis information isstored in the MISR / shift register.

Using a Hamming code, an XOR-comparison between the actual outputand a reference output directly reveals the faulty scan chain.




Output Encoding

d0 d1 d2 d3 d4 d5 d6 d7

0 1 1 0 1 0 1 11 0 1 1 0 1 0 1

1 1 0 1 1 0 1 1

1 0 1 0 1 1 0 1

1 1 0 1 0 1 0 0

Coding

Test-Output

MISR (error code)

&

Error det. codes,width dependingon the numberof scan chains andthe diagnosticresolution !

Analysis

Error coding is the same

for every test pattern !

The result can also accommodate multiple faults !




Features and Limitations

Multiple faults can be diagnosed, depending on the codeapplied. In case of Hamming code, faults that are relatedto a diagonal in the d-matrix cannot be resolved.

The set of d-bits used for encoding is independent of thetest output. It can be stored locally and is applied repeatedly.

The reference pattern for detection of the „faulty“ outputbit needs to be supplied for every bit output vector.

In this version, the scheme cannot yet handle „undetermined“scan outputs.




The „X Output Problem“

Test responses in scan test may include „undetermined“output values.

Most compaction schemes cannot handle „X“-bits, butneed to replace them by deterministic settings.

The information „which output bit on which scan chain“ needsto be set, can be as large as the (compressed) input pattern fileitself !




Encoding Test OutputsScan Input Generator(De-Compactor)

scan clock

Encoder / CompactorCode-bits

X-blankinginformation

Signature





4. „Embedded“ Fault Diagnosis

Built-in self repair needs to be done „in the field“ withlimited resources for test and diagnosis.




Built-in Fault Diagnosis?

Scan Input Generator(De-Compactor)

& & & & & & &

MISR

compare

d0 d1 d3 d4 d5 d6d2d-valuestorage

scan clock

MISR clock: k * scan-clock

aStop / activate MISR feedback

TestProcessor

Pattern-ROM

RAM

16

Ref. MISRSer. / parallel load




No Solution for „Embedded“ Diagnosis?

For efficient diagnosis by as-few- as- possible parity bits,long registers / MISRs are required (100-1000 bits!)

A reference MISR is needed in order to detect the clock cycleat which a specific scan path had a fault.

The diagnosis reference patterns must either be stored andsupplied (e.g. one for every test pattern).

A workable solution for a few specific tests,but not in the general case!




Regularity in Logic Designs

Module n Instance 1

MISR

Scan-in Scan path

Module nInstance 2

Module nInstance 3

Module n

Test Generator

Scan path

Instance 4

Scan paths and MISR sections are associated with „equal“structural entities.




Regularity in Test Generation

Equal sections can be fed in parallel with the same test patterns.

LFSR control

M11

M12

M21

M22

M31

M32

M33

Simplified ATPG, smaller and faster patterninput compaction circuitry!

scan-path




Fault Diagnosis by „Virtual Majority Vote“

Scan-inScan path

Test Generator

+ + ++fault

& & &&

Fault wordf1 f2 f3 f4

Module nInstance 1

Module nInstance 2

Module nInstance 3

Module nInstance 4




Registration of Fault Events

Scan-in Scan path

Test Generator

+ + ++fault

& & &&

MISR (Fault word)

f1 f2 f3 f4

counter

clock

OR

e

e

Storein faultmemory

Module nInstance 1

Module nInstance 2

Module nInstance 3

Module nInstance 4

enable




Single / Double Fault EventsUnit 1 2 3 4 5 6 7 8

++ + + + + + +1

single fault

Unit 1 2 3 4 5 6 7 8

++ + + + + + +1

double faultUnit 1 2 3 4 5 6 7 8

++ + + + + + +1

double fault

Unit 1 2 3 4 5 6 7 8

++ + + + + + +1

double fault




Triple Fault EventsUnit 1 2 3 4 5 6 7 8

++ + + + + + +1

triple fault

Unit 1 2 3 4 5 6 7 8

++ + + + + + +1

triple fault

Unit 1 2 3 4 5 6 7 8

++ + + + + + +1

triple faultdouble single

Unit 1 2 3 4 5 6 7 8

++ + + + + + +1

triple fault




Usage for Built-in Self Repair?switch switch

FU

FUB

FUB

FU

FU

FU

FU

FU

inputs outputs

functional

unit

backupunit

Designs that facilitatebuilt-in self repair willbe composed from a limitednumber of different functionalunits (NAND, NOR, FF)have „internal“ redundancy.

Logic will becomeregular!




Signal Processing Architecture

Z -1

Z -1

Z -1

Z -1

Z -1

Z -1

Z -1

Z -1

x

x

x

x

x

x

x

xx

x

x

+

++

+

+

+

+

+

+

+

+

+

c0

c1

c2

c3

cM-1

cM

d1

d2

d3

dN-1

dN

x (n)

InputOutputy (n)

Verzöge-rungen

y (n-1)

y (n-2)

y (n-3)

y (n-N-1)

y(n-N)

x(n-1)

x(n-2)

x(n-3)

x(n-M-1)

x(n-M)

Addierer

Multipliz.Z -1

Z -1

Z -1

Z -1

Z -1

Z -1

Z -1

Z -1

x

x

x

x

x

x

x

xx

x

x

+

++

+

+

+

+

+

+

+

+

+

c0

c1

c2

c3

cM-1

cM

d1

d2

d3

dN-1

dN

x (n)

InputOutputy (n)

Verzöge-rungen

y (n-1)

y (n-2)

y (n-3)

y (n-N-1)

y(n-N)

x(n-1)

x(n-2)

x(n-3)

x(n-M-1)

x(n-M)

Addierer

Multipliz.

... are typically regular by nature!




5. Summary and Conclusions

Fault diagnosis becomes an indispensable part of test.

Fault diagnosis for highly irregular logic structuresbecomes expensive.

DSP architectures and re-configurable logic architecturesare inherently regular.

Exploiting regularity for test generation and for faultdiagnosis can reduce the need for reference outputssignificantly, facilitating embedded fault diagnosis.

Strongly correlated faults need reference data!




What Else??

Thank You for Your Attention!!

There is still a lot of work to do before we will have highly dependent nano-electronic circuits and systems.

Documents

Lehrstuhl Technische Informatik - Computer Engineering Brandenburg University of Technology Cottbus Signal Processing Poznan 2007 Embedded Fault Diagnosis