Lee Scheffler, Cognitivitycognitivity.technology/wp-content/uploads/2017/09/Neuros-pitch.pdfognitivity Positioning 4 raction biological fidelity synapse-level simulations "classical"

ognitivity

www.cognitivity.technology

NeurOS and NeuroBlocks A Neural Operating System and Cognitive Building Blocks

© Copyright 2017, Lee Scheffler patent pending 1

portable scalable

embeddable extensible

Rapidly build/run cognitive systems

Lee Scheffler, Cognitivity

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NeurOS and NeuroBlocks in a Nutshell

Build cognitive systems… … by linking reusable modules … … into directed neural graphs/circuits

Broad applicability

Rapid iterative visual flow development

Open, extensible, embeddable, portable, scalable, …

© Copyright 2017, Lee Scheffler patent pending

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Me • Software architect/CTO career

– Multics, security (MIT, Honeywell) – networking, office automation, workstations

(Prime) – data access (Constellation - startup) – data integration – DataStage

(VMark/Ardent/Informix/Ascential/IBM)

– cognitive systems (Cognitivity)

• Maxims: Be Useful, Make Stuff Work

© Copyright 2017, Lee Scheffler

patent pending 3

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Positioning

4

abst

ract

ion

biological fidelity

synapse-level simulations

"classical" AI (symbolic)

probabilistic, connectionist

models spiking

simulations

NeurOS NeuroBlocks

(functional)

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Architecture Layers • Cognitive system architecture


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• Neural processing architecture – biologically inspired non-von Neuman

non-procedural dataflow system

"application programs"

"programming language"

• Implementation architecture – conventional computers, networks

"virtual machine"

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Cognitive System Challenge


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external world user, environment

learning

abstraction

memory

imagination

prediction

decision sen

sati

on

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Inspirations/Influences • Modular component systems

– Erector set, MIDI, Legos, ... • Circuit design • Shell pipelines • Spreadsheets • Dataflow systems • Braitenberg: "Vehicles" • Signal processing • Analog computing • Biological brains

– Jeff Hawkins: "On Intelligence"


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Example: What's That Tune?

NeuroBlocks parts bin

NeurOS Designer IDE

Drag&drop neural graph design canvas

Output module displays 8 © Copyright 2017, Lee Scheffler patent pending

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Basics

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out

links

neural graph:

out

module module in events

in


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Basics

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out

links

neural graph:

out

in events

in


module Group/layer of neurons or dendritic branches with similar function; state

link Mulitiplexed event signal path: axons of multiple neurons

neural graph Directed flow, loops, nestable sub-graphs

event New spiking rate of a neuron

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Basics

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out

links

neural graph:

out

in events

in






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Basics

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out

links

neural graph:

out

in events

in






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Basics

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out

links

neural graph:

out

in events

in






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Basics

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out

links

neural graph:

out

in events

in


max rate 50% rate 33% rate

(0, id,1.0) (25, id,0) (50,id, 0.5) (75, id,0.33) (120, id,0) event code:

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Module Types

inputs (senses)

processing

memory

outputs (actions,

effectors)

temporal pattern in

keyboard grid in data gen MIDI in stream in

working memory

set patterns

sequence patterns

temporal patterns

pattern reify

filter transformer group ops wrapper subgraph

print plot cloud grid out stream out MIDI out log

16 © Copyright 2017, Lee Scheffler

patent pending

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Memory Pattern Module Types

Sets Concurrent feature collections in any order

Semantic range: any/OR, a few, some, many, most, all/AND

Sequences Time-independent sequences of features

Parameters for non-exact sequence matching

Temporal Patterns

Time-relative sequences of multiple features

Parameters for non-exact matching, speed range

Reify Inverse: generate pattern features

e.g., prediction, imagination, expectations, feedback


patent pending

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Pattern Examples

18 © Copyright 2016 Lee Scheffler

"dog"

"cat"

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Layers of Patterns

© Copyright 2016 Lee Scheffler 19

letter

LED

seg

men

t

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www.cognitivity.technology © Copyright 2016 Lee Scheffler 20

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Pattern Learning • Current inputs match an existing pattern

well-enough? – novelty threshold parameter – adjust feature weights of best matching

pattern(s); learning rate parameter, annealing • Otherwise:

– create a new pattern from the current inputs Enables complex pattern heterarchies

– specific exemplars, stereotypes, ... – layers of recombination of abstractions


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Typical Cognitive System Structure


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external world user, environment

sensory preprocessing feature/invariant extraction

dimensionality reduction multiple channels

outputs, actions multiple channels

mer

gin

g

sensory control

predictions expectations imagination

pattern learning and recognition

abstraction

be

hav

ior

pat

tern

s

reification

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NeurOS Strengths

• One/few-shot learning – no huge training sets

• Continuous on-line learning

• Unsupervised, supervised ("teaching"), reinforcement learning

• Few configuration "hyper-parameters"


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NeurOS Implementation Architecture

36 © Copyright 2017, Lee Scheffler patent pending

neural graphs

development tools

run-times

single process

multi- process

distributed

GPUs, custom chips

stand- alone m

odule &

ass

embly

libra

ries

exte

rnal libra

ries,

sy

stems

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Module


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Module Life-Cycle • create instance

• start(vtime) – initialize external resources, internal state – schedule self-events if needed (e.g., input polling modules)

• run(vtime) – access input signals

• new events (changed signal values) • current signal values

– recompute internal dynamic parameters (e.g., learning rate) – compute internal state changes – update shared global data – compute and send output signal events

• non-zero virtual time delay

– schedule self-events (input modules, decays, randomness)

• finish(vtime): finalize/close external resources


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sub-graph module

Recursion • Sub-circuits recaptured as reusable modules


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graph parameters pattern spaces

pattern spaces

pattern space map

module parameters

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Virtual Time

• Always moves forward – non-zero module processing vtime

• variable processing vtimes model biology

– enables (feedback) loops – vital !

• Signals synchronized only where needed – enables parallelism

• Synchronized with real time at edges – typical compromises: miss inputs, stumble


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Master Work Queue/Loop (single process, multi-thread implementation)

• Event send: – post event message (vtime, signal id, new value) on

each output link

– add run(module, vtime) to vtime-sorted work queue

• Next iteration: – get run(module, vtime)s for lowest vtime and run

• can be concurrent


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Performance, Scalability

• Signal value changes only – don't run modules where there are no signal changes – good-enough approximations

• Patterns indexed by events – don't evaluate patterns that don't care about current

signal changes

• Multi-threading • Multi-process, distributed execution • Partitioning, load balancing • Custom hardware


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Integrations, Extensions, Embeddings

• Configurable modules – formatted file I/O, database access,

pipes/sockets, web services, etc.

• External library functions

• Wrap external library/program – stdin/stdout/stderr, APIs

– no write-shared state among module instances; no synchronization guarantees

• Templated and custom modules


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Active Projects

• Industrial machine vibration monitoring, alerting, predictive maintenance, diagnosis

• Adaptive doctor's user interfaces to EHR systems

• Virtual infant robot learning

• Redistributable dev kit


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ognitivity


NeurOS and NeuroBlocks in a Nutshell

Build cognitive systems… … by linking reusable modules … … into directed neural graphs/circuits

Broad applicability

Rapid iterative visual flow development

Open, extensible, embeddable, portable, scalable, …


46

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Contact

http://www.cognitivity.technology

[email protected]


patent pending

(Sign up to be notified when NeurOS development kit is available)

http://www.cognitivity.technology/

http://www.cognitivity.technology/

Documents

Lee Scheffler, Cognitivitycognitivity.technology/wp-content/uploads/2017/09/Neuros-pitch.pdfognitivity Positioning 4 raction biological fidelity synapse-level simulations "classical"