Lecturer Michael S. McCorquodale Authors Michael S. McCorquodale, Mei Kim Ding, and Richard B. Brown Top-Down and Bottom-Up Approaches to Stable Clock

LecturerMichael S. McCorquodale

AuthorsMichael S. McCorquodale, Mei Kim Ding, and Richard B. Brown

Top-Down and Bottom-Up Approaches to Stable Clock Synthesis

Solid State Electronics LaboratoryCenter for Wireless Integrated Microsystems (WIMS) Department of Electrical Engineering and Computer ScienceUniversity of MichiganAnn Arbor, MI USA 48109-2122

International Conference on Electronic Circuits and Systems, Sharjah, U.A.E., 2003

2NSF ERC for Wireless Integrated MicroSystems (WIMS)NSF ERC for Wireless Integrated MicroSystems (WIMS)

Lecture Overview

• Overview of Clock Synthesis

• Effects of Frequency Translation on Frequency Stability

• Top-Down and Bottom-Up Synthesis

• Application

• Design and Simulation

• Results

• Conclusions and Future Work

Overview Freq. Trans. Synthesis Application Design & Sim. Results Conclusions


Clock Synthesis

• The clock is arguably the most significant signal in any synchronous system

• Harmonic quartz XTAL reference + PLL is the ubiquitous approach

– High accuracy and stability

– Broad range of output frequencies

• Drawbacks

– Discrete components required (not monolithic)

– PLL power and area

– Systemic short-term stability degradation (to be presented)

• Challenges in developing an alternative (possibly monolithic) approach

– Accuracy and stability

– Monolithic reference (typically low-Q)



Short-Term Frequency Stability Metrics

o

mov

fo

o

P

ffS

P

N

m

)(

Phase Noise: Power relative to fundamental at some offset fm

ffo

P

fm

JTttkJ kkk )var()var()( 1

Period Jitter: of the position of the next edge relative to the ideal

Ideal Period Period Jitter

tk tk+1

)10//( 6TJJ ppm



Frequency Multiplication and Division

dt

d

Phase and frequency are related by a linear operator:

))(cos()( ttVtv noon ))(cos()(, tNtNVtv noomultn

Frequency mult./div. results in phase noise mult./div.:

Using narrowband FM approximation:

)log( 2

./.,

NP

N

P

N

mm fo

o

divmultfo

o

Linear freq. translation results in quadratic change in noise power



Converting Phase Noise to Period Jitter

3

2

2o

m

fo

o

f

f

P

NJ

m

• Typically fo2c called corner or line width: select fm above the corner and below fo

• Lorentzian implies absence of flicker noise (slope must be 20dB/dec)

2242

2

mo

o

fo

o

fcf

cf

P

N

m

The SSB phase noise PSD can be represented by a Lorentzian function:

mfo

o

P

N

fm

20dB/decomo ffcf 2

2

2

m

o

fo

o

f

cf

P

N

m

Which can be approximated for:

Using the above:



Frequency Translation and Jitter

Using phase noise conversion expression, determine jitter:

NJNf

f

P

NNJ

o

m

fo

omult

m

/)(

23

22

JN

Nf

f

P

N

NJ

o

m

fo

odiv

m

3

2

2 )/(

12

Considering fractional, or ppm, jitter:

610/T

JJ ppm

ppmmultppm JNNT

NJJ

6, 10/)/(

/NJ

NT

JNJ ppmdivppm /

10/ 6,

Frequency translation also enhances and degrades jitter



Relationship with Quality-Factor

• Leeson model: Q-factor quadratically related to phase noise

• Q-factor is one of the most significant metrics indicating stability

• Typical quartz XTAL Q on the order of 10,000

• Frequency translation also quadratically related to phase noise

• Consider effective Q-factor modification due to freq. translation

• If NdivNmult > Qmult/Qdiv then divided signal more stable

• Assumption: oscillator power and noise factor are the same

• Nmult for XTAL+ PLL up to 4096: high-Q, but large degradation

2

28

1

m

o

fm

o

f

f

QC

FkT

C

N Leeson Phase Noise Model



Frequency Translation Summary

NJ /

mfo

o

P

N

Variable/MetricReferenceOscillator

FrequencyMultiplication

FrequencyDivision

Output Frequency

(Hz)fref Nfref fref /N

SSB Phase Noise PSD

(dBc/Hz)

Period Jitter (s) J

Relative

Period Jitter (ppm)

Jppm

)log(20 NP

N

mfo

o

)log(20 N

P

N

mfo

o

JN

NJ ppm /ppmJN



A Bottom-Up Approach

÷N

NfrefLPFvctrl

fref

CPPFD

Quartz XTAL reference oscillator + PLL

The signal that actually drives the processor is a frequency multiplied (and degraded) image of the reference



A Top-Down Approach

÷Nfref fref

N

A harmonic LC (and monolithic) RF reference

The signal that actually drives the processor is a frequency divided (and enhanced) image of the reference

LC reference also provides good accuracy as compared to ring or relaxation approach



Application Test Bench

• Intel SA-1110

–3.6864MHz XTAL reference + PLL

–~200MHz max output frequency

• Bottom-up Approach

–3.125MHz XTAL, Q = 10,000

–Output = 200MHz, N = 64

• Top-down Approach

–3.2GHz reference, Q = 10

–Output = 200MHz, N = 16

All transistor design with TSMC 0.18 MM/RF



Pierce Bottom-Up XTAL Reference OSC

301

501

389m 4.79f 900

30p30p

7p

500k

3.125MHz XTAL reference

Requires off-chip XTAL + 2 capacitors + 1 resistor

XTAL lumped parameter model



Ring Bottom-Up VCO

40.18

20.18

40.18

20.18

40.18

20.18

bias

from last stage from last stage

20-stage 200MHz current-starved ring VCO



A Bottom-Up System

LPFPFD

÷N

fref

Nfref

vctrlCP

Remainder of PLL modeled with Verilog-A



LC Top-Down Reference OSC

400.18

1000.18

400.18

1000.18

360.18

2nH

bias

950fF

3.2GHz monolithic RF LC reference oscillator



Top-Down System Implementation

Entire system designed at the device level

Each feedback flip-flop divides frequency by two


DFFDFFDFF

Q

Q

D

AMP+

-

3.2GHz Q

Q

D Q

Q

D

DFF

QD

Q 200MHz


Design and Simulation

• Bottom-up Approach

–Phase noise for reference OSC and VCO simulated at device level

–Device-level results modeled with Verilog-A

–Entire PLL modeled with phase domain approach using Verilog-A

• Top-down Approach

–Entire system simulated at the device level



Bottom-Up Phase Noise Performance

101

102

103

104

105

106

107

-150

-125

-100

-75

-50

-25

0

Offset Frequency (Hz)

Pha

se N

oise

Spe

ctra

l Den

sity

(dB

c/H

z)Bottom-up Reference OscillatorBottom-up VCOBottom-up Synthesizer Output

~20log(64)



Bounding PLL Phase Noise

101

102

103

104

105

106

107

-150

-125

-100

-75

-50

-25

0


Pha

se N

oise

Spe

ctra

l Den

sity

(dB

c/H

z)Bottom-up Reference OscillatorBottom-up VCOBottom-up Synthesizer Output

~20log(64)

PLL Loop BW

20dB/dec

20dB/dec

Upper Bound

Lower Bound



Top-Down Phase Noise Performance

101

102

103

104

105

106

107

-150

-125

-100

-75

-50

-25

0


Pha

se N

oise

Spe

ctra

l Den

sity

(dB

c/H

z)Top-down Reference OscillatorTop-down Synthesizer Output

~20log(16)



Performance ComparisonPerformance Metric Bottom-Up Synthesis Top-Down Synthesis

Application Frequency, fo (MHz) 200 200

Reference Oscillator Frequency, fref (MHz) 3.125 3,200

Multiplication/Division Factor, N 64 16

Reference Oscillator Quality Factor, Q 10,000 10

Reference Oscillator Phase Noise Density, (No/Po)fm (dBc/Hz) -140.8dBc/Hz @ 10kHz -83dBc/Hz @ 10kHz

Calculated Period Jitter at Reference from (No/Po)fm @ 10kHz offset, J (fs) 233 5.5

Calculated Relative Period Jitter at Reference, J ppm (ppm) 0.73 18

Synthesizer Output Phase Noise Density, (No/Po)fm (dBc/Hz) -104.6dBc/Hz @ 10kHz -106.8 @ 10kHz

Calculated Period Jitter at Output from (No/Po)fm @ 10kHz offset, J (fs) 29 23

Calculated Relative Period Jitter at Output J ppm (ppm) 5.9 4.6

Phase Noise Density Accumulation/Reduction Factor, (dB) 36.2 -23.8

Period Jitter Accumulation/Reduction Factor 0.12 4.2

Relative Period Jitter Accumulation/Reduction Factor 8.0 0.23



Conclusions and Future Work

• Frequency multiplication degrades short term stability and effectively

reduces reference oscillator Q

• Frequency division enhances short-term stability and effectively

increases reference oscillator Q

• Bottom-up approach requires reference XTAL OSC + PLL while top-

down approach requires only reference OSC + divider

• For a common application, top-down approach provides comparable

frequency stability to bottom-up approach, while being substantially

simpler to implement

• Top-down approach facilitates monolithic integration

• Such a clock synthesis system has been developed and will be

reported in the near future

• More sophisticated top-down architectures will be explored



Conclusions and Future Work

Questions?


Documents

Lecturer Michael S. McCorquodale Authors Michael S. McCorquodale, Mei Kim Ding, and Richard B. Brown Top-Down and Bottom-Up Approaches to Stable Clock