Lecture1 1 Fabrication+Processing+Steps

8/9/2019 Lecture1 1 Fabrication+Processing+Steps

1/28

12/12/2008 1VLSI Design

CMOS ProcessingCMOS Processing

VLSI DesignVLSI Design

UNIT I: Introduction to IC Technology


2/28

VLSI Design 2

N Transistor Structure

Polysilicon GateSiO2

Insulator

n+ n+

p substrate

channel

Source Drain

n transistor

G

S

D

SB

L

W

G

S

D

substrate connected

to GND


3/28

VLSI Design 3

Transistor Structure

p+ p+

n substrate

channel

Source Drain

p transistor

S

D

S

olysilicon ateSi 2

Insulator L

substrate connected

to V DD


4/28

VLSI Design 4

Semiconductor Review

` Create by doping a pure silicon crystal

` Diffuse impurity into crystal lattice

` Changes the concentration of carriers

Electrons

Holes

` More doping -> more carriers available

` n-type semiconductor (n or n+)

` Majority carrier: electrons

` Typical impurity: Arsenic (Column V)

` p-type semiconductor (p or p+)

` Majority carrier: holes

` Typical impurity: oron (Column III)

n

n+

p

p+


5/28

VLSI Design 5

ther key working materials

` Insulator - Silicon Dioxide (Si 2)` Used to insulate transistor gates (thin oxide)

` Used to insulate layers of wires (field oxide)

` Can be grown on Silicon or Chemically Deposited

` olysilicon - polycrystalline silicon` Key material for transistor gates

` Also used for short wires

` Added by chemical deposition

`

Metal - Aluminum (and more recently Copper)` Used for wires` Multiple layers common

` Added by vapor deposition or sputtering


6/28

VLSI Design 6

CM S rocessing

` afer rocessing

` hotolithography

` xide rowth & Removal

` Material Deposition & Removal

` Diffusion of Impurities

` utting it all together


7/28

VLSI Design 7

A View of the Clean room

AMDsDresden Fab - Source:AMD Corporation www.amd.com


8/28

VLSI Design 8

Creating afers - Czochralski Method

` Start with crucible of molten

silicon (1425oC)

` Insert crystal seed in melt

` Slowly rotate / raise seed to form

single crystal boule

` After cooling, slice boule into

wafers & polish

Crucible

Molten

Silicon


9/28

VLSI Design 9

afer Structure

` Current production: 200mm

` Newest technology: 300mm

Die Single IC chip

300mm waferImage Source: Intel Corporation

www.intel.com


10/28

VLSI Design 10

rocessing afers

` All dice on wafer processed simultaneously

` Each mask has one image for each die

` The basic approach:

` Add & selectively remove materials Metal - wires

olysilicon - gates

xide

` Selectively diffuse impurities

` hotolithography is the key


11/28

VLSI Design 11

hotolithography

` Coat wafer with photoresist ( R)

` Shine UV light through mask to

selectively expose R

` Use acid to dissolve exposed R

` Now use exposed areas for

` Selective doping

` Selective removal of material under

exposed Rafer

hotoresist

Mask

UV Light


12/28

VLSI Design 12

Adding Materials

` Add materials on top of silicon

` olysilicon

` Metal

` xide (Si 2) - Insulator

` Methods` Chemical deposition

` Sputtering (Metal ions)

` xidation

Silicon

Added Material(e.g. olysilicon)


13/28

VLSI Design 13

xide (Si02) - The Key Insulator

` Thin xide

` Add using chemical deposition

` Used to form gate insulator & block active areas

` Field xide (F X) - formed by oxidation` et (H20 at 900

oC - 1000oC) or Dry ( 2 at 1200oC)

` Used to insulate non-active areas

Silicon afer Silicon afer

SiN / Si 2F X F XSi 2 Thin xide


14/28

VLSI Design 14

atterning Materials using hotolithography

` Add material to wafer

` Coat with photoresist

` Selectively remove photoresist

` Remove exposed material

` Remove remaining R

Silicon

Added Materiale.g. olysilicon


15/28

VLSI Design 15

Diffusion

` Introduce dopant via epitaxy or ion

implant e.g. Arsenic (N), oron ( )

` Allow dopants to diffuse at high

temperature

`lock diffusion in selective areasusing oxide or R

` Diffusion spreads both vertically,

horizontally

Silicon

Diffusion

locking aterial( xide)


16/28

VLSI Design 16

CM S ell Structures

` Need to accommodate both N, transistors

` Must implement in separate regions - wellls (tubs)

` N-well

` -well` Alternate approach: Silicon on Insulator (S I)

n-wellp substrate

n well

n substrate

p well

p-welln tub p tub insulator

n epi p epi

twin-tub S I


17/28

VLSI Design 17

Detailed View - N- ell rocess

` verall chip doped as p substrate, tied to ND

` Selected well areas doped n, tied to VDD

n+ n+

p substrate

channel

p+ p+

n well

channel

Gnd

n+ n+

s strate

c annel

+ +

n ell

c annel

VDD


18/28

VLSI Design 18

substrate

CM S rocessing - Creating an Inverter

` Substrate

` ell

` Active Areas

` ates` Diffusion

` Insulator

` Contacts

` Metal

wafer

n well


19/28

VLSI Design 19

substrate

CM S Mask Layers

` Determine placement of layout

objects

` Color coding specifies layers

` Layout objects:

` Rectangles

` olygons

` Arbitrary shapes

` rid types

` Absolute (micron)

` Scaleable (lambda)

wafer

n well


20/28

VLSI Design 20

Mask eneration

` Mask Design using Layout Editor

` user specifies layout objects on different layers

` output: layout file

`attern enerator` Reads layout file

` enerates enlarged master image of each mask layer

` Image printed on glass reticle

` Step & repeat camera

` Reduces & copies reticle image onto mask

` ne copy for each die on wafer

` Note importance of mask alignment


21/28

VLSI Design 21

Advanced Fabrication

` lanarization

` Copper Interconnect

` Low-k dielectric for interconnect

` High-k dielectric for transistor gates` ptical problems (and fixes)

` Immersion Lithography

` Maskless Lithography


22/28

VLSI Design 22

Advanced Transistor Fabrication

` Shallow Trench Isolation (STI) to separate transistors -trenches filled with oxide by CVD

` Lightly Doped Drain/Source followed by deeper doping

` Silicon Nitride (SiN) - Spacer

` Silicide - refractory metal (e.g. Ti, t, , Ta, Co) to reduceresistance of polysilicion and diffusion

STI STI

Silicide

olycide

SiN


23/28

VLSI Design 23

lanarization

` roblem: adding multiple layers of metal is difficult over

uneven chip structures

` Solution: lanarization

`Add thick oxide layer over chip

` Use Chemical-Mechanical olishing (CM ) to grind flat

substrate

wafer

n well


24/28

VLSI Design 24

Copper interconnect

` Copper is a much better conductor than aluminum

` ut, it reacts chemically with silicon, oxide

` Fabrication of copper wires: damascene process

`Etch trenches in the surface where wires will be placed

` Coat with secret chemical (isolates Cu, silicon, oxide)

` Coat with layer of copper

` olish wafer to remove copper except in trenches


25/28

VLSI Design 25

Maskless Lithography

` Key idea: instead of shining UV light through mask, expose

photoresist directly

` E- eam - use one or more steerable beams of electrons

` Micromirror array - steer light to expose R

` Imprint lithography - pattern by direct contact

` Intended for low-volume applications


26/28

VLSI Design 26

Silicides

` Make polysilicon a better wire

` Add a refractory metal to polysilicon

e.g., tantalum

` Lower resistance by an order of magnitude

from 50;/sq to 3;/sq

CS/ECE 755

rocessing Variations

Silicides

Make polysilicon a better wire

Add a refractory metal to polysilicon

e.g., tantalum

Lower resistance by an order of magnitudefrom 50 ;/sq to 3 ;/sq

5

silicide gate

polycide metal/silicide salicide

(self aligned silicid)

silicide

polysiliconmetal

polysilicon

silicide

CS/ CE 755 Processing

ariations

Silicides

ake polysilicon a better ire

dd a refractory etal to polysilicon

e.g., tantalu

Lo er resistance by an order of agnitude

fro 50 ;/sq to 3 ;/sq

5

silici e gate

olyci e metal/silici e salici e

(self alig e silici )

silicide

polysiliconmetal

polysilicon

silicide


27/28

VLSI Design 27

After Fabrication- Testing and ackaging

Figure Source: D. Patterson and J. Hennessey, Computer Organization and Design, Morgan Kafumann, 1996


28/28

VLSI Design 28

ottom Line: Moores Law Lives!

` Doubled transistor density compared to

65nm

` enryn - Dual Core, 200M Trans.

` 4-Core, 8-Core chips planned!

Intel enryn(Image source: www.intel.com)

Documents

Lecture1 1 Fabrication+Processing+Steps