Lecture Set 02

8/12/2019 Lecture Set 02

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hapter 2Instructions: Language

of the Computer

[Some slides adapted from A. Sprintson, M. Irwin, D.Paterson and others]


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2

The Instruction Set Architecture (ISA)

instruction set architecture

software

hardware

The interface description separating thesoftware and hardware


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How Do the Pieces Fit Together?

I/O systemProcessor

om!i"er

O!eratingSystem

A!!"ications

Digita" Design

ircuit Design

Instruction SetArchitecture

Firmware

Coordination of many levels of abstraction

Under a rapidlychanging set of forces

Design, measurement, andevaluation

#emory

system

Data!ath $ ontro"

networ%


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The #IPS ISA

Instruction Categories

Load/Store Computational

Jump and ranch

!loating "oint coprocessor

#emory #anagement

Special

&' &*

PHI

+O

OP

OP

OP

rs rt rd sa funct

rs rt immediate

,um! target

Instruction Formats- a"" . its wide

&egisters


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5

Assem"y +anguage Instructions

The language of the machine

$ant an IS% that ma&es it easyto 'uild the hardware and thecompiler while ma(imi)ing performanceand minimi)ing cost

Stored program *von +eumann concept Instructions are stored in memory *as is the data

-ur target. the #I"S IS% similar to other IS%s developed since the 0123s

Design goals: maximize performance, minimize cost,

reduce design time (time-to-market), minimize memory

space (embedded systems), minimize power

consumption (mobile systems)


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&IS &educed Instruction Set om!uter

4ISC philosophy

fi(ed instruction lengths load5store instruction sets

limited num'er of addressing modes

limited num'er of operations

#I"S, %4#, Sun S"%4C, I# "ower"C 6 Instruction sets are measured 'y how well compilers

use them as opposed to how well assem'ly languageprogrammers use them

CISC *C for comple(, e7g7, Intel (18


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7

The Four Design Princi!"es

7 Simplicity favors regularity7

97 Smaller is faster7:7 #a&e the common case fast7

;7


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8

The #IPS ISA

Instruction Categories Load/Store

Computational

Jump and ranch

!loating "oint coprocessor

#emory #anagement

Special

&' &*

P

HI

+O

&egisters


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#IPS &egisters

Unli&e =LL li&e C or Java, assem'ly cannot use

varia'les $hy not> ?eep =ardware Simple

%ssem'ly -perands are registers limited num'er of special locations 'uilt directly into the

hardware

operations can only 'e performed on these@

enefit. Since registers are implemented directly inhardware, they are very fast*faster than 'illionth of a second


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#IPS &egisters

Draw'ac&. Since registers are in hardware, there are

a predetermined num'er of them Solution. #I"S code must 'e very carefully put together to

efficiently use registers

:9 registers in #I"S $hy :9> Large for the time, easier compiling

Small now *'ut we are stuc& with it

Aach #I"S register is :9 'its wide


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' 01eroconstant ' (Hdware)

* 0at reser2ed for assem"er

. 02' e3!ression e2a"uation $

02* function resu"ts

4 0a' arguments

5 0a*

6 0a.

7 0a

8 0t' tem!orary- ca""er sa2es

9 9 9 (ca""ee can c"oer)

*5 0t7

:aming on2entions for &egisters

*6 0s' ca""ee sa2es

9 9 9 (ca""er can c"oer)

. 0s7

.4 0t8 tem!orary (cont;d)

.5 0t

onstant (or Immediate) O!erands


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$hat instruction format is used for the addi>

addi $s3, $s3, 4 #$s3 = $s3 + 4

#achine format.

#achine +anguage > Immediate Instructions


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$hat instruction format is used for the addi>

addi $s3, $s3, 4 #$s3 = $s3 + 4

#achine format.

#achine +anguage > Immediate Instructions

op rs rt 8 'it immediate I format

1 0 0 ;

The constant is &ept inside the instruction itself@ So must use the I format Immediate format Limitsimmediate values to the range H9E to 59E


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Cut point777


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#emory is a large, single5dimensional array

%n addressacts as the inde( into the memory array

Processor

#emory

:9 'its

>locations

read addr/write addr

read data

write data

:9

:9

:9 9:9

ytes*;


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Consider memory to 'e a single huge array.

Aach cell of the array has an address associated with it7 Aach cell also stores some value7

Do you thin& they use signed or unsigned num'ers> +egativeaddress>@

DonBt confuse the addressreferring to a memorylocation with the valuestored in that location7

23 42 ......101 102 103 104 10 ...

"rocessor #emory Interconnections


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%n address refers to a particular memory location7 In

other words, it points to a memory location7 "ointer. % varia'le that contains the address of a

varia'le7

23 42

......

101 102 103 104 10 ...

!"

#o$ation %address&

name

p104



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=ow to create a pointer.

operator. get address of a varia'le

N operator. dereference operator get value pointed to

printf(p points to %d\n,*p);

int *p, x; p ? x ?

! = 3" p ? x 3

=!"p x 3



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=ow to change a varia'le pointed to>

Use dereference operator on left of =

p x 5*p = 5;

p x 3



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Cut "oint777


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MIPS has two basic data transferinstructions for accessing

memory (assume $s3 holds 2410lw $t0! 4($s3 "load word from memory

sw $t0! #($s3 "store word to memory

he data transfer instruction must s%ecify

where in memory to read from (load or write to (store &memory address

where in the register file to write to (load or read from (store &register destination (source

he memory address is formed by summing the constant %ortion of

the instruction and the contents of the second register

%ccessing #emory


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#I"S has two 'asic data transferinstructions for accessing

memory *assume Ks: holds 9;2lw Kt2, ;*Ks: Oload word from memory

sw Kt2, 1*Ks: Ostore word to memory

The data transfer instruction must specify

where in memory to read from *load or write to *store memory address

where in the register file to write to *load or read from *store register destination *source

The memory address is formed 'y summing the constant portion ofthe instruction and the contents of the second register

912

:92

%ccessing #emory

#IPS #emory Addressing


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The memory address is formed 'y summing the

constant portion of the instruction and the contents ofthe second *'ase register

%& $t0, 4($s3) #&hat is %oaded i'to $t0

s& $t0, 8($s3) #$t0 is stored &here

#emory

7 7 7 2 2 2Data $ord %ddress

2

;

1

9

8

92

9;

7 7 7 2 2 2

7 7 7 2 2 2

7 7 7 2 2 2

7 7 7 2 2

7 7 7 2 2

7 7 7 2 2$s3holds 1



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The memory address is formed 'y summing the

constant portion of the instruction and the contents ofthe second *'ase register

%& $t0, 4($s3) #&hat is %oaded i'to $t0s& $t0, 8($s3) #$t0 is stored &here

#emory

7 7 7 2 2 2:9 'it Data $ord %ddress

2

;

1

9

8

92

9;

7 7 7 2 2 2

7 7 7 2 2 2

7 7 7 2 2 2

7 7 7 2 2

7 7 7 2 2

7 7 7 2 2$s3holds 1

in location 8

7 7 7 222

7 7 7 222


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om!i"ing with +oads and Stores

%ssuming varia'le bis stored in $s2and that the 'ase

address of array % is in $s3, what is the #I"S assem'lycode for the C statement

*8 = *2 - b

$s3

$s3H;

$s3H1

$s3H9

7 7 7

%P9Q

%P:Q

7 7 7

%PQ

%P2Q


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om!i"ing with +oads and Stores

%ssuming varia'le bis stored in $s2and that the 'ase

address of array % is in $s3, what is the #I"S assem'lycode for the C statement

*8 = *2 - b

$s3

$s3H;

$s3H1

$s3H9

7 7 7

%P9Q

%P:Q

7 7 7

%PQ

%P2Qlw $t0, 8($s3)

sub $t0, $t0, $s

sw $t0, 3($s3)

om!i"ing with a aria"e Array Inde3


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%ssuming that the 'ase address of array

% is in register $s4, and varia'les ', c,and i are in $s1, $s2, and $s3,respectively, what is the #I"S assem'lycode for the C statement

c = *i - b

add $t1, $s3, $s3 #arra i'de! i is i' $s3

add $t1, $t1, $t1 #te reg $t1 ho%ds 4i

$s4

$s4H;

$s4H1

$s4H97 7 7

%P9Q

%P:Q7 7 7

%PQ

%P2Q



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%ssuming that the 'ase address of array

% is in register $s4, and varia'les ', c,and i are in $s1, $s2, and $s3,respectively, what is the #I"S assem'lycode for the C statement

c = *i - b

add $t1, $s3, $s3 #arra i'de! i is i' $s3

add $t1, $t1, $t1 #te reg $t1 ho%ds 4i

$s4

$s4H;

$s4H1

$s4H97 7 7

%P9Q

%P:Q7 7 7

%PQ

%P2Q

add $t1, $t1, $s4 #addr of *i 'o& i' $t1

%& $t0, 0($t1)

sub $s2, $t0, $s1


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&e2iew- #IPS Instructions@ so far

ategory Instr O!ode

=3am!"e #eaning

%rithmetic add 2 R:9

add Ks, Ks9, Ks: Ks F Ks9 H Ks:

su'tract 2 R:;

su' Ks, Ks9, Ks: Ks F Ks9 5 Ks:

%rithmetic addimmediate

1 addi Ks, Ks9, ; Ks F Ks9 H ;

Data

transfer

load word :E lw Ks, 22*Ks9 Ks F #emory*Ks9H22

store word ;: sw Ks, 22*Ks9 #emory*Ks9H22 F Ks

C t i t


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Cut point7777


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&e2iew- nsigned Binary &e!resentation

=e( inary Decimal

2(22222222 262222 22(2222222 26222

2(22222229 26222 9

2(2222222: 2622 :

2(2222222; 26222 ;

2(2222222E 2622 E

2(22222228 2622 8

2(2222222 262

2(22222221 26222 1

2(22222220 2622 0

6

2(!!!!!!!C 622

2(!!!!!!!D 62

2(!!!!!!!A 62

2(!!!!!!!! 6 9:95

9:95 9

9:95 :

9:95 ; ..

*

* * * 9 9 9 * * * * it

: :2 90 7 7 7 : 9 2 'it position

9: 9:2 990 7 7 7 9: 99 9 92 'it weight

* ' ' ' 9 9 9 ' ' ' ' *

&e2iew- Signed Binary 9Bsc 'inary decimal


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&e2iew- Signed Binary&e!resentation

y

222 51

22 5

22 58

2 5E

22 5;

2 5:

2 59

52222 2

222

222 9

22 :222 ;

22 E

22 8

2 9:5 F

5*9:5 F

59: F

22

complement all the 'its

2

and add a

complement all the 'its

22

and add a

22

# hi + + d I t ti


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Consider the load5word and store5word instrBs

$hat would the regularityprinciple have us do> ut 7 7 7


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Consider the load5word and store5word instrBs

$hat would the regularityprinciple have us do> ut 7 7 7


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#emory Address +ocation

A(ample. %& $t0, 24($s2)#emory

data word address *he(

2(222222222(2222222;2(222222212(2222222c

2(f f f f f f f f

$s2 2(922;20;

2(22222229

2410+ $s2 =

+ote that the offsetcan 'e positiveornegative


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#emory Address +ocation

A(ample. %& $t0, 24($s2)#emory

data word address *he(

2(222222222(2222222;2(222222212(2222222c

2(f f f f f f f f

$s2 2(922;20;

2(22222229

2410+ $s2 =

+ote that the offsetcan 'e positiveornegative

7 7 7 22 222H 7 7 7 222 222 7 7 7 22 22 F 2(922;2ac

2(922;2ac

$t0


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A(ample. s& $t0, 24($s2)

% 85'it offset means access is limited to memorylocations within a range of 9/:F 1,09 words*9/EF

:9,81 'ytes of the address in the 'ase register$s2 9Bs complement * sign 'it H E magnitude 'its

#achine +anguage Store Instruction

op rs rt 8 'it num'er

;: 1 1 9;

22 222 2222 22222222222222


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A(ample. s& $t0, 24($s2)

% 85'it offset means access is limited to memorylocations within a range of H9/:5 to 59/:*1,09 words

*H9/E5 to 59/E*:9,81 'ytes of the address in the'ase register$s2 9Bs complement * sign 'it H E magnitude 'its

#achine +anguage Store Instruction


;: 1 1 9;

22 222 2222 22222222222222

Instruction Format =ncoding


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Instruction Format =ncoding

Can reduce the comple(ity with multiple formats 'y

&eeping them as similaras possi'le !irst three fields are the same in 45type and I5type

Aach format has a distinct set of values in the op field

Instr Frmt o! rs rt rd shamt funct address

add 4 2 reg reg reg 2 :9ten

+%

sub 4 2 reg reg reg 2 :;ten

+%

addi I 1ten

reg reg +% +% +% constant

%& I :Eten

reg reg +% +% +% address

s& I ;:ten reg reg +% +% +% address

OP

OP

rs rt rd sa funct

rs rt immediate

Cut "oint


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Cut "oint


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#IPS Data Ty!es

Bit- 2,

Bit String- seuence of 'its of a particular length ; 'its is a ni''le 1 'its is a 'yte 8 'its is a half5word :9 'its is a word

8; 'its is a dou'le5wordharacter- %SCII 'it code

Decima"-

digits 250 encoded as 22229 thru 229 two decimal digits pac&ed per 1 'it 'yte

Integers- 9s complement

F"oating Point

B d :


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Beyond :umers #ost computers use 15'it 'ytes to represent characters

with the%merican Std Code for Info Interchange *%SCII

So, we need instructions to move 'ytes around

ASII har ASII har ASII har ASII har ASII har ASII har

2 +ull :9 space ;1 2 8; V 08 W 9 p

:: @ ;0 8E % 0 a :

9 :; E2 9 88 01 ' ; r

: :E O E : 8 C 00 c E s

; A-T :8 K E9 ; 81 D 22 d 8 t

E : G E: E 80 A 2 e u

8 %C? :1 R E; 8 2 ! 29 f 1 v

:0 3 EE < 2: g 0 w

1 '&sp ;2 * E8 1 9 = 2; h 92 (

0 ta' ; E 0 : I 2E i 9 y

2 L! ;9 N E1 . ; J 28 M 99 )

;: H E0 E ? 2 & 9: X

9 !! ;; , 82 Y 8 L 21 l 9; Z

E ; / 8: > 0 - o 9 DAL

B t Add


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Byte Addresses Since 15'it 'ytes are so useful, most architectures

address individual 'ytes in memory Therefore, the memory address of a wordmust 'e a

multiple of ; *alignment restriction

ig Andian. leftmost *most significant 'yte is wordaddress I# :82/:2, #otorola 81&, #I"S, Sparc, =" "%

Little Andian. rightmost *least significant 'yte is word

address Intel 12(18, DAC [a(, DAC %lpha *$indows +T

=ndianess


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=ndianess

ig Andian. leftmost 'yte is word address

Little Andian. rightmost 'yte is word address

ms "s

"itt"eendian

igendian

=ndianess


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=ndianess

A(ample. consider the num'er 2(;2 stored in a ;5'yte

integer In 'inary 22222222 22222222 2222222 2222222

00 01 02 03

00000000 00000000 00000100 00000001

00000001 00000100 00000000 00000000'i( )ndian#ittle )ndian

+ di d St i B t


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+oading and Storing Bytes

#I"S provides special instructions to move 'ytes

%b $t0, 1($s3) #%oad bte fro eorsb $t0, .($s3) #store bte to eor

$hat 1 'its get loaded and stored> load 'yte places the 'yte from memory in the rightmost 1 'its of

the destination register $hat happens to the other 'its in the register>

store 'yte ta&es the 'yte from the rightmost 1 'its of a registerand writes it to the 'yte in memory

leaving the other 'ytes in the memory word unchanged


=3am!"e of +oading and Storing Bytes


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add $s3, $zero, $zero%b $t0, 1($s3)sb $t0, .($s3)

#emory

2( 2 2 0 2 9 % 2

Data $ord

%ddress *Decimal

2

;

19

8

92

9;

2( ! ! ! ! ! ! ! !

2( 2 2 2 2 ; 2 92( 2 2 2 2 2 2

2( 2 2 2 2 2 2 2 2

2( 2 2 2 2 2 2 2 2

2( 2 2 2 2 2 2 2 2

$hat value is left in Kt2>

$hat if the machine was littleAndian>

$hat word is changed in #emoryand to what>



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add $s3, $zero, $zero%b $t0, 1($s3)sb $t0, .($s3)

#emory

2( 2 2 0 2 9 % 2

Data $ord

%ddress *Decimal

2

;

19

8

92

9;

2( ! ! ! ! ! ! ! !

2( 2 2 2 2 ; 2 92( 2 2 2 2 2 2

2( 2 2 2 2 2 2 2 2

2( 2 2 2 2 2 2 2 2

2( 2 2 2 2 2 2 2 2Kt2 F 2(22222202

mem*; F 2(!!!!02!!

mem*; F 2(!!9!!!!

$hat value is left in Kt2>

$hat if the machine was littleAndian>

$hat word is changed in #emoryand to what>

Kt2 F 2(2222229

A"ignment


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A"ignment

Ali(nment restri$tion* re+ires thato-e$ts fall on address that is amltiple of their si/e.

2 9 :

ligned

!otligned

#i!s and A"ignment


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#i!s and A"ignment

#I"S supports 'yte addressa'ility.

% 'yte is the smallest unit with its address #I"S restricts memory accesses to 'e aligned as

follows. :95'it word has to start at 'yte address that is multiple of ;

Thus, :95'it word at address ;n includes four 'ytes with

addresses. ;n, ;nH, ;nH9, and ;nH:7 85'it half word has to start at 'yte address that is multiple of 9

Thus, 85'it word at address 9n includes two 'ytes withaddresses. 9n and 9nH7

#I"S supports :95'it addresses. %n address is given as :95'it unsigned integer

Cut point


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Cut point777

Instructions for #a%ing Decisions


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Decision ma&ing instructions

alter the control flow i7e7, change the \ne(t\ instruction to 'e e(ecuted

#I"S conditional 'ranchinstructions.

b'e $s0, $s1, /b% #go to /b% if $s0$s1

be $s0, $s1, /b% #go to /b% if $s0=$s1

A(ample. if (i==) h = i + "

b'e $s0, $s1, /b%1add $s3, $s0, $s1

/b%1

Instructions for #a%ing Decisions

S!ecifying Branch Destinations


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! y g

b'e $s0,$s1,/b%1

add $s3,$s0,$s1

/b%1

The 'ranch distance is limited to 59Eto H9E5

instructions from the *instruction after the 'ranch 'ut most 'ranches are local

5

Another Instruction for hanging F"ow


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Another Instruction for hanging F"ow

#I"S also has an unconditional 'ranchinstruction orMumpinstruction.

/b% #go to /b%

A(ample. if (i6=)h=i+"

e%seh=i-"

be $s0, $s1, %se

add $s3, $s0, $s1 !it%se sub $s3, $s0, $s1!it

om!i"ing Chi"e +oo!s


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om!i"ing Chi"e +oo!s

Compile the assem'ly code for the C &hi%eloop where

iis in $s0, is in $s1, and is in $s2 &hi%e (i6=)

i=i+"

/oo be $s0, $s2, !itadd $s0, $s0, $s1 /oo

!it

asic 'loc& % seuence of instructionswithout 'ranches *e(cept at the end andwithout 'ranch targets *e(cept at the 'eginning

Branching Far Away


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$hat if the 'ranch destination is further away than can

'e captured in 8 'its>

The assem'ler comes to the rescue it inserts

an unconditional Mump to the 'ranch target andinverts the condition

be $s0, $s1, /1

'ecomes

b'e $s0, $s1, /2 /1

/2

Cut "oint


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Cut "oint

& i #IPS I t ti f


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ategory Instr O!d =3am!"e #eaning

%rithmetic add 2 R 92 add Ks, Ks9, Ks: Ks F Ks9 H Ks:

su'tract 2 R 99 su' Ks, Ks9, Ks: Ks F Ks9 5 Ks:

add immediate 1 addi Ks, Ks9, ; Ks F Ks9 H ;

Data

transfer

load word 9: lw Ks, 22*Ks9 Ks F #emory*Ks9H22

store word 9' sw Ks, 22*Ks9 #emory*Ks9H22 F Ks

Cond7'ranch

'r on eual ; 'e Ks, Ks9, L if *KsFFKs9 go to L

'r on not eual E 'ne Ks, Ks9, L if *Ks @FKs9 go to L

&e2iew- Instruction Format =ncoding


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g

Instr Frmt o! rs rt rd shamt funct addressadd 4 2 reg reg reg 2 :9

ten+%

sub 4 2 reg reg reg 2 :;ten

+%

addi I 1ten

reg reg +% +% +% constant

%& I :Eten


s& I ;:ten


A "i B h


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Instructions.b'e $s0, $s1, /b% #go to /b% if $s0$s1be $s0, $s1, /b% #go to /b% if $s0=$s1

#achine !ormats.

=ow is the 'ranch destination address specified>

Assem"ing Branches

op rs rt 8 'it num'er I format

E 8 >>>>

; 8 >>>>


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S!ecifying Branch Destinations

Could use a 'ase register and add to it the85'it offset

which register> Instruction %ddress 4egister

*"C F program counter 5 its use is

automatically implied'y 'ranch

"C gets updated *"CH; during the fetchcycle so that it holds the address of the ne(tinstruction

limits the 'ranch distance to 59E to

H9E5instrBs from the *instruction after the'ranch

'ut most 'ranches are local anyway

b'e $s0,$s1,/b%1

add $s3,$s0,$s1

/b%1

Could specify the memory address

'ut that would reuire a :9 'it field

5

Disassem"ing Branch Destinations


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Disassem"ing Branch Destinations

The contents of the updated "C *"CH; is added to the 8

'it 'ranch offset which is converted into a :9 'it value 'y concatenating two low5order )eros to ma&e it a word address andthen sign5e(tending those 1 'its

The result is written into the "C if the 'ranch condition istrue 5 'efore the ne(t !etch cycle

"C%dd

:9

:9 :9

:9

:9

offset

8

:9

22

sign5e(tend

from the low order 8 'its of the 'ranch instruction

'ranch dstaddress

>%dd

; :9

Offset Tradeoffs


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Offset Tradeoffs

$hy not Must store the 'yteoffset in the low order 8'its> Then the two low order )eros wouldnBt have to'e concatenated, it would 'e less confusing, 6

ut that would limit the 'ranch distance to 59:to H9:5 instrBs from the *instruction after the'ranch

%nd concatenating the two )ero 'its costs usvery little in additional hardware and has noimpact on the cloc& cycle time

Assem"ing Branches =3am!"e


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%ssem'ly codeb'e $s0, $s1, /b%1

add $s3, $s0, $s1/b%1 #achine !ormat of b'e.


op rs rt 8 'it offset I format

E 8

4emem'er%fter the b'einstruction is fetched, the "C is updated so

that it is addressing the addinstruction *"C F "C H ;7 The offset *plus 9 low5order )eros is sign5e(tended and

added to the *updated "C



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%ssem'ly codeb'e $s0, $s1, /b%1

add $s3, $s0, $s1/b%1 #achine !ormat of b'e.


op rs rt 8 'it offset I format

E 8

4emem'er%fter the b'einstruction is fetched, the "C is updated so

that it is addressing the addinstruction *"C F "C H ;7 The offset *plus 9 low5order )eros is sign5e(tended and

added to the *updated "C

2(222

Assem"ing um!s


79/148

79

Instruction. /b% #go to /b%

#achine !ormat.

Assem"ing um!s

op 985'it address J format

9 >>>>

=ow is the Mump destination address specified>%s an a'solute address formed 'y concatenating 22 as the 9 low5order 'its to ma&e it a word

address

concatenating the upper ; 'its of the current "C *now "CH;

Disassem"ing um! Destinations


80/148

80

Disassem"ing um! Destinations

The low order 98 'its of the Mump instr converted into a :9

'it Mump destination address 'y concatenating two low5order )eros to create an 91 'it *word

address and then concatenating the upper ; 'its of the current "C*now "CH; to create a :9 'it *word address

that is put into the "C prior to the ne(t !etch cycle

"C; :9

98

:9

22

from the low order 98 'its of the Mump instruction

A "i B h d


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81

%ssem'le the #I"S machine code *in decimal is fine forthe following code seuence7 %ssume that the addr of thebeinstr is 2(22;22292he(

be $s0, $s1, %seadd $s3, $s0, $s1 !it

%se sub $s3, $s0, $s1

!it

Assem"ing Branches and um!s

Assem"ing Branches and um!s


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82

%ssem'le the #I"S machine code *in decimal is fine forthe following code seuence7 %ssume that the addr ofthe beinstr is 2(22;22292he(

be $s0, $s1, %seadd $s3, $s0, $s1 !it

%se sub $s3, $s0, $s1

!it

g !

0!00400020 4 1. 17 2

0!00400024 0 1. 17 19 0 0!20

0!00400028 2 0000 0100 0 0 0011 002

0!0040002c 0 1. 17 19 0 0!22

0!00400030

dst = (0!0) 0!040003 002(002) = 0!00400030

Cut "oint


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83

Cut "oint

#ore Instructions for #a%ing Decisions


84/148

84

$e have be, b'e, 'ut what a'out 'ranch5if5less5than>

+ew instruction.s%t $t0, $s0, $s1 # if $s0 : $s1

# the'# $t0 = 1

# e%se# $t0 = 0

#achine format.

9

g

op rs rt rd funct

2 8 1 2 ;9 F 2(9a

4 format

Eet #ore Instructions for #a%ing Decisions


85/148

85

Since constant operands are popular in comparisons,

also have s%ti +ew instruction.

s%ti $t0, $s0, 10 # if $s0 : 10 # the'

# $t0 = 1 # e%se

# $t0 = 0

#achine format.

9

g


a 8 1 2(222a

I format

Other Branch Instructions


86/148

86

Other Branch Instructions Can use s%t,be,b'e, and the fi(ed value of 2 in$zeroto createall relative conditions

less than b%t $s1, $s2, /b%

less than or eual to b%e $s1, $s2, /b%

greater than bgt $s1, $s2, /b%

great than or eual to bge $s1, $s2, /b%

%s pseudo instructions they are recogni)ed *ande(panded 'y the assem'ler

The assem'ler needs a reserved register *$at so there are policy of use conventions for registers



87/148

87


Can use s%t,be,b'e, and the fi(ed value of 2 in$zeroto createall relative conditions

less than b%t $s1, $s2, /b%

less than or eual to b%e $s1, $s2, /b%

greater than bgt $s1, $s2, /b%

great than or eual to bge $s1, $s2, /b%

%s pseudo instructions they are recogni)ed *ande(panded 'y the assem'ler

The assem'ler needs a reserved register *$at so there are policy of use conventions for registers

s%t $at, $s1, $s2 #$at set to 1 if

b'e $at, $zero, /b% # $s1 : $s2

-ther "seudo5instructions


88/148

88

Cut "oint


89/148

89

#IPS Organi1ation


90/148

90

Processor#emory

:9 'its

9:2words

read/writeaddr

read data

write data

word address*'inary

26222226222262222622

622

4egister !ile

src addr

src9 addr

dst addr

write data

:9 'its

src

data

src9data

:9registers

*K)ero 5 Kra

:9

:9

:9

:9

:9

:9

E

E

E

%LU:9

:9

:9 2 9 :

8E;

'yte address*'ig Andian

%rithmetic instructions to/from the register file

Load/store instructions 5 to/from memory

#IPS &egister Fi"e


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91

-perands of arithmetic instructions must 'e from a

limited num'er of special locations contained in thedatapathBs register file Thirty5two :95'it registers Two read ports

-ne write port

4egister !ile

src addr

src9 addr

dst addr

write data

:9 'its

srcdata

src9

data

:9locations

:9E

:9

E

E

:9

#IPS &egister Fi"e


92/148

92

4egisters are

!ast Smaller is fasterR #a&e the common case fast

Aasy for a compiler to use e7g7, *%N *CND *AN! can do multiplies in any

order

Improves code density Since registers are named with fewer 'its than a

memory location

4egister addresses are indicated 'y using K

Two ey Princi!"es of #achine Design


93/148

93

y ! g

7 Instructions are represented as num'ers

97 "rograms are stored in memory to 'e read or written,Must li&e num'ers

Stored5program concept

"rograms can 'e shipped asfiles of 'inary num'ers 'inary compati'ility

Computers can inheritready5made softwareprovided they are compati'lewith an e(isting IS% leadsindustry to align around asmall num'er of IS%s

%ccounting prg*machine code

C compiler*machine code

"ayroll

data

Source code inC for %cct prg

#emory

Programming Sty"es


94/148

94

g g y

"rocedures *su'routines, functions allow the

programmer to structure programs ma&ing them easier to understand and de'ug and allowing code to 'e reused

"rocedures allow the programmer to concentrateon one portion of the code at a time parameters act as 'arriers'etween the procedure and

the rest of the program and data, allowing the procedureto 'e passed values *arguments and to return values

*results

Si3 Ste!s in =3ecution of a Procedure


95/148

95

!

#ain routine *caller places parameters in a placewhere the procedure *callee can access them $a05 $a3. four argumentregisters

Caller transfers control to the callee

Callee acuires the storage resources needed

Callee performs the desired tas&Callee places the result value in a place where the

caller can access it $;05 $;1. two valueregisters for result values

Callee returns control to the caller $ra. one returnaddressregister to return to the point of

origin

Instruction for a""ing a Procedure


96/148

96

#I"S procedure callinstruction.

a% rocddress #u a'd %i'

Saves "CH; in register $raas the lin& to thefollowing instruction to set up the procedure return

#achine format.

Then procedure can returnwith Must

r$ra #retur'

g

op 98 'it address J format

: >>>>

Basic Procedure F"ow


97/148

97

Basic Procedure F"ow

!or a procedure that computes the


98/148

98


99/148


100/148

om!i"ing a +eaf Procedure


101/148

101

! g

Leafprocedures are ones that do not call otherprocedures7 (i+)"retur' f" ?

where g, h, i, and are in $a0, $a1, $a2, $a3

%eaf


102/148

102

=3am!"e


103/148

103

=3am!"e

# $s0=ai'

!!!addi $a0,$0,2 # agrue't0=addi $a1,$0,3 # agrue't1=3addi $a2,$0,4 # agrue't2="addi $a3,$0,@ # agrue't3=5a% diffofsus #ca%% rocedure

!!!# $s0=resu%t

diffofsus#ddi $sp, $sp, .- ' sp# on st#' to stor tr r+istrss& $s0, 8(s) # sa;e $s0 o' stacs& $s1, 4(s) # sa;e $s1 o' stac

s& $s2, 0(s) # sa;e $s2 o' stac#dd $s-, $#0, $#- $s-=f+#dd $s, $#, $#3 $s=isub $s0, $s-, $s rsult = (f+).(i)#dd $/0, $s0, $0 put rturn /#lu in $/0l& $s2, 0(s) # restore $s2 fro stacl& $s1, 4(s) # restore $s1 fro stacl& $s0, 8(s) # restore $s0 fro stac#ddi $sp,$sp, - d.#llo#t st#' sp#r $r# rturn to #llr


104/148

104

:ested Procedures


105/148

105

$hat happens to return addresses with nestedprocedures>i't rt


106/148

106

ca%%er a% rt


107/148

107

+ested procedures *ipassed in$a0, return value in $;0

rt


108/148

108

high addr

$s

%o& addr

$raca%%er rt addr

o%d ABC


rt


109/148

109

ca%%er rt addr

high addr

$s

$s

%o& addr

o%d $a0

$raca%%er rt addr

o%d ABC


rt


110/148

110

ca%%er rt addr

high addr

$s

$s

%o& addr

o%d $a0

$raca%%er rt addrb


111/148

111

ca%%er rt addr

high addr

$s

%o& addr

o%d $a0

$rab


112/148

112

ca%%er rt addr

high addr

$s

$s

%o& addr

o%d $a0

$rab


113/148

113

:ame &egister

:umer

sage Preser2e on

ca""?

K)ero 2 the constant 2 n7a7

Kv2 5 Kv 95: returned values no

Ka2 5 Ka: ;5 arguments ]esN

Kt2 5 Kt 15E temporaries no

Ks2 5 Ks 859: saved values yes

Kt1 5 Kt0 9;59E temporaries no

Kgp 91 glo'al pointer yes

Ksp 90 stac& pointer yes

Kfp :2 frame pointer yes

Kra : return address yes

he $onention sed in the -oo does not presere a0a3

Chat is and what is not !reser2ed acrossa !rocedure ca""9


114/148

114

A""ocating S!ace on the Stac%


115/148

115

The segment of the stac&

containing a procedureBssaved registers and localvaria'les is its procedureframe*a&a activation

record The frame pointer *$f

points to the first word ofthe frame of a procedure providing a sta'le 'ase

register for the procedure $fis initiali)ed using $son a

call and $sis restored using$fon a return

%o& addr

high addr

$s

Ca;ed argue't

regs (if a')

Ca;ed retur' addr

Ca;ed %oca% regs

(if a')

/oca% arras

structures (if

a')

$f

A""ocating S!ace on the Hea!


116/148

116

Static data segment forconstants and otherstatic varia'les *e7g7,arrays

Dynamic data segment*a&a heap forstructures that growand shrin& *e7g7, lin&edlists%llocate space on the

heap with a%%oc()and free it with free()

#emory

2( 2222 2222

Te3t(Eour code)

&eser2ed

Static data

2( 22;2 2222

2( 222 22222( 222 1222

2( f f f f f f c

Stac%

Dynamic data(hea!)

Ksp

Kgp

"C

om!i"ing a &ecursi2e Procedure


117/148

117

% procedure for calculating factorial i't fact (i't ')

if (' : 1) retur' 1" e%se retur' (' fact ('-1))" ?

% recursiveprocedure *one that calls itself@fact *2 F

fact * F N F

fact *9 F 9 N N F 9

fact *: F : N 9 N N F 8

fact *; F ; N : N 9 N N F 9;

7 7 7

%ssume 'is passed in $a0 result returned in$;0

om!i"ing a &ecursi2e Procedure


118/148

118

fact addi $s, $s, -8 #adust stac oi'ters& $ra, 4($s) #sa;e retur' address

s& $a0, 0($s) #sa;e argue't 's%ti $t0, $a0, 1 #test for ' : 1be $t0, $zero, /1 #if ' D=1, go to /1addi $;0, $zero, 1 #e%se retur' 1 i' $;0addi $s, $s, 8 #adust stac oi'terr $ra #retur' to ca%%er

/1 addi $a0, $a0, -1 #' D=1, so decree't 'a% fact #ca%% fact &ith ('-1)#this is &here fact retur's

b


119/148

119

$s

$ra

$a0

$;0

o%d ABC

Stac& state aftere(ecution of firstencounter with the a%instruction *secondcall tofact routine with $a0nowholding save return address to

caller routine *i7e7, locationin the main routine wherefirstcall to fact is made

on the stac& save original value of $a0

on the stac&

A +oo% at the Stac% for 0a' G .@ Part *

S f


120/148

120

$s

$ra

$a0

$;0

ca%%er rt addr

2

o%d ABC

Stac& state aftere(ecution of first

encounter with the a%instruction *secondcall tofact routine with $a0nowholding saved return address to


on the stac& saved original value of$a0on the stac&


St & t t ft


121/148

121

$s

$ra

$a0

$;0

$s

ca%%er rt addr

ca%%er rt addr

$a0 = 2

2

o%d ABC

Stac& state aftere(ecution of first

encounter with the a%instruction *secondcall tofact routine with $a0nowholding saved return address to


on the stac& saved original value of$a0on the stac&


St & t t ft


122/148

122

$s

$ra

$a0

$;0

$s

ca%%er rt addr

ca%%er rt addr

$a0 = 2

21

b


123/148

123

$ra

$a0

$;0

$s

ca%%er rt addr

$a0 = 2

1

b


124/148

124

$ra

$a0

$;0

$s

ca%%er rt addr

$a0 = 2

10

b


125/148

125

$ra

$a0

$;0

b


126/148

126

$ra

$a0

$;0

b


127/148

127

$ra

$a0

$;0

b


128/148

128

$ra

$a0

$;0

$s

b


129/148

129

$ra

$a0

$;0

$s

b


130/148

130

$ra

$a0

$;0

$s

b


131/148

131

$ra

$a0

$;0

$s

b


132/148

132

$ra

$a0

$;0

$s

b


133/148

133

$ra

$a0

$;0

$s

b


134/148

134

$ra

$a0

$;0

$s

b


135/148

135

How Aout +arger onstants?


136/148

136

$ed also li&e to 'e a'le to load a :95'it

constant into a register#ust use two instructions, new \load upper

immediate\ instruction%ui $t0, 0!aaaa

Then must get the lower order 'its right, i7e7,ori $t0, $t0, 0!aaaa

8 2 1 22222222

22222222

2222222222222222 22222222

2222222222222222

How Aout +arger onstants?


137/148

137

$ed also li&e to 'e a'le to load a :95'it

constant into a register#ust use two instructions, new \load upper

immediate\ instruction%ui $t0, 0!aaaa

Then must get the lower order 'its right, i7e7,ori $t0, $t0, 0!aaaa

f 2 1 22222222

22222222

2222222222222222 22222222

2222222222222222

22222222 22222222

Shift O!erations

1


138/148

138

+eed operations to pac&and unpac&15'it

characters into :95'it wordsShifts move all the 'its in a word left or right

s%% $t2, $s0, 8 #$t2 = $s0 :: 8 bits

sr% $t2, $s0, 8 #$t2 = $s0 DD 8 bits

op rs rt rd shamt funct

Such shifts are called logical'ecause they fillwith )eros+otice that a E5'it shamt field is enough to shift a

:95'it value 9E or : 'it positions

2 8 2 1 2(22

4 format


139/148

om!i"ing Another Chi"e +oo!

C il th 'l d f th C


140/148

140

Compile the assem'ly code for the C &hi%e

loop where iis in $s3, is in $s@, and the'ase address of the array sa;eis in $s.

&hi%e (sa;e*i == )i += 1"

om!i"ing Another Chi"e +oo!

C il th 'l d f th C


141/148

141

Compile the assem'ly code for the C &hi%e

loop where iis in $s3, is in $s@, and the'ase address of the array sa;eis in $s.

&hi%e (sa;e*i == )i += 1"

/oo s%% $t1, $s3, 2add $t1, $t1, $s. %&

$t0, 0($t1) b'e $t0, $s@,!it addi $s3, $s3, 1

/oo!it

Cut "oint


142/148

142



143/148

143

ategory Instr O! =3am!"e #eaning

%rithmetic

*4 R Iformat

add 2 R 92 add Ks, Ks9, Ks: Ks F Ks9 H Ks:

su'tract 2 R 99 su' Ks, Ks9, Ks: Ks F Ks9 5 Ks:

add immediate 1 addi Ks, Ks9, ; Ks F Ks9 H ;

shift left logical 2 R 22 sll Ks, Ks9, ; Ks F Ks9 YY ;

shift right logical 2 R 29 srl Ks, Ks9, ; Ks F Ks9 __ ; *fill with)eros

shift rightarithmetic

2 R 2: sra Ks, Ks9, ; Ks F Ks9 __ ; *fill withsign 'it

and 2 R 9; and Ks, Ks9, Ks: Ks F Ks9 R Ks:

or 2 R 9E or Ks, Ks9, Ks: Ks F Ks9 Z Ks:

nor 2 R 9 nor Ks, Ks9, Ks: Ks F not *Ks9 Z Ks:

and immediate c and Ks, Ks9, ff22 Ks F Ks9 R 2(ff22

or immediate d or Ks, Ks9, ff22 Ks F Ks9 Z 2(ff22

load upperimmediate

f lui Ks, 2(ffff Ks F 2(ffff2222




144/148

144


Data

transfer

*I format

load word 9: lw Ks, 22*Ks9 Ks F #emory*Ks9H22

store word 9' sw Ks, 22*Ks9 #emory*Ks9H22 F Ks

load 'yte 92 l' Ks, 2*Ks9 Ks F #emory*Ks9H2

store 'yte 91 s' Ks, 2*Ks9 #emory*Ks9H2 F Ks

load half 9 lh Ks, 2*Ks9 Ks F #emory*Ks9H29

store half 90 sh Ks, 2*Ks9 #emory*Ks9H29 F Ks

Cond7 'ranch

*I R 4 format

'r on eual ; 'e Ks, Ks9, L if *KsFFKs9 go to L

'r on not eual E 'ne Ks, Ks9, L if *Ks @FKs9 go to L

set on less thanimmediate

a slti Ks, Ks9, 22 if *Ks9Y22 KsF elseKsF2

set on less than 2 R 9a slt Ks, Ks9, Ks: if *Ks9YKs: KsF else

KsF2

Uncond7Mump

Mump 9 M 9E22 go to 2222

Mump register 2 R 21 Mr Kt go to Kt

&e2iew- #IPS &''' ISA

Instruction Categories&egisters


145/148

145

Instruction Categories Load/Store Computational Jump and ranch !loating "oint coprocessor

#emory #anagement Special

: Instruction !ormats. all :9 'its wide

&' &*

P

HI+O

-" rs rt rd shamt funct

-" rs rt 8 'it num'er

-" 98 'it Mump target

g

4 format

I format

8 'its E 'its E 'its E 'its E 'its 8 'its

J format

#IPS Organi1ation

Processor


146/148

146

Processor#emory

:9 'its

9:2

words

read/writeaddr

read data

write data

word address*'inary

26222226222

262222622

622

4egister !ile

src addr

src9 addr

dst addr

write data

:9 'its

srcdata

src9data

:9registers

*K)ero 5 Kra

:9

:9

:9

:9

:9

:9

E

E

E

"C

%LU

:9 :9

:9

:9

:9

2 9 :8E;

'yte address*'ig Andian

!etch"C F "CH;

DecodeA(ec

%dd:9

:9;

%dd:9

:9'r offset

#IPS Addressing #odes

4egister addressing operand is in a register


147/148

147

4egister addressing operandis in a register

ase *displacement addressing operandis atthe memory location whose address is the sum ofa register and a 85'it constant contained withinthe instruction

Immediate addressing operandis a 85'it

constant contained within the instruction"C5relative addressing instruction addressis the

sum of the "C and a 85'it constant containedwithin the instruction

"seudo5direct addressing instruction addressisthe 985'it constant contained within the instructionconcatenated with the upper ; 'its of the "C

Addressing #odes I""ustrated7 4egister addressing

op rs rt rd funct 4egister


148/148

op rs rt rd funct 4egister

word operand

op rs rt offset

97 ase addressing

'ase register

#emory

word or 'yte operand

:7 Immediate addressing

op rs rt operand;7 "C5relative addressing

op rs rt offset

"rogram Counter *"C

#emory

'ranch destination instruction

E7 "seudo5direct addressing#emory

Documents

Lecture Set 02