Lecture Outline VLSI Fundamentals · for Assume: bulk at VDD the unit n/pMOS transistors " p For scaled MOS device with scale factors κ n, κ p ≥ 1, i.e. W = κW un (W p = κ p

1

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Lec 12: February 22, 2018 Combination Logic: CMOS

Penn ESE 570 Spring 2018 – Khanna

Lecture Outline

!  CMOS Gates "  1st order delay of Gates "  Gate design

"  Sizing, fanin

!  CMOS Worst Case Analysis

3 Penn ESE 570 Spring 2018 – Khanna

Review: 1st Order RC Delay Models

4

!  Equivalent circuits used for MOS transistors "  Ideal switch + “effective” ON resistance + load

capacitance "  Define unit resistance, Ru: “effective” ON resistance of unit transistor

with min length and W=Wu (usually min width) "  Define Run and Rup for nMOS and pMOS respectively

"  Cgb = Cg and Cdb = Csb = Cd for the unit n/pMOS transistors "  For scaled MOS device with scale factors κn, κp ≥ 1, i.e. Wn = κnWun

(Wp = κpWup) "  “effective” ON resistance Rn= Run/κn (Rp= Rup/κp) "  capacitances κnCd, κnCg (κpCd, κpCg)

τ PHL ≈ 0.69 ⋅Cload ⋅Rn Cload ≈ Cdbn + Cdbp + Cint + Cgb


Review: 1st Order Switch-RC MOS Models

5

nMOS

Rn = Run/κn

Assume: bulk at GND

κnCg

κnCd

κnCd

ON/OFF

(W/L)n

pMOS VDD

VDD VDD Rp = Rup/κp

Assume: bulk at VDD κpCd

κpCd ON/OFF

(W/L)p

κpCg

Rup ≈VDDLup

0.69µpCoxWup(VDD− |VT 0 p |)2

Run ≈VDDLun

0.69µnCoxWun (VDD −VT 0n )2

(W/L)n = κn (W/L)un

(W/L)p = κp (W/L)up

Rup= µn/µp Run


Review: 1st Order Delay Model -τPHL

6

Rn Cd

Cd

nCg

nκpCg

κpCd

κpCd

VDD VDD

VDD VDD

Y

Cs = Cd= Cdiff


κp κp

1 1 A Y

VDD VDD

where Wn=Wunit => κn=1, Rn=Run

Wp = κpWunit

κp = µn/ µp = 2

Rp = Rup/κp = Rn

1,κp

1,κp

1,κp

n

2

1

Rp

Review: 1st Order Delay Model -τPHL

7

Rn Cd

Cd

nCg

nκpCg

κpCd

κpCd

VDD VDD

VDD VDD

Y

Rp VDD

VDD

κpCd

nκpCg

κnC κnC

Rn/n Rn Cd nCg

Y

Cload = (1 + κp)(Cd + nCg)

τ PHL ≈ 0.69RnCload = 0.69Rn (1+κ p )(Cd + nCg )

τ PHL = τ PLHPenn ESE 570 Spring 2018 – Khanna

2

Review: Elmore Delay: Distributed RC network

!  The delay from source to node i "  N = number of nodes in circuit

8

Rik = Rj∑ ⇒ (Rj ∈ [path(s→ 4)∩ path(s→ k)])

τ Di = CkRikk=1

N

∑

τ Di =C1(R1)+C2 (R1)+C3(R1 + R3)+C4 (R1 + R3)+Ci (R1 + R3 + Ri )

(0 # 50%)

τ D = RpCload (0 # 63%)

NOTE:

τ p = 0.69τ DPenn ESE 570 Spring 2018 – Khanna

Combinational Logic

CMOS


CMOS Combinational Logic

!  Complimentary MOSFET "  Pull-up/pull-down complimentary networks

10

pMOS Net = dual (nMOS Net)


Two-Input NOR Gate (NOR2)

11

For Complimentary CMOS: Pull-up Net = dual (Pull-down Net)

F (VF) A (VA)

Z (VZ)

B (VB)

A (VA)

B (VB)

(A . B)

F (VF)

(A + B)

(A . B) (A + B) = Penn ESE 570 Spring 2018 – Khanna

Data Dependent Delay

!  Drive resistance depends on input values "  Delay depends on input data "  Analyze using worst case delay




!  Reminder: "  Rn= Run/κn

"  Rp= Rup/κp

"  Assume: µn=2µp

"  What is Rout? "  Output drive resistance


3




"  Rp= Rup/κp


"  What is Rout? "  Depends on input

"  What is worst case Rout?





"  Rp= Rup/κp



"  What is worst case Rout? "  Choose κp and κn, such that worst-case Rout=Run/2





"  Rp= Rup/κp



"  What is worst case Rout? "  What is input capacitance?


NAND2 – 1st Order Models


"  Rp= Rup/κp


"  Choose κp and κn, such that worst-case Rout=Run/2 "  What is input capacitance?


Series Transistors


Transistor Sizing

!  What gate is this? !  Size (κp and κn) equalize rise/fall

times Rout=Run/2? !  Input Capacitance?


4

Transistor Sizing

!  NAND2 sized for Rout=Run/2 "  κp=4 and κn=4 "  Cin=8Cg

!  NAND3 sized for Rout=Run/2 "  κp=4 and κn=6 "  Cin=10Cg


Increasing Fanin

!  What happens to input capacitance as fanin (k) increases "  Keeping output drive the same

"  E.g. Rdrive=R0/2

!  k-input nand gate has what input capacitance?


Fanin

!  Conclude: gates slow down with fanin "  Less drive per input capacitance "  CInLoad/Ids increases


Transistor Sizing: INV

!  Size (κp and κn) equalize rise/fall times Rout=Run/2?

!  Input Capacitance?


Which is Faster?

!  nand32 Assume: -  Rup=2Run and gates are sized for Rout=Run/2 -  Input also driven by Rdrive = Run/2

nand4-inv-nand4-inv-nand2 (nand2-inv)4-nand2 24 Penn ESE 570 Spring 2018 – Khanna

Lesson

!  Large gates are slow / inefficient "  High capacitive load / drive current

!  Small gates can be inefficient "  Need many stages

!  Staging over moderate size gates minimizes delay !  Exact size will be technology dependent


5

26

And-Or Chain


Delay of each implementation?


Take Away?


CMOS NOR2 VTC

29

Kenneth R. Laker, University of Pennsylvania,

updated 26Feb15

3 VTC Cases V1 = 0 V; V2 = 0 → VDD V1 = 0 → VDD; V2 = 0 V1 and V2 = 0 → VDD simultaneously

Vout

Vin 0

simultaneous switching

only one input

switches

VDD

Switching Threshold Voltage: V1 = V2 = Vout = Vth


CMOS NOR2 Vth

30


updated 26Feb15


k pEQV= k p/2

k nEQV= 2k n

k p

k p

k n k n

Review: CMOS Inverter: Vth

31

k 'n2

WL

!

"#

$

%&n

Vin −VT 0n( )2 =k 'p2

WL

!

"#

$

%&p

Vin −VDD −VT 0 p( )2

kR Vth −VT 0n( )2 = Vth −VDD −VT 0 p( )22

Vth =VT 0n +

1kR

VDD +VT 0 p( )

1+ 1kR

Typically, Ln=Lp=Lmin

kR =k 'n W L( )nk 'p W L( )p

=µn W L( )nµp W L( )p

=µnWn

µpWp


6

CMOS NOR2 Vth

32


updated 26Feb15


k pEQV= k p/2

k nEQV= 2k n

k p

k p

k n k n

CMOS NOR2 Vth

33

k pEQV= k p/2

k nEQV= 2k n

k p

k p

k n k n

Vth =VDD2

kpEQVknEQV

=1

Symmetric ‘Inv’

&

kp = 4knPenn ESE 570 Spring 2018 – Khanna

Parasitic Caps for NOR2 (worst case)

34

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd

Csb1p = Csb2p = Cd Cd

Cd

Cd

Cd Cd



35

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd


Cd

Cd

Cd Cd

V1 = 0, V2 = VDD-> 0 @t=0 & Vx ≈ Vout = 0 -> VDD



36

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd


Cd

Cd

Cd Cd

V1 = 0, V2 = VDD-> 0 @t=0 & Vx ≈ Vout = 0 -> VDD Cload-NR2 ≈ 2Cd + 3Cd + Cint + 2Cg

RpEQV = Rp2+Rp1 Lumped Model Penn ESE 570 Spring 2018 – Khanna


37

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd


Cd

Cd

Cd Cd

V1 = 0, V2 = VDD-> 0 @t=0 & Vx ≈ Vout = 0 -> VDD

Elmore Model? Cload-NR2 ≈ 2Cd + 3Cd + Cint + 2Cg

RpEQV = Rp2+Rp1


7


38

Vx

2Cg

Cd

Cd

Cd

Cd Cd



39

Vx

2Cg

Cd

Cd

Cd

Cd Cd


τ = (2Cd)(Rp2)+(3Cd+Cint+2Cg)(Rp1+Rp2)


40

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd


Cd

Cd

Cd Cd



41

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd


Cd

Cd

Cd Cd

V1 = 0, V2 = 0 ->VDD @t=0 & Vx ≈ Vout=VDD-> 0



42

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd


Cd

Cd

Cd Cd

V1 = 0, V2 = 0 ->VDD @t=0 & Vx ≈ Vout=VDD-> 0

Elmore Model? Penn ESE 570 Spring 2018 – Khanna


43

Vx

2Cg

Cd

Cd

Cd

Cd Cd


8


44

Vx

2Cg

Cd

Cd

Cd

Cd Cd


τ = (2Cd)(Rp1+Rn2)+(3Cd+Cint+2Cg)(Rn2)

45


updated 26Feb15

CMOS NAND2 Vth

k pEQV= 2 k p

k nEQV= kn/2k n

k n

k p k p


46


updated 26Feb15

CMOS NAND2 Vth

k pEQV= 2 k p

k nEQV= kn/2k n

k n

k p k p


47


updated 26Feb15

CMOS NAND2 Vth

k pEQV= 2 k p

k nEQV= kn/2k n

k n

k p k p

Vth =VDD2

kpEQVknEQV

=1

Symmetric ‘Inv’

&

4kp = knPenn ESE 570 Spring 2018 – Khanna

48

Vx

V1

V2

2Cg

Cdbp1 = Cdbp2 = Cdbp

Cdbn1 = Cdbn2 = Cdbn

Csb1n = Csb2n = Csbn = Cdbn

Parasitic Caps for NAND2 (worst case)


49

Vx

V1

V2

2Cg






9

50

Vx

V1

V2

2Cg





V1 = VDD, V2 = VDD-> 0 @t=0 & Vx ≈ Vout= 0 ->VDD


51

Vx

V1

V2

2Cg






52

Vx

V1

V2

2Cg





V1 =VDD, V2 = 0 ->VDD @t=0 & Vx≈ Vout=VDD-> 0


Driving Large Load


Driving large load

54

CLOAD

standard CMOS logic on

die

INV1


Driving large load

55

CLOAD


die

INV1

A DESIGN STRATEGY: Make buffer (W/L)n and (W/L)p sufficiently large to drive CLOAD with a specified τP.

Buffer

How do you feel about this design strategy?


10

Driving large load

56

CLOAD


die

INV1

A DESIGN STRATEGY: Make buffer (W/L)n and (W/L)p sufficiently large to drive CLOAD with a specified τP.

Buffer

How do you feel about this design strategy?

What happens to Cin as (W/L)n and (W/L)p sufficiently large? What is the impact on the standard CMOS logic on the die?


Super-Buffer to Drive Large CLOAD

57

CLOAD

CLOAD

PROBLEM: A minimum sized inverter drives a large load CLOAD, leading to

excessive delay, even with a large buffer (large W/L). SOLUTION: Insert N inverter stages in cascade with

increasing W/L between INV1 and load CLOAD. The total delay through N smaller stages will be less than the delay

through a single large stage driving CLOAD.

VDD

VDD N = 3


die

INV1

CLOAD



58

INV1

Stage-0

a -> stage scale factor > 1

NOTE for CMOS INV: Cd = Cdbn + Cdbp Cg = Cgbn + Cgbp

CLOAD



59

INV1

Stage-0


Wn1 = aWn0, Ln1 = Ln0 and Wp1 = aWp0, Lp1 = Lp0


CLOAD



60

INV1

Stage-0


Wn2 = aWn1, Ln2 = Ln1 and Wp2 = aWp1, Lp2 = Lp1


CLOAD



61

INV1

Stage-0


Wni = aiWn0, Lni = Ln0 and Wpi = aiWp0, Lpi = Lp0 for i = 0, 1, 2, ..., N


CLOAD


11


62

INV1

Stage-0



Stage load capacitances Cloadi are also scaled by a

Cloadi = ai Cload0 = ai (Cd + aCg) for i = 0, 1, 2, .., N


CLOAD



63

INV1

Stage-0




Cloadi = ai Cload0 = ai (Cd + aCg) for i = 0, 1, 2, .., N when i = N: CloadN = aN Cload0 = aN (Cd + aCg) => let CLOAD = aN(aCg) = aN+1Cg


CLOAD



64

INV1

Stage-0




Cloadi = ai Cload0 = ai (Cd + aCg) for i = 0, 1, 2, .., N when i = N: CloadN = aN Cload0 = aN (Cd + aCg) => let CLOAD = aN(aCg) = aN+1Cg

CLOAD/Cg = aN+1 =>

NOTE for CMOS INV:

N is rounded up to nearest integer value.

Cd = Cdbn + Cdbp Cg = Cgbn + Cgbp

CLOAD

N =ln(CLOAD Cg )

lna−1


65

NOTE: ALL inverters Stage-0 through Stage-N have the same gate delay

CLOAD

CLOAD

τ p =τ PHL +τ PLH

2= Γ

Cload

W



66


Let τ0 = gate delay for INV1 (with a = 1) with load Cload = Cd + Cg

CLOAD

CLOAD


2= Γ

Cload

W


τ0 = (Cd +Cg ) W0


67


CLOAD

CLOAD


2= Γ

Cload

W


τ p0

τ 0=

Cload0 W0

(Cd +Cg ) W0

=Cd + aCg

Cd +Cg

⇒ τ p0 = τ 0Cd + aCg

Cd +CgFor Stage-0:


τ0 = (Cd +Cg ) W0

12

68

CLOAD

CLOAD


τ p0

τ 0=

Cload0 W0

(Cd +Cg ) W0

=Cd + aCg

Cd +Cg


Cd +CgFor Stage-0:

For Stage-1:

For Stage-N:

τ p1

τ 0=

Cload1 aW0

(Cd +Cg ) W0

=aCd + a

2Cg( ) / aCd +Cg


Cd +Cg

= τ p0

τ pN

τ 0=CloadN aNW0

(Cd +Cg ) W0

=aNCd + a

N+1Cg( ) / aNCd +Cg

⇒ τ pN = τ 0Cd + aCg

Cd +Cg

= τ p0


69

CLOAD

CLOAD


τ p0

τ 0=

Cload0 W0

(Cd +Cg ) W0

=Cd + aCg

Cd +Cg


Cd +CgFor Stage-0:

For Stage-1:

For Stage-N:

τ p1

τ 0=

Cload1 aW0

(Cd +Cg ) W0

=aCd + a

2Cg( ) / aCd +Cg


Cd +Cg

= τ p0

τ pN

τ 0=CloadN aNW0

(Cd +Cg ) W0

=aNCd + a

N+1Cg( ) / aNCd +Cg

⇒ τ pN = τ 0Cd + aCg

Cd +Cg

= τ p0

τ total = (N +1)τ p0 = (N +1)τ 0Cd + aCg

Cd +Cg

Choose N and a to minimize τtotal Penn ESE 570 Spring 2018 – Khanna


70

Wni = aiWn0 Wpi = aiWp0

TO MINIMIZE τtotal:


Cd +Cg

N =ln(CLOAD Cg )

lna−1

τ total =ln(CLOAD Cg )

lnaτ 0Cd + aCg

Cd +Cg

dτ totalda

= τ 0 ⋅ lnCLOAD

Cg

⋅−1/ alna( )2

Cd + aCg

Cd +Cg

+1lna

Cg

Cd +Cg

#

$%%

&

'((= 0

−1/ alna( )2

Cd + aCg

Cd +Cg

+1lna

Cg

Cd +Cg

= 0

aopt lnaopt −1#$ &'=Cd

Cg



71

Wni = aiWn0 Wpi = aiWp0

TO MINIMIZE τtotal:


Cd +Cg

N =ln(CLOAD Cg )

lna−1

τ total =ln(CLOAD Cg )

lnaτ 0Cd + aCg

Cd +Cg

dτ totalda

= τ 0 ⋅ lnCLOAD

Cg

⋅−1/ alna( )2

Cd + aCg

Cd +Cg

+1lna

Cg

Cd +Cg

#

$%%

&

'((= 0

−1/ alna( )2

Cd + aCg

Cd +Cg

+1lna

Cg

Cd +Cg

= 0

aopt lnaopt −1#$ &'=Cd

Cg

Cd = 0 is only an academic special case. Penn ESE 570 Spring 2018 – Khanna

72

EXAMPLE: Design a Buffer using a scaled cascade of inverters to achieve minimum total delay ttotal when CLOAD = 100 Cg. Consider the case where Cd = 2Cg.

e

Cd = 2Cg => plot aopt as function of Cd/Cg: aopt = 4.35 => ln aopt = 1.47

CLOAD≈ 100Cg

CdCg

= aopt [ln aopt− 1]Cd

Cd/Cg = 2

aopt= 4.35


N =ln(CLOAD Cg )

lna−1= 2.13→ N = 3


Idea

!  CMOS Logic "  Complimentary dual pull-up/down networks

!  Delay "  1st order model on gates "  Size for worst case delay

!  Gates have different efficiencies "  Drive strength per unit input capacitance "  Reason to prefer nand over nor

!  Large fanin and fanout slow gates "  Decompose into stages "  …but not too much

!  Drive large load in scaled stages


13

Admin

!  HW 5 due Thursday, 3/1


Documents

Lecture Outline VLSI Fundamentals · for Assume: bulk at VDD the unit n/pMOS transistors " p For scaled MOS device with scale factors κ n, κ p ≥ 1, i.e. W = κW un (W p = κ p