Lecture 7 - CpE 690 Introduction to VLSI Design

8/13/2019 Lecture 7 - CpE 690 Introduction to VLSI Design

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CpE 690: Introduction to VLSI DesignFall 2013

Lecture 7

CMOS Transistor Theory and DC Response

1

Bryan Ackland

Department of Electrical and Computer Engineering

Stevens Institute of Technology

Hoboken, NJ 07030

Adapted from Lecture Notes, David Mahoney Harris CMOS VLSI Design


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So far, we have treated transistors as ideal switches

An ON transistor passes a finite amount of current Depends on terminal voltages Derive current-voltage (I-V) relationships

Transistor gate, source, drain all have capacitance

I = C (V/t) -> t = (C/I) V Capacitance and current determine speed

Also revisit what a degraded level means

Introduction

nMOS pMOS


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Gate and body formMOS capacitor:

Accumulation:Vg< 0

Depletion:0 < Vg< Vt

Inversion:Vg> Vt

MOS Capacitor


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Mode of operation depends on Vg, Vd, Vs

Vgs= Vg VsVgd = Vg VdVds= Vd Vs= Vgs Vgd

Source and drain are (physically)symmetric terminals By convention, nMOS source is terminal at

lower voltage Hence Vds0

nMOS body is grounded (0 volts).

For now, assume source is grounded too. Three regions of operation

Cutoff Linear

Saturation

nMOS Terminal Voltages

Vg

Vs Vd

Vgs Vgd

Vds


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Vgs< Vt : No channel

Source-body and drain-body junctions are reverse biased Ids 0

nMOS Cutoff

+-

Vgs

= 0

n+ n+

+-

Vgd

p-type body

b

g

s d


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Vgs< Vt : Channel forms

Current flows from drainto source electrons go from source

to drain

Ids increases with Vds Similar to linear resistor

Also called:

resistive triode non-saturated

nMOS Linear


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If Vds > VgsVtthen Vgd < Vt: channel pinches off

Conduction due to drift induced by positive drain voltage Idsindependent of Vds We say channel current saturates Similar to current source

nMOS Saturation

+-

Vgs

> Vt

n+ n+

+-

Vgd

< Vt

Vds

> Vgs

-Vt

p-type body

b

g

s d Ids


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In linear region, Idsdepends on

How much chargeis in the channel? Howfastis the charge moving?

Linear I/V Characteristics


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MOS structure looks like parallel plate capacitor while

operating in inversion Gate : oxide : channel Qchannel= C =

V =

Channel Charge

C.V

Cg= ox.W.L/tox= Cox.W.L where Cox= ox/ toxCoxis gate capacitance perunit area

Vgc Vt= (Vgs Vds/2) Vt

n+ n+

p-type body

W

L

tox

SiO2gate oxide

(good insulator, ox= 3.9)

polysilicongate

n+ n+

p-type body

+

Vgd

gate

+ +

source

-

Vgs-

drain

Vds

channel-

Vg

Vs

Vd

Cg


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Charge is carried by e-

Electrons are propelled by the lateral electric fieldbetween source and drainE = Vds/L

Carrier velocity v proportional to lateral E-field

v = .E called (electron) mobility(~ 500-600 cm2/V.s in heavily doped channel)

Time for carrier to cross channel:= L / v

Carrier Velocity

= L2/(.Vds)

n+ n+

p-type body

+

Vgd

gate

+ +

source

-

Vgs

-drain

Vds

channel-

Vg

Vs

Vd

Cg

v


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Now we know

How much charge Qchannelis in the channel How much time each carrier takes to cross

Ids= Qchannel /

= (Cox.W.L) . (Vgs Vt Vds/2) / (L2/(.Vds))

= . Cox.(W/L). (Vgs Vt Vds/2). Vds

= . (Vgs Vt Vds/2). Vds

nMOS Linear I/V

n+ n+

p-type body

+

Vgd

gate+ +

source

-

Vgs

-drain

Vds

channel-

Vg

Vs

Vd

Cg

v

where= . Cox.(W/L)


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nMOS IV Linear Region

12

For small , increases linearly behaves as a resistor As increases, charge in channel decreases

as a result: decreases

What happens when reaches it maximum ?

=. 2

.

()

()

=2

= 1.5

=1


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Suppose we increase Vdsuntil Vds= Vgs- Vt

Then Vgd= Vgs Vds= Vt The channel pinches off near drain We call this value of Vdsthe saturation voltage:

Vdsat= Vgs Vt At the point of saturation:

Idsat= . (Vgs Vt Vdsat/2). Vdsat= (/2). (Vgs- Vt )2

nMOS Saturation

n+ n+

p-type body

+

Vgd

gate

+ +

source

-

Vgs

-drain

Vds

channel-

Vg

Vs

Vd

Cg


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What happens if Vds> Vdsat

Pinch off extends from the drain towards the source Now, length of inverted channel is L = L.(Vdsat/Vds) Gate to channel capacitance is now

C = Cox.W.L = Cox.W.L.(Vdsat/Vds) Average voltage across capacitor is (Vgs-Vt)/2 = Vdsat/2

So Qchannel= Cox.W.L.(Vdsat)2/(2.Vds)

nMOS Saturation Channel Charge

n+ n+

p-type body

+

Vgd

gate

+ +

source

-

Vgs

-drain

Vds

channel-

Vg

Vs

Vd

Cg

L


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As before:Ids= Qchannel /

= (Cox.W.L.(Vdsat)2/(2.Vds)) ((.Vds)/L2)= (. Cox.(W/L)/2) . (Vdsat)2

= (/2). (Vgs- Vt )2

Note that Ids= Idsatand is now independent of Vds MOS transistor in saturation behaves like a constant current

source (with respect to Vds)

Square law dependence on Vgs

nMOS Saturation I/V

n+ n+

p-type body

+

Vgd

gate+ +

source

-

Vgs

-drain

Vds

channel-

Vg

Vs

Vd

Cg


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nMOS IV Linear Region

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For > = , channel saturates

Transistor behaves as a constant current source Idsindependent of Vds

= ( 2) .

()

()

=2

= 1.5

=1


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Shockley first-order model:

also known as ideal, long-channel model

nMOS I/V Summary

( )2

cutoff

linear

saturatio

0

2

2n

gs t

dsds gs t ds ds dsat

gs t ds dsat

V VV

I V V V V V

V V V V


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0 1 2 3 4 5

0

0.5

1

1.5

2

2.5

Vds

Ids

(mA)

Vgs

= 5

Vgs

= 4

Vgs

= 3

Vgs

= 2

Vgs

= 1 Vgs=1

Vgs=2

Vgs=3

Vgs=4

Vgs=5

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tox= 100 = 350 cm2/V.s Vt= 0.7 V

Use W/L = 4/2

Example: 0.6m process

( )14

2

8

3.9 8.85 10350 120 /

100 10ox

W W WC A V

L L L

= = =


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tox= 10.5 = 80 cm2/V.s Vt= 0.3 V

Use W/L = 4/2

Example: 65 nm process

= 262 . (W/L) A/V2


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Shockley first-order model:

also known as ideal, long-channel model

pMOS I/V Summary

( )2

cutoff

linear

saturatio

0

2

2

n

gs t

dsds gs t ds ds dsat

gs t ds dsat

V V

VI V V V V V

V V V V

< =

2

2

>

>


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All dopings and voltages are inverted for pMOS

Source is the more positive terminal Mobility pis determined by holes

Typically 2-3x lower than that of electrons n 120 cm2/V.s in 0.6 m process

Thus pMOS must be wider toprovide same current

In this class: assume n/ p= 2

pMOS I/V

-5 -4 -3 -2 -1 0-0.8

-0.6

-0.4

-0.2

0

Ids

(mA)

Vgs

= -5

Vgs

= -4

Vgs

= -3

Vgs = -2

Vgs

= -1

Vds

65nmpMOS


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Input to CMOS gate presents effectively infinite input

resistance The dominant load in CMOS circuits is capacitance Capacitance exists wherever there are two conductors

separated by a thin insulator

Gate to channel capacitor is very important Creates channel charge necessary for operation

Source and drain have capacitance to body Parasitic capacitance across reverse-biased diodes

Depletion region (insulator) separates N & P type conductors Called diffusion capacitance because it is associated with

source/drain diffusion

Capacitance


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Gate is top plate of capacitor

Assume bottom plate is source In cut-off, bottom plate is actually the body In linear mode, bottom plate is channel which is connected to

source and drain In saturation, bottom plate is channel connected to source

Cgs= ox.W.L/tox= Cox.W.L = Cpermicron.W Cpermicronis typically about 1-2 fF/m of width

Gate Capacitance

n+ n+

p-type body

W

L

tox

SiO2gate oxide

(good insulator, ox

= 3.90)

polysilicongate


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Csb, Cdb

Diffusion region isresistive and capacitive(to body)

Capacitance depends onarea and perimeter

Use small as possiblediffusion nodes

Comparable to Cgforcontacted diffusion

Use Cg/2 for merged Varies with process

Diffusion Capacitance

Isolated

Diffusion Gg

Cnode= 2.Cg

Shared

Diffusion Gg

Cnode= Cg

MergedDiffusion Gg/2

Cnode= Cg/2


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We have assumed source is grounded or at least close to ground, pulling drain down

What if source >> 0? e.g. nMOS pass transistor passing VDD

Vg= VDD If V

s> V

DD-V

t, V

gs< V

t Hence transistor would turn itself off

nMOS pass transistors pull no higher than VDD-Vtn Produces a degraded 1 Approach degraded value slowly (low Ids)

pMOS pass transistors pull no lower than |Vtp| Transmission gates are needed to pass both good 0 and good 1

Pass Transistors

VDDV

DD


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Degraded Time Constant

VDD

VDD

C Ids((VDDVt) - Vs)2

Ids

pull-up deviceis in saturation:

VDD

C IdsVs

Ids

pull-down device isin linear (mostly):

VDD

GND

VDD - Vt

t/

Pull-up time constant (to90% final value) can be 6xpull-down time constant!


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Cascaded Pass Transistors

VDD

VDD

VDD- Vtn

| Vtp |

VDD

VDD VDD VDD

VDD- Vtn VDD- Vtn VDD- Vtn

VDD

VDD

VDD- Vtn

VDD 2.Vtn


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Digital circuits are merely analog circuits used over aconstrained portion of their range

Derive DC transfer function for static CMOS inverter When Vin= 0 Vout = VDD When Vin = VDD Vout= 0

In between, Voutdepends ontransistor size and current

By KCL, must settle such thatIdsn= | Idsp |

We could solve equations, but Graphical solution gives more insight

DC Response: Inverter

Idsn

Idsp

Vout

VDD

Vin


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Current (Idsn, Idsp) depends on region of transistor behavior

For what Vinand Voutare nMOS and pMOS in

Cutoff?

Linear?

Saturation?

Transistor Operation

Idsn

Idsp

Vout

VDD

Vin


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Inverter: nMOS Operation

Cutoff Linear Saturated

Vgsn Vgsn

Vdsn

Vgsn

Vdsn

Idsn

Idsp Vout

VDD

Vin

< Vtn > Vtn > Vtn

< Vgsn - Vtn > Vgsn - Vtn

Vgsn= VinVdsn= Vout

Vin< Vtn Vin> Vtn Vin> Vtn

Vout< Vin - Vtn Vout> Vin - Vtn


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Inverter: pMOS Operation

Cutoff Linear Saturated

Vgsp> VtpVin> VDD+ Vtp

Vgsp< VtpVin< VDD+ Vtp

Vdsp> Vgsp Vtp

Vout> Vin- Vtp

Vgsp< VtpVin< VDD+ Vtp

Vdsp< Vgsp Vtp

Vout< Vin- Vtp

Idsn

Idsp Vout

VDD

Vin

Vgsp= Vin- VDD

Vdsp= Vout- VDD

(remember: Vdspand Vtp< 0)


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Mobility of holes is 2-3x less than mobility of electrons

Usually make pMOS 2x wider than nMOS so that

I-V Characteristics

Idsn

Idsp

VDD

VDD

Vdsn

VdspVgsn0Vgsn1Vgsn2Vgsn3

Vgsn4

Vgsn5

Vgsp0Vgsp1V

gsp2Vgsp3

Vgsp4

Vgsp5


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Replot I-V as function of Vout & Vin

Idsn

IdspV

out

VDD

Vin

Voutis where Idn= -Idp

VinC

Idsn,

VoutVDD

Vin5

Vin4

Vin3

Vin2Vin1Vin0

VinC

Vin5Vin4Vin3

Vin2

Vin1

Vin0

|Idsp

|


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Load Line Analysis

Idsn

Idsp

Vout

VDD

Vin

Vin= 0

Vin0

Vin0

Idsn,|Idsp|

VoutVDD


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Load Line Analysis

Idsn

Idsp

Vout

VDD

Vin

Vin= 0.2V

DD

Vin1

Vin1Idsn,|Idsp|

VoutVDD


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Load Line Analysis

Idsn

Idsp

Vout

VDD

Vin

Vin= 0.4V

DD

Vin2

Vin2

Idsn,|Idsp|

VoutVDD

L d Li A l i


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Load Line Analysis

Idsn

Idsp

Vout

VDD

Vin

Vin= 0.5V

DD

VinCVinC

Idsn,|Idsp|

VoutVDD

L d Li A l i


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Load Line Analysis

Idsn

Idsp

Vout

VDD

Vin

Vin= 0.6V

DD

Vin3

Vin3

Idsn,|Idsp|

VoutVDD

L d Li A l i


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Load Line Analysis

Idsn

Idsp

Vout

VDD

Vin

Vin= 0.8V

DD

Vin4

Vin4

Idsn,|Idsp|

VoutVDD

L d Li A l i


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Load Line Analysis

Idsn

Idsp Vout

VDD

Vin

Vin

= VDD

Vin5

Vin5

Idsn,|Idsp|

VoutVDD

L d Li A l i


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Load Line Analysis

Idsn

IdspV

out

VDD

Vin

VinCVinC

Idsn,|Idsp|

VoutVDD

Vin5

Vin5

Vin4

Vin4

Vin3

Vin3 Vin2

Vin2

Vin1

Vin1

Vin0

Vin0

DC T f C


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DC Transfer Curve

CV

out

0

Vin

VDD

VDD

A B

DE

Vtn

VDD

/2 VDD

+Vtp

Vin0

Vin1

Vin2

Vin3

Vin4 Vin5

Trans-scribe points onto Vin vs. Voutplot

S l C t


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Supply Current

IDD= Idsn= -Idsp

Zero current when in normal logic range

Transient current pulse drawn from VDDsupply on each

switching event

IDD

Vin VDD0

Operating Regions


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Operating Regions

CV

out

0

Vin

VDD

VDD

A B

DE

Vtn

VDD

/2 VDD

+Vtp

Vin0 Vin1V

in2

Vin3

Vin4 V

in5

Re-visit operating regions

Region nMOS pMOS

AB

C

D

E

Cutoff

Saturation

Saturation

Linear

Linear Cutoff

Saturation

Saturation

LinearLinear

Vout

VDD

Vin

Simulated 65nm DC Characteristic


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Simulated 65nm DC Characteristic

Beta Ratio


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If p/ n1, switching point will move from VDD/2

Calledskewed

gate Other gates: collapse into equivalent inverter

Beta Ratio

Restoring Logic


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Restoring Logic

Reason that we can build digital circuits with millionsof gates and always get same answer is:

Most CMOS logic gates are restoring output logic level is better than input logic level

47

input 0 input 1

output 1

output 0

Noise Margins


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How much noise can a gate input see before it does notrecognize the input?

Noise Margins

Indeterminate

Region

NML

NMH

Input CharacteristicsOutput Characteristics

VOH

VDD

VOL

GND

VIH

VIL

Logical High

Input Range

Logical Low

Input Range

Logical High

Output Range

Logical Low

Output Range

Nominal Logic Levels


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To maximize noise margins, select worst case logic levels at unity gain point of DC transfer characteristic

Nominal Logic Levels

Vout

Vin

VDD

VDD0

Vout

VDD

Vin

p/n > 1

VOH

VOL

VIL VIH

Unity Gain PointsSlope = -1

Example: MOS IV Formula


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Example: MOS IV Formula

Suppose we connect two identical nMOS devices in series between VDD

and GND and connect the gates of each to VDD:

Assuming VDD> VT,1.In which region is the upper transistor operating? Why?2.In which region is the lower transistor operating? Why?3.Derive an expression for the voltage Vxat the intermediate node

Documents

Lecture 7 - CpE 690 Introduction to VLSI Design