Lecture 6 - CpE 690 Introduction to VLSI Design

8/13/2019 Lecture 6 - CpE 690 Introduction to VLSI Design

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CpE 690: Digital System DesignFall 2013

Lecture 6

CMOS Fabrication and Layout

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Bryan Ackland

Department of Electrical and Computer Engineering

Stevens Institute of Technology

Hoboken, NJ 07030

Adapted from Lecture Notes, David Mahoney Harris CMOS VLSI Design


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CMOS transistors are fabricated on silicon wafer

mechanical support electrical ground plane

epitaxial layer: single crystal substrate (< 0.2 defects/cm2)

CMOS Wafers

Courtesy IBM


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Lithography process similar to printing press

glass masks and UV light

CMOS Fabrication

On each step, different materialsare deposited or etched accordingto one of these masks

As process line width shrinks: smaller transistors & wires

faster transistors

lower power transistors

Easiest to understand by viewing both top and cross-section of wafer in a simplified manufacturing process

Wikipedia


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Typically use p-type substrate for nMOS transistors

Requires n-well for body of pMOS transistors

CMOS Fabrication

n+

p substrate

p+

n well

A

YGND VDD

n+ p+

SiO2

n+ diffusion

p+ diffusion

polysilicon

metal1

nMOS transistor pMOS transistor

GND VDDY

A


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Substrate must be tied to GND and n-well to VDD

Metal to lightly-doped semiconductor forms poorconnection called Shottky Diode

Use heavily doped well & substrate contacts / taps / ties

Well and Substrate Taps

GND VDDY

A

n+

p substrate

p+

n well

A

Y

GND VDD

n+p+

substrate tapwell

tap

n+ p+


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Transistors and wires are defined by masks

Cross-section taken along dashed line

Inverter Layout

GND VDDY

A

GND VDD

Y

A

substrate tap well tap


A


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6 masks

n-well polysilicon

n+ diffusion

p+ diffusion

contact

metal

Detailed Mask Views

Metal

Polysilicon

Contact

n+ Diffusion

p+ Diffusion

n well

GND VDD

Y

A




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Start with blank wafer

Build inverter from the bottom up First step will be to form the n-well:

Cover wafer with protective layer of SiO2(oxide)

Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer

Strip off SiO2

Fabrication Steps

p substrate


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Grow SiO2on top of Si wafer

900 1200C with H2O or O2in oxidation furnace

Oxidation

p substrate

SiO2


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Strip off exposed photoresist with developer

organic solvent Leaves exposed SiO2in pattern determined by n-well

mask

How do we make 65 nm patterns with UV-light where

= 193 ?

Lithography

p substrate

SiO2

Photoresist


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Etch oxide with hydrofluoric acid (HF)

Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed

Etch

p substrate

SiO2

Photoresist


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Strip off remaining photoresist

Use mixture of acids called piranah etch mixture of H2SO4 and H2O2

Necessary so resist doesnt melt in next step

Strip Photoresist

p substrate

SiO2


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Strip off the remaining oxide using HF

Back to bare wafer with n-well

Subsequent masks involve similar series of steps

Strip Oxide

p substrate

n well


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Deposit very thin layer of gate oxide

40 (~13 atomic layers) at 180nm node 20 (6-7 atomic layers) at 130nm node

12 (4-5 atomic layers) at 65nm node

Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH4) - pyrophoric

Forms many small crystals called polysilicon

Heavily doped to be good conductor

Gate Oxide and Polysil icon

Thin gate oxide


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Polysilicon Structure

Crystallinesilicon

Polycrystallinesilicon

Amorphoussilicon


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Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon

p substrate

Thin gate oxide

Polysilicon

n well


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Grow another layer of SiO2

Will use oxide and masking to expose where n+ dopantsshould be diffused or implanted

N-diffusion forms nMOS source/drain, and n-wellcontact

N+ Diffusion / Implantation

p substraten well


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Pattern oxide and form n+ regions

Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates

because it doesnt melt during later processing

Self-Aligned Process

p substraten well

n+ Diffusion


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Historically dopants were diffused

Usually ion implantation today But these n+ regions are still called diffusion

N+ Diffusion (cont.)

n wellp substrate

n+n+ n+


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The dominant doping method

Excellent control of dose (ions/cm2)

Good control of implant depth with ionenergy (KeV to MeV)

Repairing crystal damage and dopantactivation requires annealing, which cancause dopant diffusion and loss of depthcontrol.

Ion Implantation


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Strip off oxide to complete patterning step

N+ Diffusion (cont.)

n wellp substrate

n+n+ n+


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Similar set of steps form p+ diffusion regions for pMOS

source and drain and substrate contact Boron atoms are implanted in the unmasked silicon

P+ Diffusion / Implant

p+ Diffusion

p substraten well

n+n+ n+p+p+p+


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Now we need to wire together the devices

Cover chip with thick field oxide Etch oxide where contact cuts are needed

Contacts

Contact


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A layer of tungsten is grown over surface

Etched away to leave only contact holes filled withtungsten

Tungsten conforms better (than Al) to geometry of smallholes

Tungsten Plugs

Tungsten

Thick

FieldOxide


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Suppose we want to connect our first layer metal (M1)to a higher metal routing layer (M2)

Grow another layer of SiO2as an insulating dielectric Etch VIA holes (VIA1) to connect M2 to M1

Fill with Tungsten

More Tungsten Plugs

ThickFieldOxide

Metal 1

MoreOxide

Tungsten VIA1


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Pattern and plasma etch second layer of metal (M2)

M2 connects to M1 through VIA1

If there is a third layer of metallization, M2 connects toM3 through VIA2 (not shown)

M2 cannot connect (directly) to poly or diffusion

Second Layer of Metallization M2

ThickFieldOxide

Metal 1

MoreOxide

Metal 2


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Contacts & Vias

Diffusion Poly Gate Poly Wire Metal1 Metal2

Diffusion contact Poly Gate Poly Wire contact

Metal1 contact contact VIA1

Metal2 VIA1

diffusionpoly gate

poly wire

metal 1

metal 2

silicon

SiO2


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Need at least 3-4 layers of metal to support densecustom (hand-drawn) layout.

Automatic place & route tools rely on multiple metallayers to create dense designs with good power & clockdistribution and minimum parasitics.

Modern processes have 5-10 layers of metal upper layers often Cu (rather than Al_) each layer requires viaand a metal pattern mask

Higher Metallization Layers

cross-section showing 11metallization layers

(Courtesy IBM)


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Mask to Layout

VDD

GND

A B C

Y

(layout)

(masks)


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Would like to make objects (transistors, wires etc.) as

small as possible to increase speed, decrease cost & power Object size and spacing is limited by precision of

photolithography & manufacturing process

Need Design Rules to constrain layout engineer ensure design is manufacturable

Process Limitations and Design Rules

layout on-chip wiring


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b d D i R l


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We can simplify design by adopting a conservative setof rules normalized to minimum feature sizef

Express rules in terms of = f/2 e.g. for 180nm process, = 90nm

For example MOSIS SCMOS rules:

Layout can be scaled to new process by simply

changing value of

based Design Rules

3

3

2

2

3

1

1.5

Si lif i d D i R l


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A simpler (more conservative) set to get you started:

Simplif ied Design Rules

Metal1 Metal2 N Diffusion P Diffusion Poly

4 4 4 4 4 4 4 4 32

Metal1-DiffusionContact

Metal1-PolyContact

Metal1-Metal2Via

32 2

2

Si lifi d D i R l ( )


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Creating NMOS devices:

This produces minimum size device: W = 4, L=2

Simplified Design Rules (cont.)

diffusion regionbecomes S/D

regions

poly gate crossesdiffusion region,separating S/D

4

2

S/D S/D

G

contacts connect

M1 to gate andS/D regions

4 44

2

4

Si lifi d D i R l ( t )


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PMOS device created in same way:

Simplified Design Rules (cont.)

6

6

4

2

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n-well

PMOS device often wider tomatch drive strength of

NMOS: (W = 8, L = 2)

PMOS device surrounded bynwell (at least 6 )

NMOS device must beseparated from nwell by atleast 6

G t L t


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Layout can be very time consuming

can waste a lot of time trying to squeeze last micron out Layout more efficient if we design gates to fit togethernicely

Build a library of standard cells

Gate Layout

GND VDD

Y

A



VDD

GND

YA

St d d C ll D i M th d l


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VDD and GND run horizontally & shouldabut standard height cell

nMOS horizontally at bottom and pMOS attop

Polysilicon runs vertically to connecttransistor gates

All gates include well and substratecontacts

Adjacent gates should satisfy design rules extend VDD and GND rails by 2 Layout can be built on 8x 8grid with

metal1 wiring tracks between nMOS andpMOS devices.

Standard Cell Design Methodology

YA

VDD

GND

Wiring tracks


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A wiring track is the space required for a wire

4 width, 4 spacing from neighbor = 8 pitch Transistors also consume one wiring track

Wiring tracks

4 4 4

8

4

4

4

4

4

4

metal1

metal1

metal2

metal2

8

Well Spacing


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Wells must surround transistors by 6

Implies 12 between opposite transistor flavors Leaves room for one wire track

Well Spacing

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6

4

4

Building Gates: Transistors in Series


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Building Gates: Transistors in Series

GND

A B C YY

8

8

Transistors can be placed in series by simply

overlaying their common source/drain region

A

B

C

Y

Building Gates: Transistors in Parallel


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Building Gates: Transistors in Parallel

Transistors can be placed in parallelby using a

combination of source/drain overlap and metalinterconnect

GND

A B C YY

8

8

Y

A B C

Y


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Stick Diagrams


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Stick Diagrams

Stick diagrams help plan layout quickly

Need not be to scale As drawn in textbook (Weste & Harris)


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Example: O3AI


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Example: O3AI

Sketch a stick diagram for O3AI and estimate area.

Y = ( A + B + C) D


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XOR gate layout with M1


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XOR gate layout with M1

How to

complete the

wiring?

Paths are

blocked by

horizontal and

vertical M1


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Transistor Sizing


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Transistor Sizing

In most layouts, transistors are not all of same size pMOS has about drive of same size nMOS

series/parallel combinations lead to different drive strength

Transistor dimensions specified as Width / Length

Minimum size is 4 / 2, sometimes called 1 unit e.g. in f = 0.5 m process, this is 1.0 m wide, 0.5mlong

Impact of Sizing on Layout


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Impact of Sizing on Layout

Adding sized transistors complicatessimple 8x 8grid

Still useful for draft layout andapproximate area calculations

When estimating area, add (w-1).4in height to accommodate atransistor of width w.

Add extra contacts when possible Improved contact resistance

Improves yield

Many designers will use two-contacttransistor as minimum width device

VDD

GND

YA

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Lecture 6 - CpE 690 Introduction to VLSI Design