Lecture #20 Page 1 ECE 4110– Digital Logic Design Lecture #21 Agenda 1.MSI: Carry Look-Ahead Adders Announcements 1.N/A

Lecture #20Page 1

ECE 4110– Digital Logic Design

Lecture #21

• Agenda

1. MSI: Carry Look-Ahead Adders

• Announcements

1. N/A.

Lecture #20Page 2

Carry Look Ahead Adders

• Addition – Carry Look Ahead Adder

- We've seen a Ripple Carry Adder topology (RCA)

- this is good for simplicity and design-reuse

- however, the delay increases linearly with the number of bits

tRCA = n·tFull-Adder

- different topologies within the full-adder to reduce delay (Δt) will have a n·Δt effect

- the linear increase in delay comes from waiting for the Carry to Ripple through

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- to avoid the ripple, we can build a Carry Look-Ahead Adder (CLA)

- this circuit calculates the carry for all Full-Adders at the same time

- we define the following intermediate stages of a CLA:

Generate "g", an adder (i) generates a carry out (C i+1)under input conditions Ai and Bi independent of Ai-1, Bi-1, or Carry In (Ci)

Ai Bi Ci+1

0 0 0

0 1 0 we can say that: gi = Ai·Bi

1 0 0

1 1 1 remember, g does NOT consider carry in (Ci)

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Propagate "p", an adder (i) will propagate (or pass through) a carry in (C i) depending on input conditions Ai and Bi,:

Ci Ai Bi Ci+1

0 0 0 0

0 0 1 0 pi is defined when there is a carry in,

0 1 0 0 so we ignore the row entries where Ci=0

0 1 1 1

1 0 0 0 if we only look at the Ci=1 rows

1 0 1 1 we can say that:

1 1 0 1 pi = (Ai+Bi)·Ci

1 1 1 1

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- said another way, Adder(i) will "Generate" a Carry Out (Ci+1) if:

gi = Ai·Bi

and it will "Propagate" a Carry In (Ci) when pi = (Ai+Bi)·Ci

- a full expression for the Carry Out (Ci+1) in terms of p and g is given by:

Ci+1 = gi+pi·Ci

- this is good, but we still generate Carry's dependant on previous stages (i-1) of the iterative circuit

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- We can eliminate this dependence by recursively expanding each Carry Equation

ex) 4 bit Carry Look Ahead Logic

C1 = g0+p0·C0 (2-Level Product-of-Sums) C2 = g1+p1·C1

C2 = g1+p1·(g0+p0·C0) C2 = g1+p1·g0+p1·p0·C0 (2-Level Product-of-Sums)

C3 = g2+p2·C2

C3 = g2+p2·(g1+p1·g0+p1·p0·C0) C3 = g2+p2·g1+p2·p1·g0+p2·p1·p0·C0 (2-Level Product-of-Sums)

C4 = g3+p3·C3

C4 = g3+p3·(g2+p2·g1+p2·p1·g0+p2·p1·p0·C0)

C4 = g3+p3·g2+p3·p2·g1+p3·p2·p1·g0+p3·p2·p1·p0·C0 (2-Level Product-of-Sums)

- this gives us logic expressions that can generate a next stage carry based upon ONLY the inputs to the adder and the original carry in (C0)

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- the Carry Look Ahead logic has 3 levels

1) g and p logic 2) product terms in the Ci equations 3) sum terms in the Ci equations

- the Sum bits require 2 levels of Logic

1) AiBiCi NOTE: A Full Adder made up of 2 Half Adders has 3 levels. But the 3rd level is used in the creation of the Carry Out bit. Since we do not use it in a CLA, we can ignore that level.

- So a CLA will have a total of 5 levels of Logic

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- the 5 levels of logic are fixed no matter how many bits the adder is (really?)

- In reality, the most significant Carry equation will have i+1 inputs into its largest sum/product term

- this means that Fan-In becomes a problem since real gates tend to not have more than 4-6 inputs

- When the number of inputs gets larger than the Fan-In, the logic needs to be broken into another level

ex) A+B+C+D+E = (A+B+C+D)+E

- In the worst case, the logic Fan-In would be 2. Even in this case, the delay associated with the Carry Look Ahead logic would be proportional to log2(n)

- Area and Power are also concerns with CLA's. Typically CLA's are used in computationally intense applications where performance outweighs Power and Area.

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• Adders in VHDL

- (+) and (-) are not defined for STD_LOGIC_VECTOR

- The Package STD_LOGIC_ARITH gives two data types:

UNSIGNED (3 downto 0) := "1111"; -- +15 SIGNED (3 downto 0) := "1111"; -- -1

- these are still resolved types (STD_LOGIC), but the equality and arithmetic operations are slightly different depending on whether you are using Signed vs. Unsigned

• Considerations

- when adding signed and unsigned numbers, the type of the result will dictate how the operands are handled/converted

- if assigning to an n-bit, SIGNED result, an n-1 UNSIGNED operand will automatically be converted to signed by extending its vector length by 1 and filling it with a sign bit (0)

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• Adders in VHDL

ex) A,B : in UNSIGNED (7 downto 0); C : in SIGNED (7 downto 0); D : in STD_LOGIC_VECTOR (7 downto 0);

S : out UNSIGNED (8 downto 0); T : out SIGNED (8 downto 0); U : out SIGNED (7 downto 0);

S(7 downto 0) <= A + B; -- 8-bit UNSIGNED addition, not considering Carry

S <= ('0' & A) + ('0' & B); -- manually increasing size of A and B to include Carry. Carry will be kept in S(9) T <= A + C; -- T is SIGNED, so A's UNSIGNED vector size is increased by 1 and filled with '0' as a sign bit U <= C + SIGNED(D); -- D is converted (considered) to SIGNED, not increased in size U <= C + UNSIGNED(D); -- D is converted (considered) to UNSIGNED, not increased in size

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Lecture #20 Page 1 ECE 4110– Digital Logic Design Lecture #21 Agenda 1.MSI: Carry Look-Ahead Adders Announcements 1.N/A