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Lecture (01)Transistor Bias Circuit
By:
Dr. Ahmed ElShafee
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II١
Collector Characteristic Curves
٢
BC
E
BJT Characteristic
BJT modes of operation
• Conditions in Cutoff
• Conditions in Saturation
٣
DC Bias
• Following Figure shows the effects of proper and improper dc biasing of an inverting amplifier.
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٤
which means that it isout of phase with the input.
The output signal swings equally above and below the dc bias
level of the output, VDC(out).
• If an amplifier is not biased with correct dc voltages on the input and output, it can go into saturation or cutoff when an input signal is applied
• Improper biasing can cause distortion in the output signal
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٥
Figure illustrates limiting of the positive portion of the output
voltage as a result of a Q-point (dc operating point) being too close to cutoff
•
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٦
limiting of the negative portion of the output voltage as a result of a dc operatingpoint being too close to saturation.
• The transistor in Figure is biased with VCC and VBB to obtain certain values of IB, IC, and VCE.
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٧
• assign three values to IB and observe what happens to IC and VCE.
• VBB is adjusted to produce an IB of 200 uA
• Since IC = β IB• the collector current is 20 mA,
• This Q‐point is shown on the graph of Figure
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٨
• VBB is increased to produce an IB of 300 uA and an IC of 30 mA.
• The Q‐point for this condition is indicated by Q2 on the graph
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٩
• VBB is increased to give an IB 400 uA of and an IC of 40 mA.
• Q3 is the corresponding Q‐point on the graph.
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II١٠
DC Load Line
• The dc operation can be described graphically using a dc load line.
• This is a straight line drawn on the characteristic curves from the saturation value where IC =IC(sat)on the y‐axis to the cutoff value where VCE = VCC on of a transistor circuit on the x‐axis,
• The load line is determined by the external circuit (VCC and RC), not the transistor itself,
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II١١
• This is the equation of a straight line with a slope of ‐1/RC, an x intercept of VCE = VCC,
• and a y intercept of VCC/RC, which is IC(sat).
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II١٢
• The point at which the load line intersects a characteristic curve represents the Q‐point for that particular value of IB.
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II١٣
Linear Operation
• The region along the load line including all points between saturation and cutoff is generally known as the linear region of the transistor’s operation.
• As long as the transistor is operated in this region, the output voltage is ideally a linear reproduction of the input.
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II١٤
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II١٥
• AC quantities are indicated by lowercase italic subscripts
• Assume a sinusoidal voltage, Vin, is superimposed on VBB,
• Ib to vary sinusoidally 100uA above and below its Q‐point value of 300uA
• causes the collector current to vary 10 mA above and below its Q‐point value of 30 mA
• Vce voltage varies 2.2 V above and below its Q‐point value of 3.4 V
•
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II١٦
Waveform Distortion
• under certain input signal conditions the location of the Q‐point on the load line can cause one peak of the Vce waveform to be limited or clipped,
• When the positive peak is limited, the transistor is being driven into cutoff.
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II١٧
• input signal is too large for the Q‐point location and is driving the transistor into cutoff or saturation during a portion of the input cycle.
• When the negative peak is limited, the transistor is being driven into saturation
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II١٨
• When both peaks are limited, the transistor is being driven into both saturation and cutoff by an excessively large input signal.
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II١٩
Example 1
•
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٢٠
Solution 1
•
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٢١
•
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٢٢
• that before saturation is reached, IC can increase an amount ideally equal to
• IC can decrease by 39.6 mA before cutoff (IC = 0) is reached
• the limiting excursion is 21 mA because the Q‐point is closer to saturation than to cutoff
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٢٣
• The 21 mA is the maximum peak variation of the collector current.
• Actually, it would be slightly less in practice because VCE(sat) is not quite zero.
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٢٤
• Determine the maximum peak variation of the Ib base current as follows
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٢٥
Voltage divider bias
• biasing a transistor for linear operation using a single source resistive voltage divider.
• A more practical bias method is to use VCC as the single bias source,
• A dc bias voltage at the base of the transistor can be developed by a resistive voltage divider that consists of R1 and R2,
• voltage‐divider bias circuits are designed so that the base current IB is much smaller than the current (I2) through R2
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٢٦
• Calculate the voltage on the base using the unloaded voltage‐divider rule
• you can find the voltages and currents in the circuit
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٢٧
Example 02
•
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٢٨
Solution 2
•
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٢٩
Loading Effects of Voltage‐Divider Bias; DC Input Resistance at the Transistor Base
• The dc input resistance of the transistor is proportional to βDC when operating in its linear region, the emitter current
IE = IB x βDC• When the emitter resistor is viewed from
the base circuit, the resistor appears to be larger than its actual value because of the dc current gain in the transistor.
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٣٠
• estimate the loading effect by comparing RIN(BASE) to the resistor R2 in the voltage divider.
• As long as RIN(BASE) is at least ten times larger than R2, the loading effect will be 10% or less and the voltage divider is stiff.
• If RIN(BASE) is less than ten times R2, it should be combined in parallel with R2.
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٣١
Example 3
•
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٣٢
Solution 3
•
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٣٣
Thevenin’s Theorem Applied to Voltage‐Divider Bias• Let’s get an equivalent base‐emitter circuit for the circuit
using Thevenin’s theorem.
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٣٤
• circuit can be redrawn
• Calculate VTH, RTH
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٣٥
• Applying Kirchhoff’s voltage
• Ohm’s law
• Substituting IE / β = IB
• solving for IE,
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٣٦
• If RTH/βDC is small compared to RE, the result is the same as for an unloaded voltage divider
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٣٧
Voltage‐Divider Biased PNP Transistor•
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٣٨
•
• Thevenin’s theorem,
• The base current is
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٣٩
•
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٤٠
• The analysis procedure is the same as for an npn transistor circuit using Thevenin’stheorem and Kirchhoff’s voltage law,
• Thevenin’s theorem,
• The base current is
٤١
•
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٤٢
Example 04
•
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٤٣
Solution 4
• Apply Thevenin’s theorem.
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٤٤
• Use Equation
• The negative sign on IE indicates that the assumed current direction in the Kirchhoff’s analysis is opposite from the actual current direction
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٤٥
•
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٤٦
Example 5
•
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٤٧
Solution 5
•
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٤٨
•
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٤٩
Thanks,..
See you next week (ISA),…
Dr. Ahmed ElShafee, ACU : Fall 2016, Electronic Circuits II٥٠