Lecture 01: Introduction - UCSD VLSI CAD Laboratoryvlsicad.ucsd.edu/courses/cse241a/web/lec_notes/Lec1_final.pdf · ... VLSI Integrated Circuits and Systems Design) Winter 2003 Lecture

CSE241 L1 Introduction.1 Kahng & Cichy, UCSD ©2003

CSE241A: Introduction to Computing Circuitry

(ECE260B: VLSI Integrated Circuits and Systems Design)

Winter 2003

Lecture 01: Introduction


Outline

§ Introduction

§ Motivation/Trends

§ Transistor

§ Basic logic blocks

§ Performance

§ Power


Logistics

§ Instructor: Andrew B. Kahng (UCSD CSE & ECE)l [email protected]

§ TA: Benjamin Cichy (on UCSD CSE staff)l [email protected]

§ Class: Tu, Th 9:30am-10:50am, Center 217B

§ Recitation: Wed 2:00-3:00pm

§ Lab: Wed 3:30-5:00pm EBU1 3327

§ Text: M. J. S. Smith, Application-Specific Integrated Circuits, Addison-Wesley, 1997. Chapters 1-3, 11-17

§Website: vlsicad.ucsd.edu/courses/cse241a


Class Info

§ CSE241A and ECE260B crosslisted

§ Prerequisitesl ECE 260B: ECE 260Al CSE 241A: CSE 240

§ ~6 labs, 1 project (through quarter), ~19 lecturesl Meeting #5 = guest lecture (synthesis)l Meeting #8 = midterm

§ Gradingl 40% project, 25% midterm, 20% homework, 15% lab

§ Content: CMOS devices and manufacturing technology. CMOS logic gates and their layout. Propagation delay, noise margins, and power dissipation. Combinational (e.g., arithmetic) and sequential circuit design. Memory design. Overall ASIC implementation flow.


Other Notes

§ Check website frequently for new slides or other updates

§ This course will be “under construction” throughout the quarter; expect small resets as we go

§ My background: CS, and VLSI CAD (physical design, back-end implementation methodology, performance analysis, design-manufacturing interface)

§ Homeworkl Due, neatly written or printed, at the end of class one week after the

question appears in lecture slidesl No extensions unless a doctor’s note is provided

§ Academic integrityl All work must be your own unless collaboration is specifically permittedl All sources must be specifically and completely acknowledgedl Violations will be reported per university regulations


Class Objectives

§ Learn about ASIC implementation flow: VerilogàGDSIIl Design and implementation of CMOS digital circuits, and

optimization with respect to different constraints: cost, area, speed, power dissipation, and reliability

§ High-level overview of each phase of the design flow

§ Introduce industry-standard design tools

l Logic synthesis: Synopsys Design Compiler

l Place and route: Cadence Silicon Ensemble (SE-PKS)

l Physical verification: Cadence Assura / Diva

§ Prepare for future design experiences

§ Synthesize a modern processor (soft core) into GDSII


Other Objectives§ Understand basic building blocks of VLSI

l Transistors and wiresl Logic gates and other (memory, datapath) blocksl Layout

§ Conceptually model and build systeml State-machine design (RTL)l Verilog modelingl Synthesis, place and route

§ Understand constraints and tradeoffsl Timing (gates and interconnects)l Clocking methodologyl System integration issues (power/ground routing, noise, package, cost)

§ Note: You should have taken logic design (Boolean logic, K-maps, state machines), and some ECE 165 (UG VLSI) background as welll We will review or develop quickly: basic circuit theory (MOS device

parasitics, performance); Verilog HDL; EDA tools (layout, schematic capture, simulation/synthesis); logic design (minimization, FSMs)


Outline

§ Introduction


§ Transistor


§ Performance

§ Power


Cost and Integration Drivers

§ Moore’s Law is about costl How many distinct statements

(versions) of Moore’s Law can you find?

§ Increased integration, decreased cost à more possibilities for semiconductor-based products

§ Pentium 4 die shot:

§ Estimate (a) the number of SRAM bitcells per square millimeter, and (b) the number of logic gates per square millimeter, in 130nm CMOS.

2.2cm

Slide courtesy of Mary Jane Irwin, PSU


MOS Transistor Scaling (1974 to present)

S=0.7[0.5x per 2 nodes]

Pitch Gate

Source: 2001 ITRS - Exec. Summary, ORTC Figure

§ Homework Q1: (a) What is the website of the International Technology Roadmap for Semiconductors (ITRS)? (b) How many chapters are in the ITRS? (c) How is transistor performance (speed) measured in the ITRS, and what is the predicted speed of a high-performance transistor in the 65nm node?


Half Pitch (= Pitch/2) Definition

(TypicalMPU/ASIC)

(TypicalDRAM)

Poly Pitch

Metal Pitch

Source: 2001 ITRS - Exec. Summary, ORTC Figure


Sense of Scale (Scaling)

§ What fits on a VLSI Chip today?

§ State of the art logic chipl 20mm on a side (400mm2)l 0.13µm drawn gate lengthl 0.5µm wire pitchl 8-level metal

§ For comparisonl 32b RISC processor

- 8K λ x 16Kλ

l SRAM- about 32λ x 32λ per bit- 8K x 16K is 128Kb, 16KB

l DRAM- 8λ x 16λ per bit- 8K x16K is 1Mb, 128KB

20mm(40,000 wire pitches)

320,000 λ

0.13µm (2 λ)

32b RISCProcessor

64b FPProcessor

0.5µm(8 λ)

Slide courtesy of Ken Yang, UCLA


Design Levels

§ Specificationl what the system (or

component) is supposed to do

§ Architecturel high-level design of

component- state defined

- logic partitioned into major blocks

§ Logicl gates, flip-flops, and the

connections between them

§ Circuitl transistor circuits to realize

logic elements

§ Devicel behavior of individual circuit

elements

§ Layoutl geometry used to define and

connect circuit elements

§ Processl steps used to define circuit

elements

Can describe design at many different levels of abstraction



Abstractions and Disciplines

§ Digital abstractionl signals are 1 or 0

§ Switch abstractionl MOSFETs as simple switches

§ Gate abstractionl Unidirectional elementsl Separable timing

§ Synchronous abstractionl Race free logicl Function does not depend on

timing

§ Constrain the design space to simplify the design processl Balance between design

complexity and performancel E.g., standard-cell methodology

§ Orthogonalize concernsl Architecture and implementationl Logic and timingl Logic and embedding

§ Partition the problem (hierarchy)l Module is a box with pinsl Apply recursively



Design Procedure and Tools

§ Conceptl divider

§ Architecturel subtract/compare

§ Logical Implementationl ab+bc+acl xor

§ Circuit Implementationl transistors

§ Physical layout + Verifyl mask layers (rectangles)

§ C-modeling

§ Behavior modelingl Verilog or VHDL

§ Logic synthesisl Design Compiler (Synopsys)l Verification of synthesis

- Static timing analysis

§ Place and routel Silicon Ensemble (Cadence)l Verification of layout

- Dynamic timing analysis


§ Exercise: (a) List the top 6 “Electronic Design Automation” (EDA) companies according to annual revenue. (b) Estimate the percentage of EDA industry revenue garnered by the remaining (how many?) companies in the industry, and explain how you reached this estimate.


Bigger Picture of Design Flow

Schematic Entry Cell

CharacterizationLayout Entry

Standard Cell Library

3-D RLC Modeling

Tool

Wire ModelDevice model

Layout rules

ρ,σ, µLayers

Synthesis Library (Timing/Power/Area)

C-Model Verilog Behavioral

Model Verilog Structural

RTL

Structural Model

Parasitic Extraction LibraryPlace & Route Library (Ports)

Floorplan

Global Layout

Block Layout

Floorplan

P & R

Functional

DRC/ERC/LVS

Static/Dynamic Timing w/extractFunctional

Static TimingPower/Area Scan/Testability

Synthesis P & R

Clock Routing/Analysis



Outline

§ Introduction


§ Transistors


§ Performance

§ Power


NMOS Transistors

§ Raising the gate voltage attracts electrons to form a thin n-region under the gate, called the channel, through which current flows between the two n+ regions

§ If the n-channel is not present, the two n+ regions are separated by back-to-back diodes, which blocks current flow

§ The gate voltage at which a channel forms depends on the value of VGS = VG-VSl The gate must first repel away the positive charge before building up the

negative channell For this to happen requires VGS > VT, where VT is the threshold voltagel (When VGS < VT , subthreshold current is still flowing)

n+ n+

poly

pchannel



MOSFET as Switch

§ (NMOS) three-terminal devicel Source, Drain

- two ends of conductive path- VDS (voltage of drain with respect to

source) must be positive for current to flow

l Gate- controls conductive path

l Operation- conducts (“on”) when gate is high (1)- open circuit (“off”) when gate is low (0)

l Passes 0’s well, but not 1’s – Why?

source

gate

drain

For PMOS, everything is reversed: source terminal must have higher voltage, and the

transistor is on when the gate is much lower than the source


Transistor Operation

§ Voltage on gate induces a charge in the channel

§ Voltage across source-drain creates a field that moves the charge (Source is the lower voltage for an nMOS)

§ IDS = Qper_length ∗ velcarrier

§ Vel = µ ∗ EDSl µ is electron mobility

§ COXTOT = Cox ∗ A = εoxA/tox

Qper_length = COXTOT/L(VGS-VT)

= COXTOT/L*VGT

Gate

Source Drain

EDS

Well/SubstrateL

W

•Slide courtesy of Ken Yang, UCLA


Resistive Region

§ At low VDS (and large VGS-VT), channel voltage is essentially constant and charge remains uniform across channel

§ Device acts as a resistor

§ EDS = VDS/L

§ IDS = KVGTVDS

§ Where K = µCoxW/L

QpL = WCOX(VGS-VT) = WCOXVGT

Gate

Source Drain



Linear/Triode Region

§ If we raise VDS so that the charge under the gate near the drain differs from that near the source.

§ Take the average Qper_ length

Gate

Source Drain

−=

2

2DS

DSGTDSV

VVKI

Ave(QpL) = ½(WCOX(VGS-VT) + WCOX(VGD-VT))

= WCOX(VGT-VDS/2)



Current-Source (Saturation) Region

§ At high VDS > VGT, channel voltage, and hence charge slopes across channel

§ Charge pinches off near drain

§ The drain voltage no longer affects channel

§ With the VGS fixed, the device acts as a current source.

Gate

Source Drain

2

2GT

DSKV

I =

V@pinchoff = VG-VT

VD > VG-VT



Transistor Summary

§ Three regions of operation:l Off (VGS<VT)l Triode/Linear (VGD>VT)l Saturated (VGS>VT and VGD<VT or VGD>VGS-VT)

§ The value of the current is proportional to the gate to source voltage minus threshold voltage, VGS-VT

§ Current inversely proportional to the oxide thickness

§ Current proportional to width (width of the diffusion), inversely proportional to length (width of the poly)

So

§ Resistance of transistor is proportional to length and inverselyproportional to width

−=

2

2DS

DSGTDS

VVVKI

2

2GT

DSKV

I =L

WCK oxµ=

TGSGT VVV −=



MOS Approximation

§ The transistor’s resistance is variable and depends on the gate voltage.

§ This approximation is ok for timing estimates, but not for analog circuits

Vds

ids

Vg = 1.0V

Vg = 1.5V

Vg = 2.0V

Vg = 2.5V



Complementary Transistors

§ PMOS transistors have negative threshold voltagel Devices turn on when gate is LOWER than source by more than

threshold voltagel Source is the diffusion terminal with the HIGHER voltagel Draw ‘bubble’ or ‘o’ on gate of PMOS device

§ Complementary device typesl NMOS connected when gate is high

- Passes 0, but high output is degraded

l PMOS connected when gate is low- Passes 1, but low output is degraded

a b

c

d e

f

c high à a connected to b f low à d connected to e

Vdd -Vth - weak

Gnd -strong

Vdd - strong

Vth - weak


Switch Networks

§ Since transistors can be modeled as switchesl Draw an abstract switch as

- Control (gate) terminal is on top

§ We can build switch networks between two non-control terminalsl Define the function of a switch network by the conditions on inputs

that will connect the two terminals of the network

l Structure of switch network sets its logic functions:- ‘OR’ functions are constructed by parallel switches- ‘AND’ function are constructed by series switches

§ VLSI chip = millions of these switch networks

A

X Y

A B

A

B

YX

X Y


Outline

§ Introduction


§ Transistors


§ Performance

§ Power


NOR Gate

§ F(NOR) = (A+B)’l Output is low when either A or B is high.

- NMOS’s form an OR network to VGND.

l Output is high when A and B are both low- PMOS’s form an AND network to VDD.

A

BNOR

Output



NAND Gate

§ NANDl Output is low when A and B are both highl Output is high when either A or B is low

A

B

NAND

Output



Static CMOS Logic Family

§ Can implement any function

§ To build a logic gate g(x1, …, xn) = f’(x1, …, xn) , need to build two switch networks:

§ Pull-down: α(x1, …, xn) = f(x1, …, xn)

§ Pull-up: β(x1’, …, xn’) = f’(x1, …, xn) l Note: PMOS inverts inputs

α

β

NMOS only, since only passes 0

PMOS only, since only passes 1

PMOS pull-up network

Connects the output to

VDD when f is FALSE

NMOS pull-down network

Connects the output to

VGND when f is TRUE



Duality

Pull-up and pull-down networks are duals of each other

§ Dual of a function:l Exchange ANDs and ORs

§ Example Dualsl A B ; A + Bl (A +B ) C ; (A B) + C

For switch networks l AND = series switchesl OR = parallel switches

§ So l Parallel pull-down, serial pull-up and vice versa



De Morgan’s Law

§ (a + b)’ = a’ b’

§ (a b)’ = a’ + b’

§ Complement of a function is obtained by replacing each variable / element with its complement, and exchanging the AND and OR operations

§ If element is not a single variable, then apply recursively to the expressions:l ((A+B) C)’ = (A + B)’ + C’ = (A’ B’) + C’l ((A B) + (C D))’ = (A B)’ (C D)’ = (A’ + B’) (C’ + D’)



Complex Gate Example

§ Function: And-Or-Invert (AOI): g=(AB+C)’

§ Pull-down implements fN = AB+C

§ Pull-up implements DUAL of fN

l fP = (A’+B’)C’ - inverted inputsl The network that you build is (A+B)C

and

or

invert



More Examples

§ 3 input function, g = a(b+c) + bcl For pull-down, f = (a’+b’c’)(b’+c’)l For pull-up, f’ = a’’(b’’+c’’)+b’’c’’

§ 5 input function, g = ab + (cde)’l For pull-down, f = (a’+b’)(cde)l For pull-up, f’ = a’’b’’ + (c’ + d’ + e’)

§ Depth of stacking is approximately the number of inputs à performance implications

c’ b’

c’

a’ b’

b’a’

c

d

e


§ Homework Q2: Draw the transistor schematic for (a) a 3-input XOR gate, and (b) g = a(cd + b) + bc’


Outline

§ Introduction


§ Transistors


§ Performance

§ Power


Circuit Performance Estimation

Deep Sub-micron (DSM) MOSFET models

Critical Path Timing AnalysisCritical Path Timing Analysis

Accurate interconnect delay and noise models

Reg

Reg Reg

Reg Reg

•Slide courtesy of Kevin Cao, Berkeley


Wire

ViaGlobal (up to 5)

Intermediate (up to 4)

Local (2)

PassivationDielectric

Etch Stop Layer

Dielectric Capping Layer

Copper Conductor with Barrier/Nucleation Layer

Pre Metal DielectricTungsten Contact Plug

Reverse Scaling of Global Interconnects

§ What are some implications?

•Slide courtesy of Chris Case, BOC Edwards


Interconnect Statistics

Local Interconnect

Global Interconnect



Acceleration of Gate Length Scaling


•Slide courtesy of Numerical Technologies, Inc.


Crosstalk From Capacitive Coupling

§ Glitches caused by capacitive coupling between wiresl An “aggressor” wire switchesl A “victim” wire is charged or discharged by the coupling

capacitance (cf. charge-sharing analysis)

§ An otherwise quiet victim may look like it has temporarily switched

§ This is bad if:l The victim is a clock or asynchronous resetl The victim is a signal whose value is being latched at that momentl What are some fixes?

Aggressor

Victim

•Slide courtesy of Paul Rodman, ReShape


Crosstalk: Timing Pull-In

§ A switching victim is aided (sped up) by coupled charge

§ This is bad if your path now violates hold time

§ Fixes include adding delay elements to your path

Aggressor

Victim



Crosstalk: Timing Push-Out

§ A switching victim is hindered (slowed down) by coupled charge

§ This is bad if your path now violates setup time

§ Fixes include spacing the wires, using strong drivers, …

Aggressor

Victim



Delay Uncertainty

§ Relatively greater coupling noise due to line dimension scaling

§ Tighter timing budgets to achieve fast circuit speed (“all paths critical”)

§ à Train wreck ?

§ Timing analysis can be guardbanded by scaling the coupling capacitance by a “Miller Coupling Factor” to account for push-in or push-out. Homework Q3: (a) explain upper and lower bounds on the Miller Coupling Factor for a victim wire that is between two parallel aggressor wires, assuming step transitions; (b) give an estimate of the ratio (Delay Uncertainty / Nominal Delay) in the 90nm and 65nm technology nodes.

Delay

Noise

Aggressor Victim

Delay Uncertainty

0.35 0.30 0.25 0.20 0.15 0.1025303540455055606570758085

∆Td

/ Td

(%)

Technology Generation (µm)

Nominal DelayDelay Uncertainty

•Slide courtesy of Kevin Cao, Berkeley


What is Inductance?

nn Inductance is the flux induced by current Inductance is the flux induced by current variationvariation

1S2S

1111

1

dsBS

•=Φ ∫ 2112

2

dsBS

•=Φ ∫I

Self InductanceI11Φ

=I12Φ

=Mutual Inductance

•Slide courtesy of Massoud/Sylvester/Kawa, Synopsys


Inductance§ When signal is coupled to a ground plane, the current

loop has an inductance.l The inductance is more apparent for upper layer metals and

longer linesl Simple lumped model (more nodes)

§ Inductance, makes the interconnect like a transmission line.l Propagates signal energy, with delay.l Results in sharper rise times.

VI

VO_ind

VO_RC

T-Line

VI VO



Mutual Inductance

§ Magnetic flux couples to many signalsl Not just to immediate adjacent signals

(unlike capacitors.)l Coupling over a larger range. l Sensitive to geometry and configuration.l Much bigger lumped model

- Matrix of coupling coefficients not sparse

§ Very big problem if we must analyze every signall Computationally, we know how, but too

complexl E.g., constrain problem by not building

arbitrary networks



Inductance is Important…Inductance is Important…Inductance is Important…

§ If where

§ Copper interconnects à R is reduced

§ Faster clock speeds

§ Thick, low-resistance (reverse-scaled) global lines

§ Chips are getting larger à long lines à large current loops

§ Frequency of interest is determined by signal rise time,not clock frequency

RL ≈ω

==

rtf

πππω

122

Massoud/Sylvester/Kawa, Synopsys •Slide courtesy of Massoud/Sylvester/Kawa, Synopsys


On-Chip Inductance On-Chip Inductance

§ Inductance is a loop quantity

§ Knowledge of return path is required, but hard to determine

Signal Line

Return Path

Massoud/Sylvester/Kawa, Synopsys •Slide courtesy of Massoud/Sylvester/Kawa, Synopsys


Frequency-Dependent Return PathFrequency-Dependent Return Path

§ At low frequency, and current tries tol minimize impedance l minimize resistancel use as many returns as possible (parallel resistances)

§ At high frequency, and current tries tol minimize impedance l minimize inductancel use smallest possible loop (closest return path) à L dominates, current

returns “collapse”l Power and ground lines always available as low-impedance current returns

Signal Gnd Gnd GndGndGndGnd

)( LjR ω+

)( LR ω>>

)( LR ω<<)( LjR ω+

Signal Gnd Gnd GndGndGndGnd

•Slide courtesy of Massoud/Sylvester/Kawa, Synopsys


Inductance vs. Capacitance

§ Capacitancel Locality problem is easy: electric field lines “suck up” to nearest

neighbor conductorsl Local calculation is hard: all the effort is in “accuracy”

§ Inductancel Locality problem is hard: magnetic field lines are not local; current

returns can be complexl Local calculation is easy: no strong geometry dependence;

analytic formulae work very well

§ Intuitions for designl Seesaw effect between inductance and capacitance

l Minimize variations in L and C rather than absolutes- E.g., would techniques used to minimize variation in capacitive coupling also

benefit inductive coupling?

•Slide courtesy of Sylvester/Shepard


Outline

§ Introduction


§ Transistors


§ Performance

§ Power


Power Dissipation

P6Pentium ® proc

486

3862868086

80858080

80084004

0.1

1

10

100

1971 1974 1978 1985 1992 2000Year

Po

wer

(W

atts

)Lead Microprocessor’s power continues to increaseLead Microprocessor’s power continues to increase

Courtesy, Intel

Power delivery and dissipation will be prohibitive(?)Power delivery and dissipation will be prohibitive(?)


Power Density

400480088080

8085

8086

286386

486Pentium® proc

P6

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Po

wer

Den

sity

(W

/cm

2)

Hot Plate

NuclearReactor

RocketNozzle

Power density too high to keep junctions at low temp(?)Power density too high to keep junctions at low temp(?)

Courtesy, Intel


Power and Energy Figures of Merit

§ Power consumption in Wattsl Determines battery life in hoursl Energy density ~120W-hrs/kg ?

§ Peak powerl Determines power ground wiring designsl Sets packaging limits (50W / cm2 ? 120W total ?) ($1/Watt ?)l Impacts signal noise margin and reliability analysis (Why?)

§ Energy efficiency in Joulesl Rate at which power is consumed over time

§ Energy = power * delayl Joules = Watts * secondsl Lower energy number means less power to perform a

computation at the same frequencySlide courtesy of Mary Jane Irwin, PSU


Power versus Energy

Watts

time

Power is height of curve

Watts

time

Approach 1

Approach 2

Approach 2

Approach 1

Energy is area under curve

Lower power design could simply be slower

Two approaches require the same energy



Static CMOS Gate Power

Power dissipation in static CMOS gate: 3 components

§ Dynamic capacitive powerl Still dominant component in current technologyl Charging and discharging the capacitor

§ Crowbar current (short-circuit power)l During a transition, current flows through both P and N

transistors simultaneously for a SHORT period of timel Slow transitions worsen short-circuit power

§ Leakage currentl Even when a device is nominally OFF (VGS=0), a small amount

of current is still flowingl With many devices, can add up to hundreds of mW



Reducing Dynamic Capacitive Power

Pdyn = CL VDD2 P0→1 f

Capacitance:Function of fan-out, wire length, transistor sizes

Supply Voltage:Has been dropping with successive generations

Clock frequency:Increasing…

Activity factor:How often, on average, do wires switch?



Short-Circuit Power Consumption

Finite slope of the input signal causes a direct current path between VDD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting

Vin Vout

CL

Isc



Leakage (Inactive) Power§ Three sources of leakage

§ The dominant is the Source-to-Drain leakage currentl Even when VGS = 0, a small amount of charge is still present

under the gate

l Exponentially related to the gate (and S/D) voltage

§ Source/Drain are junctions and some amount of reverse bias, IS is presentl Typically much smaller than S/D leakage

§ Gate tunneling leakagel When tox is only 5-10atoms, easy for tunneling current to flow

l More of an issue sub 0.10-µm technology

)/)(exp( nkTVVqL

WI TGSD −∝



2001 ITRS Projections of 1/τ and Isd,leak for HP, LP Logic

100

1000

10000

2001 2003 2005 2007 2009 2011 2013 2015

Year

1/τ

(GH

z)

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1.E+01

Isd,leak (µA

/µm)

`

Isd,leak—Low pwr

Isd,leak—High Perf.

1/τ—High Perf.

1/τ—Low Pwr


Projections for Low Power Gate Leakage

•Need for high K driven by Low Power, not High Performance

0.0001

0.001

0.01

0.1

1

10

100

1000

10000

100000

2001 2002 2003 2004 2005 2006 2007 2010 2013 2016

Year

J gat

e (n

orm

aliz

ed)

0.00

0.10

0.20

0.30

0.40

0.50

0.60

0.70

0.80

0.90

1.00

Tox (n

orm

alized)

Simulated Igate, oxy-nitride

Igate spec. from ITRS

Oxy-nitride no longer adequate: high K needed

Tox


Summary: Power and Energy Equations

E = CL VDD2 P0→1 + tsc VDD Ipeak P0→1 + VDD Ileakage

P = CL VDD2 f0→1 + tscVDD Ipeak f0→1 + VDD Ileakage

Dynamic power(~90% today and

decreasing relatively)

Short-circuit power

(~8% today and decreasing absolutely)

Leakage power(~2% today and

increasing relatively)

f0→1 = P0→1 * fclock


Assignment

§ Read Chapters 1, 2 before next time.

§ Remember recitation and lab tomorrow



EXTRA SLIDES


Typical Mid-Size Chip

•~550k instances (gates placed)

Documents

Lecture 01: Introduction - UCSD VLSI CAD Laboratoryvlsicad.ucsd.edu/courses/cse241a/web/lec_notes/Lec1_final.pdf · ... VLSI Integrated Circuits and Systems Design) Winter 2003 Lecture