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TA C162

Lecture 12 Storage Elements

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Todays Agenda

R-S Latch

Register

Thursday, February 11, 2010 Biju K Raveendran@BITS Pilani. 2

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R-S Latch: Simple Storage Element R is used to reset or clear the element

Set it to zero

S is used to set the element Set it to one

If both R and S are one, output could be

quiescent (or quiet) state -- Holds its previous value

, ,

Thursday, February 11, 2010 3Biju K Raveendran@BITS Pilani.

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R-S Latch Summary

Holds previous value in latch

= = Set value to 1

R = 0 S = 1 et Set value to 0 (Reset)

R = S = 0 Both outputs equal one

Final state determined by electrical properties of

ga es Dont do it!

Thursday, February 11, 2010 4Biju K Raveendran@BITS Pilani.

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Gated D Latch

-

gates that allows the latch to be set to valueof D

but only when the switch WE is on.

.

If WE is off, then value saved in the latch

..

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Gated D-Latch Two inputs: D (data) and WE (write enable) when WE = 1, latch is set to value of D

S = NOT(D), R = D when WE = 0, latch holds previous value

= =

Thursday, February 11, 2010 6Biju K Raveendran@BITS Pilani.

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Register Usually we have to deal with values

consisting of more the one bit.

Important to be able to store these largernumber of bits as self-contained units.

Register is a structure that stores a numberof bits, taken together as a unit

A four-bit register is made up of four gated Da c es.

Thursday, February 11, 2010 7Biju K Raveendran@BITS Pilani.

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Register- .

We use a collection of D-latches, all controlled by a

common WE.

When WE = 1, n-bit value D is written to register.

Thursday, February 11, 2010 8Biju K Raveendran@BITS Pilani.

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Notation for sequence of bits Q[3:0] Q[3] Q[2] Q[1] Q[0] Q[l:r] bit l to bit r, from left to right

Examples: A 15:12

A[8:4]

A 15:0

A = 010100110101010115 0

A[14:9] = 101001 A[2:0] = 101

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Memory Is made up of a large number of locations.

Each location is uniquely identifiable.

Each location has ability to store a value.

The unique identifier associated with each

memory ocat on s ca e as ts a ress.

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Address Space & Addressability Address

Unique identifier associated with each memory location

Address Space

Total number of uniquely identifiable locations (usuallya power of 2)N

Addressability Number of bits stored in each memory address location

(e.g., byte-addressable or word-addressable)

Example: 16 M Byte Memory (24 bit Address line)

16 x 220

Addressability = ???

(1 Byte)

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Memory We can build a memory a logical k marray of stored bits.

k= 2n

Address Space:

number of locations

usuall a ower of 2

locations

Addressability:number of bits per location

Thursday, February 11, 2010 12Biju K Raveendran@BITS Pilani.