LATTICESEMI.COM

Leading-edge design and implementation tools optimized for Lattice FPGA architectures

*Aldec Active-HDL Lattice Edition II simulator is only available for Windows. Floating licenses require the additional ALDEC-USBKEY product.

ADVANCED DESIGN SOFTWARE

Key Features and Benefits Design Exploration • ExploredesignalternativeswithImplementations&Strategies• RunManager foracceleratingexplorationandutilizingmulti-coreprocessors

• Lattice Synthesis Engine (LSE) for additional synthesisexplorationoptions.

Ease-of-Use Features• Advancednextgenerationuserinterface• Reportviewwithmessagefilteringfeatures• Extensivecross-probingsupport• File list View for managing multiple constraint, preference,debug,timinganalyzer,andpowercalculatorfiles

• ECOEditorforspecificphysicalnetlist-levelchanges• PlatformDesignertoolformixedsignaldeviceapplications• Programmerforimprovedprogrammingsupport

Improved Design Flow• New Timing Analyzer view allows updated timing analysis,including clock jitter analysis, without re-implementing thedesign

• Simulation Wizard to easily export designs to multiplesimulators

Additional Software Included with Diamond• LatticeMico™systemintegrationforembeddedmicroprocessorapplications

• EPICfull-featuredphysicalnetlist-leveleditor

LatticeDiamond®designsoftwareoffersleading-edgedesignandimplementationtoolsoptimizedforcost-sensitive,low-powerLatticeFPGAarchitectures.DiamondisthenextgenerationreplacementforispLEVER®featuringdesignexploration,easeofuse,improveddesignflow,andnumerousotherenhancements.Thiscombinationofnewandenhancedfeaturesallowsuserstocompletedesignsfaster,easierandwithbetterresultsthanbefore.Diamondsoftware isavailableasadownloadfromtheLatticewebsite forbothWindowsandLinux.Oncedownloadedandinstalled,itcanbeusedwitheitherafreelicenseorasubscriptionlicense.

Diamond Software Free LicenseAfreelicensecanbedownloadedfromtheLatticewebsite.ThislicenseprovidesimmediateaccesstomanypopularLatticedevicessuch asMachXO2™,MachXO™, PlatformManager 2, andLatticeXP2™atnocost.ItincludesSynopsys®SynplifyPro™forLatticesynthesisandAldec®Active-HDL™LatticeEditionIImixedlanguagesimulator.*

Diamond Software Subscription LicenseAsubscription licenseprovidessupport forallLatticeFPGAsincludingtheLatticeECP3devices.ItalsoincludesSynopsys®SynplifyPro™forLatticesynthesisandAldecActive-HDLLatticeEditionIImixedlanguagesimulator*.

Lattice Diamond Key Features

Projects / Implementations/ StrategiesDiamond allowsmore robust projectsandoffersnewcapabilitiesforimproveddesignexploration.Keyfeaturesinclude:

Mixing of Verilog, VHDL, EDIF, andschematicsources Implementationsallowmultipleversionsof a design within a single project foreasydesignexploration Strategiesallowimplementation“recipes”tobeappliedtoanyimplementationwithinaprojectorsharedbetweenprojects Manageandchoosefilesforconstraints,timinganalysis,powercalculation,andhardwaredebug

Ease of Use

Improved Design Flow

Use Run Manager view for parallelprocessingofmultipleimplementationstoexploredesignalternatives for thebestresults

HDL Analysis Tools Hierarchy view automatically parsesanddisplaysthedesignstructure Displayspost-synthesisandpost-mapdesignresources Provideseasyaccess to source filesforeachhierarchylevel Optionsforhierarchycontrol,testbenchgeneration,andsymbolgeneration

Key GUI Elements Common menu and button locationsforallviews Threeuserinterfacesectionsfortools,projects,andoutput Start Page – open projects, importispLEVER projects, online help,softwareupdates ReportView–centralizedlocationforallreportsfromimplementationtools

Addclockjitteranalysistoimprovetherobustnessofyourdesign

Scripting with Tcl Tclcommanddictionariesforprojects,netlists, HDL code checking, powercalculation,andhardwaredebug In addition to the Tcl console in theDiamond environment, a separate

Tclconsoleapplicationallowsrunningscriptsindependently

Easy Export to SimulatorsThe new Simulation Wizard guidesyouthroughall thenecessarystepstogetyourdesign toAldecorModelSimsimulatorsinthemanneryouchoose.

Design Exploration

Speeding Common Functions with ECO Editor & Programmer ECO Editor provides easy editing ofcommonnetlistchangeswithoutusingtheEPICfulleditor ProgrammerallowseasyandintuitiveprogrammingofFPGAs Deployment Tool creates a deviceprogrammingfileformatfortheuser’sdeploymentmethod

GUI for a New Generation of ToolsTheDiamonduser interfacecombinesleadingedgefeaturesandcustomizationwhile offering improved ease of use.Alltoolsopenin“Views”integratedintoa common user interface. Once theoperationforasingletoolislearned,thisknowledgecanbeappliedtoothertools.

Fast, Easy Timing AnalysisTimingAnalysisviewoffersaneasy-to-usegraphicalenvironmentfornavigatingtiminginformation.

See timing, schematic, and detailedpathsforanyconstraintgraphically Easyvisualcuesprovideinstantdesignfeedback Rapidly updated analysis when timingconstraintsarechanged

The HDL Diagram too l shows agraphicaldisplayofthedesignstructureand prov ides BKM (Best KnownMethods)rulechecks.

Synthesis Options Lattice Synthesis Engine (LSE) andSynplifyProareavailableforexploringtoachievebestresults.LSEsupportsMachXO2TM and MachXOTM, whi leSynplifyProisapplicableforalldevices.These twosynthesisoptionssupportVerilogandVHDLlanguagesandusesSynopsysDesignCompilerConstraintsformatforconstraints.

Lattice Diamond Key Tools

Floorplan ViewTiming Analysis

Message Filtering

Reveal Hardware Debugger

Platform Designer

Power Calculator

Physical View

Hierarchy View

IPexpress

Floorplan View provides the ability to view design placement and edit

placement constraints.

Timing Analysis view allows interactive editing of timing constraints and analysis

speeding the timing closure flow.

Analyze your design easily by filtering out messages once you have checked them. Messages can be filtered individually, by

IDs, categories, or severity.

The Reveal Hardware Debugger uses a signal-centric model that allows easy insertion of embedded logic analyzer

debug hardware for real-time analysis.

Platform Designer is a tool for easily building mixed-signal applications using the Platform Manager II device family. Easily configure your design elements

and compile even when the target is for multiple chips.

Power Calculator uses a data driven model to provide accurate results based on actual

silicon performance for both estimation and calculation.

A detailed, read-only view of the physical routing of paths for a more detailed

understanding of timing issues.

In addition to showing the design hierarchy, important information is

available here such as source files used, and both post-synthesis and post-map

resources used.

An interface to the Lattice catalog of modules and IP optimized for

Lattice devices.

LATTICESEMI.COM

Applications Supporttechsupport@latticesemi.com

Copyright © 2013 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., and Lattice (design), IPexpress, ispLEVER, ispVM, Lattice Diamond, LatticeEC, LatticeECP, LatticeECP2, LatticeECP2M, LatticeECP3, LatticeMico, LatticeMico32, LatticeSC, LatticeSCM, LatticeXP, LatticeXP2, MachXO, MachXO2, Reveal and sysIO are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

November 2013 Order #: I0207G

Related Products

Diamond Software Configuration Summary

Product Description Ordering Part Number

USB Key for Aldec Simulation Floating LicenseRequiredtouseAldecsimulationwithafloatinglicense.ExistingUSBkeysfromispLEVERcanalsobeusedwithDiamondsoftware. ALDEC-USBKEY

Download Cable (1.2V to 5V USB Programming Cable) USBprogrammingcable HW-USBN-2ADownload Cable (1.8V to 5V Parallel Port Programming Cable) Parallelportprogrammingcable HW-DLN-3C

Lattice Diamond Free License Lattice Diamond Subscription License

Lattice Device Support

LatticeECP3, LatticeECP2M/S, LatticeSC™, LatticeSCM™, LatticeECP2/S XMachXO2, MachXO, Platform Manager 2, Platform Manager, LatticeECP™, LatticeEC™, LatticeXP™, LatticeXP2, LatticeECP2

X X

Key Software Features

Complete Diamond Software Environment X XThird-Party Software

Synopsys Synplify Pro X XAldec Active-HDL Lattice Edition II X XOperating Systems

Windows 7 (64-bit app for 64-bit OS, 32-bit app for 32-bit OS), Vista and XP (32-bit app for 32-bit OS)

X X

Linux – REHL 6, 5 and 4; Novell SUSE 10 X XLicensing and Ordering

License Terms 1YearNodelockedOnly,Renewable 1YearSubscription,NodelockedorFloatingOrdering Part Number N/A DIAMOND-E-12M

Feature Description

Power Calculator•Useshighlyaccuratedatamodelsandadata-drivenpowermodel•Providespowerestimationandcalculationresults,graphicalpowerdisplays,andreports•Inaddition,PowerEstimatorisastand-alonetoolthatprovidespowerestimation

Spreadsheet View•Enterandviewdesignconstraints(pinassignments,clockresourceusage,globalpreferences,timingpreferences,andmore)•Checkspinassignmentsreal-timeoron-demand

Package View•Easygraphicalassignmentofsignalstopins•GraphicalrepresentationofSSOnoiseanalysis

Floorplanning Tasks

•FloorplanView–viewdesignplacementandeditplacementconstraints•PhysicalView–detailedviewofphysicalroutingofpathstounderstandtimingissues•NetlistView–browsedesignports,instances,andnets.Draganddropintootherviewstosetconstraints.•NCDView–detailedusageinformationofphysicalcomponents•DeviceView–viewdeviceresourcesandeditplacementconstraints

Lattice Synthesis Engine (LSE)•SupportsMachXO2andMachXOdevicefamilies•SupportsVerilog,VHDL,andmixedHDLdesigns•UsesSynopsysDesignCompiler(SDC)formatforconstraints

Reveal Hardware Debugger•Easyinsertionofembeddedlogicanalyzerdebughardwareforreal-timeanalysis•NewstreamlinedRevealAnalyzermodulewithmultiplecursorsandrubberbandingformeasuringeventsinthewaveformdisplay

IPexpress•Theinterfacetothecatalogofmodulesandintellectualproperty(IP)optimizedforLatticedevices•ImportareferencefileforeachmoduleorIPtoeasilyincorporatethechangesresultingfromregeneratingamoduleorIP

Programmer•Comprehensivedeviceprogrammingmanager•EfficientlyprogramsLatticedevicesusingJEDECandbitstreamfilesgeneratedbyLatticesoftware

Deployment Tool •Createsvariousdeviceprogrammingfileformatsfortesters,embeddedsystemsorexternalmemories

Synopsys Synplify Pro for Lattice Synthesis•AutomaticallyproduceanRTLschematicofyourdesign•MixedVHDLandVerilogsynthesissupport•Automaticre-timing(balancingregistersacrosscombinatoriallogic)

Aldec Active-HDL Simulation•MixedlanguagesimulationofVHDLandVerilog•LanguageAssistant•AdvancedBreakpointManagement