Layout Tut

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ECE 438( Digital Integrated Circuits) Cadence Tutorials

Cadence Tutorial 3

Layout Design andSimulation

( Using Virtuoso Layout and Analog Artist ( Spectre))

Department of Electrical & Computer Engineering

University of Waterloo, Ontario, CANADA

[Date: MAY,2006]

Developed by: Manisha Shah ( Lab Instructor)

Assisted by : Paul Hayes, Rasoul Keshavarzi

This document will help students to learn cadence tools. Please send any comments, corrections

and suggestions for improvement to [email protected] or

[email protected] . Your feedback will be greatly appreciated.

______________________________________________________________________________

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This document is solely for educational purpose without any commercial advantage. It is mainly focused

for students of University of Waterloo, Canada. All rights reserved.

Cadence is a trademark of Cadence Design Systems, Inc., 555 River Oaks Parkway, san Jose, CA 95134


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We will be using following Cadence tools in this lab:

Virtuoso Layout for layout, Diva for DRC (design rule checking) Analog Environment for simulation,

Now go to your Tutorial directory and start icfb:

cd cadence

startCds t cmosp18

After you get icfb window, press F6 and it will open the Library Manager window. Lets openour schematic of myinverter for reference. We are going to create a layout based on this

schematic. Everything in the layout should be exactly same as schematic, as later on we are

going to compare the netlists of this schematic and the extracted schematic from layout. So, lets

first see the schematic before we start layout. Here is the schematic ( Fig 0).

Fig 0

Let's start our Layout tutorial now!


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Create Layout Cellview

First create a layout view of the inverter cell, from the icfb window, go to File -> New -> Cell

view and it will open the Create New File window. Select the library CMOSInverter, fill inmyinverter for Cell Name, Virtuoso for Tool and layout for View Name. See Fig 1. Then click

OK.

Fig 1 Create New File Window

Two windows should pop-up, the Virtuoso layout window screen ( Fig 2) and the LSW(Fig 3)which is used for choosing the layers to be used:

Fig 2 Layout window


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Fig 3 LSW

Now get acquainted to the Virtuoso layout screen. It is quite similar to the Composer window,

an important addition are the X and Y absolute coordinates and dX and dY relative coordinates

on the top, these are very useful for drawing precise dimensions. The numbers are in microns butnotice as you move the cursor that the numbers only change as multiples of 0.1u. The

configuration forces a "snap to grid" policy which is very good for enforcing the SCMOS designrules. All the custom layout is done by drawing rectangles or paths by doing Create -> Rectangle

or Create -> Path and chosing the right layer from the LSW window. Doing a good layout ismore than just drawing rectangles though... The most important aspect is planning: you NEED to

use a pencil and paper and make a simple sketch of the layout before you start. You need to

decide:

the position and orientation of all transistors the orientation and metal layer of the supply lines (vdd and gnd) the orientation and layer of the input and output ports the exact sizes for the transistors and metal lines.Let's plan our layout! We will use a layout that has a similar topology to the schematic. It

will have horizontal vdd (top) and gnd (bottom) lines, IN on the left and OUT on the right, all

in metal 1. The two transistors will be arranged horizontally. The layout will be made ascompact as possible (i.e. use minimum distances as allowed by DRC wherever possible).

With these constraints let's start layout!1

1 Reference A


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Options Setup

Before we draw anything lets set the grid resolution to aid in the design process. There are two

types of grid points: Minor & Major. Well set the minor grid dots to display every 0.1 microns,

and the major ones to display every 0.5 microns.

From the Virtuoso Editor, select Options=> Display Set the Minor Spacing to: 0.1 Set the Major Spacing to: 0.5, then click Ok Select Options=> Layout Editor Set the Aperture to 0.1(the mouse step value) Now you will need to redraw the layers. To do so, select Window=>Redraw . This

displays the new grid resolution points.

Click on the Zoom-In icon on the left until you can see both the major dots and minordots. You can also use ruler icon from left buttons and measure the distance between

points. 1

Placing spcpmos and spcnmos

There are two different approaches.

You can create your own NMOS and PMOS cellviews from scratch using the tools from theLSW. That will require another Tutorial for how to draw the NMOS and PMOS cellviews. I am

not going into that detail in this Tutorial.

Other approach is to use the readily available cells from the library CMCpcell. However the

cell used from this library has the minimum Gate width criteria which is 600 n M and as you

know minimum Gate length is 180 n M for our technology. If you want to create a cell for lessthan 600 n M of Gate width, then you have to draw from the scratch using the first approach OR

you can flatten the ready cell of the CMCpcell library and modify the size.

Now lets place NMOS and PMOS for our circuit.

First let's do the nmos. In this tutorial I am going to use the readily available cells spcpmos for

PMOS and spcnmos for NMOS transistor from the library CMCpcell. Now in the Virtuoso

Layout Editing window ( Fig 2), click on the instance icon from the leftside icons. It will

open create instance window. Click on Browse. It will open Library Browser window (Fig 4). Select CMCpcells for Library, spcnmos for Cell and layout for View.

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1 Reference A


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Fig 4

You will notice that Create Instance window has expanded ( Fig 5). Enter 800n M for GateWidth, 180n M for Gate Length and M2 for Names (Make sure all these values should

match with your devices in the schematic).Also make sure you select the Add substrate

contact? box, as we need the substrate contact for the NMOS. Notice that you can change theposition of the substrate contact. For NMOS I would like to have the substrate contact at the

bottom position as later on we will add the vss bar at the bottom and connect the source-substrate

contact of NMOS to the vss bar. So select Bottom for the substrate contact position ( Fig 5).


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Fig 5

Now move your mouse over to the Virtuoso Layout Editing window( Fig 2) and place the

object on the screen with left mouse click. Then hit Esc.

Using the same instructions place spcpmos from the library CMCpcell. Remember to change

the Gate width to 600 n M, Gate Length to 180 n M and M1 for Names for PMOS.

Also make sure Add substarte contact? is checked. Now for PMOS we also need a substratewell. So check the box of Add substarte well?. In this case I would like to have the substarte

contact position at the top as that will be connected to the vdd bar at top later on. So, select

Top for substrate contact position.

Now move your mouse over to the Virtuoso Layout Editing window( Fig 2) and place thespcpmos cell above the spcnmos cell (keeping some distance between two) on the Layout

Window. Then hit Esc. Just to keep in mind that you can always go back and change the

properties of the cell or other drawings in case you made a mistake.


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So, we have NMOS at the bottom and the PMOS at the top in the Layout window. However you

can see them as boxes ( Rectangles). Press shift f to see the inside view ( Fig 6 ). You can use Ctrl Z to zoom in and Shift Z to zoom out. You can pressF on the keyboard. It will

positon your picture to fit properly in the window. It is now time to save your design. ( Design-

>Save) or click on the Save icon at the top left.

Fig 6

Now lets spend some time here to understand these blocks. The blue area is the active area. For

the PMOS the bottom part contains source, gate and drain contacts. The vertical bar is the Gate

Poly. Two small squares on either side of the Gate Poly are the Source and Drain contacts. Thetwo small squares in top part of the cell are the substrate contacts.Similarly for NMOS ( the


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Fig 7

Save your design. It will be a good idea to save your design after every step.

Creating Shape Pins

First we will draw a rectangle of metal1 dg for both vdd at top and vss at bottom.Select metal 1 dg from LSW window. Then click on the rectangle icon at leftside in the Layout

window and draw two rectangles, one at the top and one at the bottom. Now we will add contact

pins for vdd and vss. For that select metal 1 pn from the LSW window. Then in the Layoutwindow select Create-> pin. It will open the Create Symbolic Pin window. First click on the

shape pin button for mode, so it will open now the Create Shape Pin window( Fig 8).

Write vdd in the Terminal Names box. Select inputOutput for I/O type andTop, Left , Right for the Access Direction. See Fig 8


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Fig 8

Now go back to your Layout window and draw another rectangle inside the rectangle at top. Thisis the vdd pin. Dont do Esc here.

Go back to Create Shape Pin window. Now type vss for Terminal Names. Everything else

should be the same as above window. Draw a rectangle for the vss inside the metal 1 rectangle atthe bottom in the Layout window. This will create the vss pin.

Make sure names vdd and vss are same as your schematic Names.

Keep in mind that anytime if you make mistake, you can always do Esc and start again.

Lets create Vin and Vout pins.

Click on the Create Shape Pin window again. Type Vin for Terminal Names. Change

I/O Direction to input as this is an input pin. Everything else should be the same as above

window. Now draw a small rectangle for the Vin pin at the left side of the drawing in theLayout window.

Now for Vout pin, click again on the Create Shape Pin window. Type Vout for Terminal

Names. Change I/O Direction to output and draw a small rectangle for the Vout pin at the

right side of the drawing in the Layout window. Now hit Esc.

We need to draw metal 1 rectangle around the pins Vin and Vout rectangles. For that select

metal1 dg from LSW window. Then click on the rectangle icon at leftside in the Layoutwindow and draw two rectangles, one around the Vin pin and other around the Vout pin.

Your drawing in the Layout window should look something similar to this ( Fig 9 )now.


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Fig 9

You have a vdd pin at top, vss pin at bottom, Vin pin on left and Vout pin on right.

Now we will draw a path using metal1 dg for following connections:

1) From the substrate contact (which is also connected to source) of NMOS to the vss pin2) From the substrate contact (which is also connected to source) of PMOS to the vdd pin3) From the drain path to the Vout pin ( on right)

Select metal1 dg from the LSW window. Click on the path icon on the leftside in your

Layout window. Then draw all these three paths.

We also have to draw a path between Gate poly and the Vin pin. For that we will need to put a

contact of metal 1 to poly. Go to Create-> contact. in the Layout window. It will open a

window called Create Contact as below ( Fig 10 ). Select M1_Poly1 for Contact Type.

Then move your mouse over to the Layout window and place this contact somewhere betweenthe Gate poly path and the Vin pin. Then hit Esc.


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Fig 10

Now using metal1 dg and path icon draw a path between Vin pin ( left one) and the contact.

Then select poly1 dg from the LSW window. Click on the path in the Layout window anddraw a poly between this contact and the Gate poly path. See Fig

Your final layout is ready( Fig 11 ).

Some tips:If you feel you made a mistake in drawing any path, contact or any other, you can always delete

it and then redraw it. To delete just select the path using left mouse click and the Edit-> Delete.

Now we will perform the DRC check.


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Fig 11

DRC

Lets do DRC check now. You can also do DRC check after each step to make sure you are

doing ok. DRC check is for the design rules check. There are certain design rules for drawing theLayout of the circuit. Please refer to the Cadence help document for Design rules.

For DRC, go to Verify -> DRC in the Layout window. It will open the window called DRC.

Make sure you have selected divaDRC.rul as Rules File and cmosp18 as Rules Library.See Fig 12. Click Ok.


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Fig 12

Now check your icfb window. Expand the icfb window in order to view the messages that will

follow. See if you find any errors at the end of the process. The error markers will be highlighted

at particular areas on the layout drawing where there are problems. So, go back and fix the errorsin your layout design. Sometimes the easiest way to correct errors is to delete the controversial

layers, and redraw them properly, by selecting each layer and pressing the Delete key on your

keyboard. Also you might wanted to zoom in your design to have a better view of the interested

area ( Remember the keys Ctrl Z and Shift Z ).

To delete the error markers, go to Verify -> Markers -> Delete all...

Dont forget to save your design if you made any changes.

Now, assuming that you have fixed all the DRC errors, we will move to the next step.

The next step is to extract the schematic from your layout. Circuit extraction is performed afterthe mask layout design is completed, in order to create a detailed net-list ( or circuit description)

for the simulation tool. The circuit extractor is capable of identifying the individual transistors

and their interconnections (on various layers), as well as the parasitic resistances andcapacitances that are inevitably present between these layers. Thus, the extracted net-list can

provide a very accurate estimation of the actual device dimensions and device parasitics that

ultimately determine the circuit performance. The extracted net-list file and parameters aresubsequently used in Layout-versus-Schematic comparison ( LVS) and in detailed transistor

level simulations ( post-layout simulation).1

1 From Reference A


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Extract Schematic

Lets extract the schematic now. Make sure you have a layout window with a finished design

ready and no DRC errors.

From the Layout Editing Window, select Verify -> Extract.You will see a new window with extraction options. Notice that the View Names contains

extracted in the box. You should have divaEXT.rul as Rules File and cmosp18 as

Rules Library. We will not select any switch at present. The ideal case ( default options) wouldresult in a list much similar to your schematic. To enable the extraction of parasiti devices, a

switch has to be specified. We will do that later on. See Fig 13. Click Ok.

Fig 13

Wait for a while and watch your icfb window during that time. At the end you will see some

messages as follows in the icfb window.

Total errors found : 0Saving rep CMOSInverter/myinverter/extracted

So, you will notice that a new cellview has been generated in your library ( Go to Library

Manager). This cellview is called extracted view. See Fig 14.


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Fig 14

Double click on extracted in Library Manager to load the extracted cellview. It will display a

layout that looks almost identical to the layout you just extracted. Toggle between Shift-F andCtrl-F to see different levels of hierarchy.

Notice the transistor symbols ( Fig 15).

Now we will perform the LVS ( Layout Verses Schematic). This will compare the schematic andthe extracted layout to see if they are identical and their netlist matches.


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Fig 15

You can close the above window now if you want.

LVS( Layout Versus Schematic)

In your Layout Editing window, go to Verify -> LVS . It will open the window called

LVS. Click on the Browse, it will open the Library Manager window, select the library, cell

and view for both schematic and extracted netlist as shown below in the figure ( Fig 16). Checkyour Rules File and Rules Library, should be as shown in the figure.

Then click on the Run button.

Check your icfb window. It will display the message LVS job is now started.


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Fig 16

After a while it will display the message window called Analysis Job Succeeded and you will

see the message ..succeeeded if everything works fine.

Click OK.

Now lets check the Output report to see the actual result of an LVS run.

Click on the LVS window. Click on the output button next to Run button. It will displayanother window as shown below in Fig 17.

Now take a look at the complete LVS result here. The most important part of the report is themessage The net-lists failed to match. If you discover that there is a mismatch, you must go

back to the layout view or the schematic view and correct the error(s).

If there are any errors, you can see the error display. Click on the Error Display button in the

LVS form window. In the Error Display window, select Auto-Zoom. Then click on

First and you will see some description. Click on Next to display next error. Keep on going

and then fix the errors in your Layout view and/or schematic view.


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Fig 17

Ok, I got mismatch results. The schematic design does not match with the layout design. So I did

some modifications to the schematic and the symbol cellview of myinverter. In schematiccellview, I delete vdd and vss ( which I had placed before from analoglib library), instead I add

pins for vdd and vss as I have pins for vdd and vss in my layout design. I also add pins vdd and

vss to the symbol as well to match with schematic. The new schematic ( Fig 18) and symbol

cellview (Fig 19)are shown below.


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Fig 18

Notice pins for vdd and vss. The direction is input/output for these pins.


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Fig 19

Notice two new pins vdd and vss in the symbol. The direction is again input/output (both) for

these pins.

Also you have to make sure the names, properties of your devices should exactly same in both

schematic and layout designs.

Now, lets do check and save as we did changes in our designs. Anytime you change your

design, dont forget to do check and save.

If everything is ok, then perform LVS again and check the output file again. If you have made

any changes in your layout design, then you should perform DRC again. Also you need to extract

again the schematic from layout and then perform LVS.

This time I got no errors and my net-lists match. The net-lists of the schematic and the extracted

one are indeed matching. See the output report below(Fig 20).


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Fig 20

Next step will be the simulation.

Simulation of Extracted CellView

After a successful LVS you will have two main cellviews for the same circuit. The first one is

the schematic, your initial design and the second one is the extracted from layout.

You can run the simulation again on your initial schematic and find out the delay of your CMOS

Inverter.

Now lets run the simulation for extracted cellview.

Go to the Library Manager. Open your test bench schematic, Fig 21 below. I have a DCpower supply in my symbol test bench circuit.


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Fig 21

We will repeat the steps of simulation with little modification for extracted one at some places.

In the Virtuoso Schematic window of your testbench cellview (myinverter_testbench) go to

Tools -> Analog Environment. You will get Virtuoso Analog Design Environment (1) ( also

known as Virtuoso Analog Artist) window ( Fig 22).


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Fig 22 Analog Design Enviornment

Follow the steps:

1) In the Virtuoso Analog Design Environment, go to

Setup -> Simulator/Directory/Host, and choose Spectre in the pop-up window. Click OK.

( Spectre is similar to spice)

2) In the Virtuoso Analog Design Environment, go to Setup -> Model Libraries .

Enter following path in the box under the Model Library file

/home/cadence/kits/cmosp18/models/spectre/cor_std_mos.scs

Enter tt in the box under Section(.opt).

See Fig 23. Click on Add button. Then click OK.


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Fig 23

3) In the Virtuoso Analog Design Environment, go to Setup -> Enviornment. This willopen a window called Enviornment Options ( Fig 24).

Type the word extracted before the word schematic in the box Switch View List.

Fig 24


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Click OK.

4) In the Virtouso Analog Artist, go to Analyses -> Choose... ( Fig 25). Choose a transientanalysis. Enter the stop time for transient analysis. Lets type 500n for stop time. Click OK.

Fig 25 Choosing Analysis

5) In the Virtouso Analog Artist, go to Outputs -> to be plotted -> select on schematic.

Select node voltages by clicking on the input and output nets(wires) to select input and output

voltages. net3 and net6 will appear under the output section. See Fig 26 below.

Fig 26


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Now we can finally simulate! Click on the Run Simulation button (looks like a green light) on

the right or go to Simulation -> Run.

It will start simulation. You will need to wait for a while. You should check your icfb window

for messages while it is running the simulation.

Assuming there are no errors you can now admire the simulation results.

You should finally get the desired simulation results, input and output square waves!

Zoom in your waveforms. Using the calculator option, calculate delay from your waveforms.

Now you can compare the delay of your original schematic waveforms and the delay from your

extracted cellview waveforms.

Switches

Now lets do something more. We will set switch to see the parasitic capacitors and parasitic

resistors in our layout circuit.

From the Library Manager open your Layout cellview of the cell myinverter from Library

CMOSInverter.

In the Layout Editing window, go to Verify -> Extract.. It will open the window called

Extractor. See Fig 27.

Fig 27


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Click on the Set switches button. In the pop up window ( Fig 28) select parasitic caps and

click OK.

Fig 28

You will find parasitic_caps in the box Switch Names in your Extractor window.

Click OK. Now check your icfb window to see for any errors after extraction. If no errors, it will

give you the message .extracted.

Now load the extracted cellview from Library Manager. In the extracted cell view , press Shift-

F on your keyboard. You can notice some capacitors are displayed in your cellview ( Fig 29).You can also see the values of these parasitic capacitors.


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Fig 29

You can run the simulation on this extracted cellview, which has some parasitic caps now. (Refer to the section Simulation of Extrated Cellview Page 19). Calculate the delay.

Compare the delay of original schematic waveforms and the extracted cellview waveforms.


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Parasitic Resistors

You can also set the switch for parasitic resistors. Follow the same instructions( Section

Switches).

However this time you need to choose parasitic_resistors_only in the set switches window(Fig 30 ) instead of parasitic_caps.

Fig 30

You can run the simulation for this extracted cellview which has parasitic resistors and thencompare the waveforms with your initial schematic waveforms.

This the End of the this Tutorial !!!!!! Congratulations !!!!!!!!!!!

REFERENCES:

(A) Layout Design and Simulation Tutorial - Royal Military College of Canada

Documents

Layout Tut