Layout Compaction

8/2/2019 Layout Compaction

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LAYOUT COMPACTION


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VLSI DESIGN INTRODUCTION

Large no of devices.

Optimization requirements

for high performance.

Area.

Speed.

Power dissipation.

Design time.

Testability.


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VLSI DESIGN CYCLE

1. System specification

2. Functional design

3. Logic design

4. Circuit design

5. Physical design

6. Design verification7. Fabrication

8. Packaging, testing, and debugging


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PHYSICAL DESIGN

Converts a circuit description into a geometric

description.

This description is used for fabrication of the chip.

Basic steps in the physical design cycle:

i. Partitioning

ii. Floorplanning and placementiii. Routing

iv. Compaction


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PHYSICAL DESIGN IN DETAIL


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Compaction tries to minimize total layout area while

Retaining speedRespecting violating design rules anddesigner-specified constraints

Three ways to minimize the layout area

Reducing inter-feature spaceCheck spacing design rules

Reducing feature size Check size rules

Reshaping features

Electrical connectivity must be preserved


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DESIGN RULES

Interface between Design Engineer and ProcessEngineer

Guidelines for constructing process masks

Unit dimension: Minimum line width

Scalable design rules: lambda parameter Absolute dimensions (micron rules)


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PROCESS LAYERS


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Constraint Graph Based Compaction

Constraint graph G = (V,E)

Each vertex v V represents a component.

The set of edges (E) represents constraints.


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Connectivity Constraints

If two features X and Y are required to be within adistance s of each other.

A physical connection can be represented in thegraph as a pair of edges between X and Y, each withweight s.


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Separation Constraints

Two features X and Y are required to be at leastd units apart from each other.

Represented as an edge from X to Y of weight d.


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Example


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Virtual Grid Based Compaction This method assumes that the layout is to be drawn

on a grid.

Each component is considered attached to a grid line.

The compaction operation compresses the grid along

with all components placed on it keeping the gridlines straight along the way.

The minimum distance between two adjacent gridlines depends on the components on these gridlines.

X-compaction is followed by Y-compaction.Advantage: Simple and easy to implement.

Disadvantage: Does not produce compact layouts as

compared to the constraint graph method.


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Example


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2- Dimensional Compaction

2-D compaction is in general much better than

performing 1-D compaction.

2-D compaction, if solved optimally, produces

minimum-area layouts.

It is very time consuming.

Thus 1-D compaction techniques have beenproposed.

Perform x-direction compaction moves whilemaking small moves in the y-direction.


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Example


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1-Dimensional Compaction

A deterministic algorithm.Key idea is to provide enough lateral

movements to blocks during compaction toresolve interferences.

This is called 1-dimensional compactor, sincethe geometry is not as free as in true 2-dimensional compaction.

The algorithm maintains an X-Y adjacencygraph.

Vertices represent blocks.

Edges represent horizontal and vertical adjacency.


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Two blocks have a horizontal edge if they share a

vertical boundary.

Two blocks have a vertical edge if they share ahorizontal boundary.

The labels on the edges represent the minimum

allowable distance between blocks.

Four additional vertices are added to keep all the blockswithin the required bounded rectangle.

Free space is ignored in computing the neighborhood

edges between blocks

The algorithm assumes that the input is a partially

completed layout, obtained by two applications of a 1-Dcompactor.


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Maintains two lists floor and ceiling.

Floor consists of all the blocks which are visiblefrom the top, and may become a neighbor offuture block.

Ceiling is a list of all blocks which can be movedimmediately (namely, those which are visiblefrom the bottom).

Selects the lowest block in the ceiling list andmoves it to the place on the floor which

maximizes the gap betweenfloor and ceiling. The process is continued until all blocks aremoved from ceiling tofloor.


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Layout Constraints

For a given layout instance, all features may bedescribed by a set of placement constraints

These layout constraints are imposed by designrules Min spacing (separation) design rules


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Expressing constraints


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Goal of 1-D compaction is to generate a minimumwidth layout.

Determination of minimum width is equivalent tosolving a longest path problem.

The longest path from source to a vertex is thecoordinate of the vertex.

In practical layouts, the constraints graphs are verylocal. Most edges represent very local constraints in thelayout.

Theoretically, run time is O(|V|+|E|) Practically, run time is close to linear in |V|, the size ofthe layout!


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Compute the longest path in a graph G = (constraints is aset of labels, Origin is the super-source of the DAG)Forward-prop(W){for each vertex v in Wfor each edge from vvalue(w) = max(value(w), value(v) + value(w) + constraint())

if all incoming edges of w have been traversedadd w to W}Longest path(G)Forward_prop(Origin)}


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Compute the longest path in a graph G = (constraints is a set of labels, Origin is the super-source of the DAG)Forward-prop(W) {for each vertex v in Wfor each edge from v

value(w) = max(value(w), value(v) + value(w) + constraint())if all incoming edges of w have been traversedadd w to W}Longest path(G)Forward_prop(Origin)

}


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Compute the longest path in a graph G = (constraints is a

set of labels, Origin is the super-source of the DAG)Forward-prop(W){for each vertex v in Wfor each edge from vvalue(w) = max(value(w), value(v) + value(w) + constraint())if all incoming edges of w have been traversedadd w to W}Longest path(G)Forward_prop(Origin)}


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Compute the longest path in a graph G = (constraintsis a set of labels, Origin is the super-source of the DAG)Forward-prop(W){for each vertex v in Wfor each edge from vvalue(w) = max(value(w), value(v) + value(w) + constraint())

if all incoming edges of w have been traversedadd w to W}Longest path(G)Forward_prop(Origin)}


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Compute the longest path in a graph G = (constraints is aset of labels, Origin is the super-source of the DAG)Forward-prop(W){for each vertex v in Wfor each edge from v

value(w) = max(value(w), value(v) + value(w) + constraint())if all incoming edges of w have been traversedadd w to W}Longest path(G)Forward_prop(Origin)

}


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References

Algorithms for VLSI Design Automation-

Sabih H.Gerez

Layout compaction - Prof. A. R. Newton

Prof. Kurt Keutzer

www.wikipedia.com

www.gigapedia.com


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THANK YOU

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Layout Compaction