Layout-based Logic Decomposition for Timing Optimization

Yun-Yin Lien* Youn-Long Lin

Department of Computer Science, National Tsing Hua University,

Hsin-Chu, Taiwan 300, ROC

*Global Unichip Corporation

UniChipOutline

Introduction MotivationPrevious WorkProposed MethodsExperimental ResultsConclusions and Future Works

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Timing meet?No

Yes

Finished

Design HouseLogic Synthesis

Placementand Routing

ASIC Vender

Introduction

Traditional ASIC design flow

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Design HouseLogic Synthesis

ASIC VenderInitial Placement and Routing

Layout-based Logic SynthesisLayout-based Logic Synthesis

Incremental Placementand Routing

Incremental Placementand Routing

Extracted wire RC

Changed netlist,ECO information

Extracted wire RC

Timing meet

Timing not meet

Optimization or Finish

Design Flow Considering Layout

UniChipLayout-based Logic Synthesis

Some existing techniques Gate Sizing Buffer Insertion Rewiring Logic Restructuring Logic Decomposition

We combine Gate Sizing, Buffer Insertion and Logic Decomposition

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The effect of Gate Sizing is limited by the library

Library

A B EDC

A C DB

A CB

A B

A C DB

A B

A B

f

f

Observation 1

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Inputs to a cell can be divided into critical part and non-critical part

noncritical f

criticalnoncritical

noncritical

noncriticalnoncritical

noncritical

criticalf

Observation 2

UniChipMotivation

Break the limitation of gate sizing Increase gate sizing opportunity Logic decomposition for gate sizing … rule1

Speed up critical path Divide critical inputs and non-critical inputs of a

cell Logic decomposition for speeding up critical

path … rule2

UniChipPrevious Work Logic Decomposition -- Singh et al.

During technology mapping Simple delay model

Retiming and resynthesis[SIS] -- Malik et al.

Partition -- Beardslee et al.Logic restructuring and buffer insertion --

Jiang et al.

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Initial Placementand Routing

Initial Placementand Routing

Layout-basedLogic Synthesis

Layout-basedLogic Synthesis

Incremental Placement

and Routing

Incremental Placement

and Routing

Delay CalculatorPath Extraction

Delay CalculatorPath Extraction

Area Reduction•Gate Downsizing•Buffer Removal

Area Reduction•Gate Downsizing•Buffer Removal

Buffer insertion Gate sizing Logic Decomposition

Buffer insertion Gate sizing Logic Decomposition ECO information

Wire RC

Circuit Library

Timing meet

Proposed System Flow

UniChipLogic Decomposition

Cell Selection Cell Substitute GenerationCandidate SelectionCell Substitution

UniChipCell Selection

Cell Selection Criteria Cell inputs consists of critical part and non-

critical part No gain in sizing up the cell

cell had been sized up to the largest template before this iteration

cell has negative gate sizing score in this iteration

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f

f(a)

f

(c)

f

(b)

f

(d)

12

43

1234

1234

1234

1234

Cell Substitute Generation

two-level substitutes For rule1

. . .

UniChipCell Substitute Generation(cont.) For rule2

Dcritical

criticalnoncritical

noncritical

D1Anoncriticalnoncritical

criticalcritical

D2A

UniChipCandidate Selection

Criteria The longest path delaycandidate < The longest pa

th delayoriginal The longest path delaycandidate is the smallest o

ne among all substitutions

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A1A2

An

B...

C1C2

Cm

..

.

...

...

...

..

A1

An

B1

..

.

C1C2

Cm

..

.Bk+1A2

...

...

...

...

B2...

Bk...

..

...

Candidate Selection (cont.)

Assign each cell of group B to the largest template for rule1, smallest template for rule2

Assign location on layout cell Bk+1 = cell B cell B1~Bk nearby cell B

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G1

G2

4321

fG

wxyz

f

Candidate

Cell Substitution

Sort inputs of G by criticality Get the proper size of each cell

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D

D1

D2D1

D2

DReplace

D2

Insert

D2

D1

Initial Placementand Routing

Initial Placementand Routing

Layout-basedLogic Synthesis

Layout-basedLogic Synthesis

Incremental Placement

and Routing

Incremental Placement

and Routing

Delay CalculatorPath Extraction

Delay CalculatorPath Extraction

ECO information

Wire RC

Incremental P & R

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Unmapped circuitUnmapped circuit

SIS: Map for SpeedLogic Gate Sizing

SIS: Map for SpeedLogic Gate Sizing

TimberWolfSC:Initial Placementand Routing

TimberWolfSC:Initial Placementand Routing

G:Gate SizingB:Buffer InsertionD:Logic Decomposition

Layout-based Optimization

System

Layout-based Optimization

System

Final LayoutFinal Layout

TimberWolfSC:Final Placementand Routing

TimberWolfSC:Final Placementand Routing

SISGS

Experimental Procedures

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Delay Reduction (Compare with SISGS)

0%

10%

20%

30%

40%

50%

60%

C1355 C5315 s298 s1423 s5378 s9234 s13207 s15850 s35932 s38417

G GD

Experimental Results

Average delay reduction G:16.39% G+D:24.24%

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Area Increment (Compare with SISGS)

0%

2%

4%

6%

8%

10%

12%

14%

C1355 C5315 s298 s1423 s5378 s9234 s13207 s15850 s35932 s38417

G GD

Experimental Results (cont.)

Average area increment G:2.50% G+D:4.88%

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0

10000

20000

30000

40000

50000

60000

70000

80000

C1355 C5315 s298 s1423 s5378 s9234 s13207 s15850 s35932 s38417

(Sec

onds

)

G GD

Experimental Results (cont.)

CPU Time

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Delay Reduction (Compare with SISGS)

0%

10%

20%

30%

40%

50%

60%

GB GD GBD

Experimental Results(cont.)

Average delay reduction

G+B:19.96% G+D:24.24% G+B+D:25.43%

UniChipConclusions

Combine logic decomposition with gate sizing (compare with SISGS ) Only Gate Sizing

average delay reduction is 16.39%maximum delay reduction is 32.58%

Gate Sizing + Rule1average delay reduction is 20.29%maximum delay reduction is 41%

Gate Sizing + Rule2average delay reduction is 23.24%maximum delay reduction is 54%

UniChipDiscussion

Logic Decomposition Suitable for circuits with decentralized critical p

aths Useful for library with high variety in the numbe

r of template for each gateThe effectiveness of Gate Sizing is limited by

the library and the persistent netlist structure

Buffer insertion is effective for nets with high fanout counts

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Future Work

Design a filter program which can analyze the input circuit first Find suitable optimized techniques Save program run time

Interconnect-Centric Methodology