Layered Protocol Wrappers 1

James Moscolajmm5@arl.wustl.edu

Washington University

August 26, 2002

Layered Protocol WrappersDesign and Interface review

Layered Protocol Wrappers 2

Layout of Protocol Wrappers with MAC circuit

Cell Wrapper + Frame Wrapper

MAC Egress MAC Ingress

ATMCells

ATMCells

MAC Frames

MAC Frames

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The Cell Processor

• Cell Functions • Drops cells with bad cell headers• Recomputes cell header for outgoing cells

(MAC Ingress side)

• Flow Functions• Bypasses cells for different flows

• Implements Control-Plane Interface• Handles control cells• Write control / read status

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The Cell Processor

• Data Flow inside the Cell Processor

Cells

Control

DispatchCheck

HEC

HEC

Set

The output FIFOs are serviced in the following order:1. Controls Cells2. Bypassed Cells3. Application Cells

MAC Egress MAC Ingress

ATMCells

ATMCells

MAC Frames

Frame Processor

and MAC circuit

VC

I = 2

3h

VC

I = 3

2 –

35h

All other VCIs

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The Frame Processor

• Segmentation and Reassembly– Reassembles cells into frames (MAC egress)– Segments frames into cells (MAC ingress)

• Frame Functions– Detects frame boundaries– Checks & Generates AAL5 CRC

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MAC Egress MAC Ingress

The Frame Processor

• Data Flow inside the Frame Processor

Frame

Detection

Cell

AAL5CRC AAL5CRCation

SegmentMAC circuit

MAC Frames

ATMCells

ATMCells

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The Frame Processor

Module Details

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The Frame Processor

• Frame Detection Module (MAC Egress)– Single Cell Frame

• Buffers cell while waiting for length• Once length is received outputs appropriate number of words

to the MAC Egress circuit

– Multiple Cell Frame (cells A and B)• If not the last cell (PTI=‘0’), outputs all but last two words in cell

A to MAC Egress circuit (the last two words my be padding)• if cell B PTI=‘0’, the last two words of cell A are output along

with all but the last two words of the cell B• if cell B PTI=‘1’, cell B is buffered until the length is reached.

Once the length is reached, it can be determined whether or not the last two words of cell A should be output to the MAC Egress circuit and how many words of cell B should be output to the MAC Egress circuit

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The Frame Processor

• Cell Segmentation Module (MAC Ingress)– Two FIFOs

• data_fifo– written to whenever SOF_APPL_IN or DataEn_APPL_IN is

asserted by MAC Ingress circuit• length_fifo

– written to when…» a cells worth of data has been put into the data_fifo» EOF_APPL_IN has been asserted

– Cells are output as long as the length_fifo has data• dequeue length_fifo and output that many words from the

data_fifo – should always be 48 bytes, except for the last cell, when it should

be <= 48 bytes

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The Frame Processor

Interface Details

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The Frame Processor

• Frame Interface (MAC Egress)– SOF_OUT_APPL

• high for 1 clock cycle during first ATM header word• signals start of new AAL5 frame• NOTE: HEC is NOT sent after this signal

– DataEn_OUT_APPL• high during valid payload data (not during sof)• high during EOF_OUT_APPL and 2 AAL5 trailer words

– D_OUT_APPL• 32-bit data bus

– EOF_OUT_APPL• high during 1 clock cycle of last payload word in AAL5 frame• followed by two trailer words of AAL5 frame• if no EOF_OUT_APPL is asserted for a frame (consecutive

SOF_OUT_APPLs without an EOF_OUT_APPL), the frame is corrupt and should be discarded/handled by the application

– TCA_OUT_APPL• this signal is passed through, it does not affect the behavior of the

wrapper

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The Frame Processor

• Frame Interface (MAC Egress) cont …– A frame with an invalid AAL5 CRC …

• will be passed from the Frame Processor to the MAC Egress circuit

• will have an EOF_OUT_APPL • will have a non-zero value in the AAL5 CRC field

– Cells dropped from Multi-cell Frames• if a cell is dropped prior to entering the Frame

wrapper, the frame will have an invalid AAL5 CRC and should be dropped. If the dropped cell is the last cell in the frame, both the current frame and the next frame will be combined with an invalid AAL5 CRC and should be dropped.

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The Frame Processor

• Frame Interface (MAC Ingress)– SOF_APPL_IN

• must assert high for 1 clock cycle while outputting first ATM header word

• NOTE: DO NOT send a HEC, as the HEC word is inserted by the Frame Wrapper

– DataEn_APPL_IN• assert high during valid payload data (not during sof)• assert high during EOF_OUT_APPL and 2 AAL5 trailer words

– D_APPL_IN• 32-bit data bus

– EOF_APPL_IN• assert high during 1 clock cycle of last payload word in AAL5 frame• this interface assumes a user application is following the interface

protocol. If no EOF_APPL_IN is sent for a frame, it is possible for the 2 FIFOs to get out of synch and enter an unknown state

– TCA_APPL_IN• this signal is passed through the wrapper to the user application. An

application should stop sending data when TCA_APPL_IN is deasserted

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The Frame Processor

• Frame Interface (MAC Ingress) cont …– bytes(1 downto 0) of the AAL5 Length field must be set

to the number of valid bytes in the last payload word. Other bytes of the AAL5 Length can be ignored, as they will be calculated by the frame wrapper

– If an application wants a frame to be dropped, any non-zero value can be inserted into the AAL5 CRC field. The frame will still be transmitted, but will get dropped at the next hop.

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The Frame Processor