lab4_writeup

7/27/2019 lab4_writeup

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ICS155B Lab Assignments

Lab 4 Design of MIPS datapath

In this lab you will implement a data path to execute a subset of MIPS ISA shown below.

The data path implements all necessary operation for the execution of the instructions

shown, including PC calculations for next instruction.

where,

rs is source register

rt is source or destination register rd is destination register

shamt supplies the shift amount you will ignore this field and always use shamt !"#

The assignment has two parts$

". %esign and implement a multi&functional A'(.

). %esign and implement the MIPS datapath.

*ou will submit your logic design on a paper#, your +-I'/ design electronically#,and your +-I'/ testbench electronically#.

Please read ALL instructions carefully. Ma0e sure to create a folder, named by your

student id, and submit your 1ip file in it.

Part I: ALU DESIGN



Paper design "23#

The +-I'/ design and testbench 423 5 )23#

%emos 623#

The A'( has two 6)&bit inputs 7A8 and 798 and a 6)&bit output 7C8 and a "&bit output

7:ero8. In addition, it has a signal 7opcode8 for operation selection. The A'( can perform any one of the following operations$

And ; 222 r ; 22"

Add ; 2"2 <or ;2""

Shift&left ;"2" Shift&right;"""

Sub ; ""2

*ou will implement only logical shifts by ", for both 7sll8 and 7srl8. The A'( also

generates a 7:ero8 signal if the A'( output 7C8 e=uals 1ero.

Submit

Paper design to the distribution center pro>ide your name, student id number, course

number and the instructor?s name on the top#. The bloc0 diagram should describe the

A'(. *ou need to show all internal logic. Show all control signals that are necessary, andspecify their sources. (se 6) bit signals and modules whene>er possible. %o not draw

indi>idual gates and flip&flops. Assume that each unit in your design may be represented

with a bloc0.

Ma0e a 1ip file containing the +-I'/ design and +-I'/ testbench of lab4 and

submit it electronically >ia .

Part II: DATAPATH DESIGN and IMPLEMENTATION

Paper design "23#

The +-I'/ design and testbench 423 5 )23#

%emos 623#

%atapath Specification$

The datapath consists of a register file -@#, registers 7A8 and 798, an arithmetic logic

unit A'(#, a result register A'(out# and certain number of multiplexers, shift and

sign extension units. The the memory is an external component of this design. ItsinputsBoutputs are ports on your datapath entity.

The data path also performs next PC computation. There is ust one A'( that is used for

operation execution and for the next address generation. The data path implements PCcomputations and operation execution in different cloc0 cycles. Also, register file read is

done one cycle prior to A'( execution. -egister file write is performed one cycle after

the A'( execution cycle.



The register file specification was gi>en in 'ab 6. *ou will use the beha>ioral >ersion of

your 'ab6 design as a component in 'ab 4. *ou will modify your 'ab 6 so that the

register file contains 6) registers. utputs from the register file are read into registers78A8 and 798. -egisters 7A8 and 798 store >alues that are read from the register file

ser>e as some of# inputs to the A'( during the following cloc0 cycle. -esult register

7A'(out8 is 6)&bit register and it is used to store A'( output.In this lab assignment we will implement support for the following control flow

instructions$

beq rs, rt, address i !rs " rt# t$en P% " P% & ' & sign(e)t!I*+,-:./ 00 1#

bne rs, rt, address i !rs 2" rt# t$en P% " P% & ' & sign(e)t!I*+,-:./ 00 1#

j target P% " P%+3,4415/ 6 !I*+1-:./ 00 1#

lw rt, immediate(rs) rt " Mem+ I*+,-:./ & !rs# /

sw rt, immediate(rs) Mem+ I*+,-:./ & !rs# / " rt

To ma0e the bloc0 diagram of your design clear, please use$

& & & &D for control signals

&&&&&&&&&D continuous line# for data

The bloc0 diagram should describe the top&le>el design of the complete datapath. Specify

all the data and control components. Mar0 all data and control signals and specify

appropriate widths. (se bloc0s to represent A'(, register file, registers etc. %o not showthe internal organi1ation of used components. Show the control unit as a bloc0 and all its

incoming and outgoing signals.

*ou are re7uired to ma0e separate modules for the A'( lab4alu.># and -@ lab6.>

which you implemented for the pre>ious assignment#, and use these as components.

Testing

*our test bench should test ) things$

". A 6&cycle register read&A'( operation&register write se=uence, including the use ofimmediate operands.

). "&cycle PC update using offset in I-.

.*ou do not need to test memory access in this lab.

Submit

Paper design to the distribution center pro>ide your name, student id number, coursenumber and the instructor?s name on the top#.

Ma0e a 1ip file containing the +-I'/ design and +-I'/ testbench of lab4 and

submit it electronically >ia .

Documents

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