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Binary Adders and Subtractors

 Name: __________________________

Objective: The purpose of this experiment is to study the design and implementation ofcombinational adder and subtractor circuits. This includes half and full adders and anexternally controlled full-adder/subtractor combination circuit.

Equipment: One standard Logic Lab Kit and TTL chips.

Procedure:

1.0 Half-Adder Design

1.1 Complete the C (carry) and S (sum) columns in Table 1.1 below for a half-adder circuit. Derive the minimal AND-OR equations for C and S and write

them below in the spaces provided.

x y C C-LAMP S S-LAMP

0 0

0 1

1 0

1 1

Table 1.1: Half-adder truth table

S = _______________ C = _______________

1.2. Connect your circuit using NAND gates and verify that it operates properly by completing the appropriate lamp columns above in Table 1.1. Draw yourfinal circuit implementation below in double-rail form.

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2.0 Half-Subtractor Design

2.1 Complete the B (borrow) and D (difference) columns in Table 1.2 below fora half-subtractor circuit. Derive the minimal AND-OR equations for B and D

and write them below in the spaces provided.

x y B B-LAMP D D-LAMP

0 0

0 1

1 0

1 1

Table 1.2: Half-subtractor truth table

B = _______________ D = _______________

2.2 Connect your circuit using NAND gates and verify that it operates properly by completing the appropriate lamp columns above in Table 1.2. Draw yourfinal circuit implementation below in double-rail form.

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3.0 Full-Adder/Subtractor Circuit Design

3.1 Design a combinational logic circuit to implement a full-adder when anexternal control input, E, is logical zero; or a full-subtractor when E is logical

one. Include two additional indicator lamps, one for "ADD" mode and one for

"SUBTRACT" mode.

3.2 Complete the C, B, and S/D columns in Table 1.3 below for your combinationfull-adder/subtractor circuit. Derive the minimal AND-OR equations for C, B, S

and D and write them below in the space provided

x y z C C-LAMP B B-LAMP S/D S/D-LAMP

0 0 0

0 0 1

0 1 0

0 1 11 0 0

1 0 1

1 1 0

1 1 1

Table 1.3

S = ________________________________________D = ________________________________________

C = ________________________________________

B = ________________________________________

Draw your K-maps for S/D, C, and B in the space below.

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3.3 Connect your circuit using NAND gates and verify that it operates properly bycompleting the appropriate lamp columns in Table 1.3. Draw your final circuit

implementation below in double-rail form.

3.4 When you have completed all the above, have your instructor sign below.

 _______________________________Instructor's Signature

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Questions

Design a full-adder circuit that has two two-bit input words A, B and C, D and

one three-bit sum output word EFG as shown below. Using the complete truthtable method, and K-maps as appropriate, write the minimal AND-OR equations

in the spaces provided below.

A B+ C DE F G (A, C, and E = MSB for each word)

E = ____________________________________

F = ____________________________________

G = ____________________________________

Show your work and K-maps below. (5 points)