1

Lab Manual

El-297 Electronics lab II

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ELECTRONICS LAB II

(EL297)

S. No. Experiments Page

No.

0. a. Introduction to the digital laboratory, equipment used, report and

evaluation.

b. To verify the Truth Tables of basic logic gates.

3-7

1. Plot the transfer characteristics of the CMOS inverter by varying the input

voltage form 0 V to 5 V with step of 0.2V and measuring the output voltages.

Also, verify the truth table of CMOS NAND and NOR gates

8-13

2. To implement and verify

a. Gray-to-BCD code converter and show the output on 7-segment display

b. 4-line to 2-line Priority Encoder.

14-18

3. To test a 4-bit programmable adder/subtracted.

19-22

4. To test an 8-line-to-1-line multiplexer and using it implement a given 4-

variable logical function.

23-26

5. To verify the truth table of the following types of Latches and Flip Flops with

control inputs

(a) R-S (b) D (c) T (d) J-K

27-31

6. To design and implement the circuit of MOD-8 asynchronous and MOD-6

synchronous counters using J-K flip-flops.

32-36

7. Study and verify the load, shift and rotate operation of a 4-bit shift register.

37-40

8. To design and test a 4-bit R-2R ladder type DAC.

41-42

3

EXPERIMENT NO. 0

OBJECTIVE:

a. Introduction to the digital laboratory, equipment used, report and evaluation.

b. To verify the Truth Tables of basic logic gates.

EQUIPMENT/APPARATUS USED:

S. No. Name of the equipment Range/Rating Make

1. Digital IC Trainer .... ....

2. Multi-meter ... ...

BRIEF THEORY:

A Digital Logic Gate is an electronic device that makes logical decisions based on the different

combinations of digital signals present on its inputs. Logic gates are the building blocks of digital

circuits. Combinations of logic gates form circuits designed with specific tasks in mind. They are

fundamental to the design of computers. Digital logic using transistors is often referred as

Transistor-Transistor Logic or TTL gates. These gates are the AND, OR, NOT, NAND, NOR, and

EXOR gates.

AND Gate:

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A

dot (.) is used to show the AND operation i.e. A.B.The symbolic representation of the AND gate

is:

Symbolic representation of AND gate Truth table of AND gate

4

OR Gate: The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high

(1). A plus (+) is used to show the OR operation i.e. A+B. The symbolic representation of the OR

gate is:

NOT Gate: The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It

is also known as an inverter. If the input variable is A, the inverted output is known as NOT

A. This is also shown as A', or A . The symbolic representation of an inverter is:

NAND Gate: This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. It is also known

as universal gate. The outputs of all NAND gates are high if any of the inputs are low. The symbol

is an AND gate with a small circle on the output. The small circle represents inversion. The

symbolic representation of the NAND gate is:

Symbolic representation of OR gate Truth Table of OR gate

Symbolic representation of NOT gate Truth table of NOT gate

Symbolic representation of NAND gate Truth Table of NAND gate

5

NOR Gate: This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all

NOR gates are low if any of the inputs are high. The symbol is an OR gate with a small circle on

the output. The small circle represents inversion. The symbolic representation of the NOR gate is:

EXOR Gate: The output of the Exclusive –OR gate, is 0 when it’s two inputs are the same and its output is 1

when its two inputs are different. It is also known as Anti-coincidence gate.An encircled plus sign

( ) is used to show the EXOR operation.

PIN/CIRCUIT DIAGRAM:

NOT Gate:

IC 7404(HEX Inverter)

14 Pin

Supply voltage :5V

Symbolic representation of NOR gate Symbolic representation of NOR gate

Symbolic representation of EXOR gate Symbolic representation of EXOR gate

6

AND Gate:

IC 7408

14 Pin

Quad 2 input AND Gate

Supply voltage :5V

OR Gate:

IC 7432

14 Pin

Quad 2 input OR Gate

Supply voltage :5V

NAND Gate: I

C 7400

14 Pin

Quad 2 input NAND Gate

Supply voltage :5V

NOR Gate:

IC 7402

14 Pin

Quad 2 input NOR Gate

Supply voltage :5V

7

EXOR Gate:

IC 7486

14 Pin

Quad 2 input EXOR Gate

Supply voltage :5V

PROCEDURE:

1. According to the pin diagram of each IC mentioned above, wire all the gates to verify their

truth tables.

2. Connect the inputs of the gates to the input switches of the LEDs.

3. Connect the output of the gates to the output LEDs.

4. Once all connections have been done, turn on the power switch of theDigital IC Trainer.

5. Operate the switches and fill in the truth table (Write "1" if LED is ON and"0" if LED is

OFF. Apply the various combination of inputs according to the truth table and observe the

condition of Output LEDs.

6. Repeat the above steps 1 to 5 for all the ICs.

OBSERVATION TABLE:

S. No Input(A)

Input

(B)

Output

(NOT)

Y = Ā

Output

(AND)

Y=A.B

Output

(OR)

Y=A+B

Output

(NAND)

.Y A B

Output

(NOR)

Y A B

Output

(XOR)

Y=A B

1.

2.

3.

4.

REFERENCES:

1. Mano, M. M., ″Digital Logic and Computer Design″, PHI, 1989, 3rd Edition.

8

EXPERIMENT NO. 1

OBJECT:

Plot the transfer characteristics of the CMOS inverter by varying the input voltage form 0 V to 5

V with step of 0.2V and measuring the output voltages. Also, verify the truth table of CMOS

NAND and NOR gates.

EQUIPMENT/APPARATUS USED:

S. No. Name of the equipment Range/Rating Make

1. Power Supply .... ....

2. Digital Multi-meter ... ...

3. Potentiometer

4. CMOS (CD4007)

BACKGROUND:

CMOS is currently the most popular digital circuit technology. CMOS logic circuits are available

as standard SSI and MSI packages for use in conventional digital system design. CMOS is also

used in general-purpose VLSI circuits such as memory and microprocessors. The CMOS Inverter

is shown in Figure 1. It consists of an N-channel MOSFET and a P-channel MOSFET. The input

is applied to the two gates. The substrate of each transistor is connected to the source, and therefore

no body effect for both transistors. When Viis high, QN is ON and QP is OFF. The output is low

and VOL≈0 (typically less than 10mV). If Viis low, QN is OFF and QP is ON. The output is high

with VOH≈VDD (typically 10mV less than VDD). Since the inverter current is zero in each case; the

static power dissipation is zero (typically a fraction of μw). The voltage transfer characteristic has

a linear part with a high slope value. This part is obtained when both transistors are ON.

PROCEDURE:

1. Connect the circuit shown in Figure 1. Set the supply to 5V.

2. For different values of Vi in range of 0 to 5V, measure the output voltage Vo and current

from supply IDD. Record your data in Table 1. Take more readings around the point of

maximum conducting for IDD.

3. Plot the voltage-transfer characteristics as shown in Figure 2

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Figure 1: CMOS inverter

Figure 2: Transfer Characteristic

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Figure 3: IC Chip (CD4007).

Observation Table1:

Vi 0 0.4 0.8 1.2 1.6 2.0 2.4 2.6 2.8 3.0 3.2 3.4 3.6 4.0 4.4 5.0

Vo

IDD

To verify truth table of CMOS NOT, NAND and NOR gate.

BRIEF THEORY:

(a) CMOS NOT GATE:

An inverter circuit outputs a voltage representing the opposite logic-level to its input. Its main

function is to invert the input signal applied. If the applied input is low then the output becomes

high and vice versa. Inverters can be constructed using a single NMOS transistor or a

single PMOS transistor coupled with a resistor. Since this 'resistive-drain' approach uses only a

single type of transistor, it can be fabricated at low cost. However, because current flows through

the resistor in one of the two states, the resistive-drain configuration is disadvantaged for power

consumption and processing speed. Alternatively, inverters can be constructed using two

complementary transistors in a CMOS configuration. This configuration greatly reduces power

consumption since one of the transistors is always off in both logic states. Processing speed can

also be improved due to the relatively low resistance compared to the NMOS-only or PMOS-only

type devices. Inverters can also be constructed with bipolar junction transistors (BJT) in either

aresistor–transistor logic (RTL) or a transistor–transistor logic (TTL) configuration.

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Figure 4: CMOS NOT

(b) CMOS NAND GATE:

In digital electronics, a NAND gate (negative-AND) is a logic gate which produces an output

which is false only if all its inputs are true; thus its output is complement to that of the AND gate.

A LOW (0) output results only if both the inputs to the gate are HIGH (1); if one or both inputs

are LOW (0), a HIGH (1) output results. It is made using transistors and junction diodes. By De

Morgan's theorem, AB=A+B, and thus a NAND gate is equivalent to inverters followed by an OR

gate.

Figure 5: CMOS NAND and NOR

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(c) CMOS NOR GATE:

The NOR gate is a digital logic gate that implements logical NOR - it behaves according to the

truth table to the right. A HIGH output (1) results if both the inputs to the gate are LOW (0); if one

or both input is HIGH (1), a LOW output (0) results. NOR is the result of the negation of

the OR operator. It can also be seen as an AND gate with all the inputs inverted. NOR is

a functionally complete operation—NOR gates can be combined to generate any other logical

function. By contrast, the OR operator is monotonic as it can only change LOW to HIGH but not

vice versa.

Figure 6: Pin diagram IC CD 4007

PROCEDURE:

1. Make the proper connections according to the circuit diagram.

2. Provide VDD supply at Pin number 14 and connect the pin 7 to ground.

3. Verify the truth table.

Observations:

Truth Table

CMOS NAND:

A B F

0 0

0 1

1 0

1 1

13

CMOS NOR:

A B F

0 0

0 1

1 0

1 1

REFERENCES:

1. R. J. Tocci, N Widmer, and G. L. Moss, ″Digital Systems, Principles and Applications″,

Pearson, 10th Edition, 2013, Pages: 268-283.

2. Mano, M. M., ″Digital Logic and Computer Design″, PHI, 1989, 3rd Edition, Page: 202-247.

3. Millman, and Grabel, A., ″Microelectronics″, New York: Mc Graw Hill, 2nd Edition, 2010.

Pages: 330-340.

14

EXPERIMENT NO. 2

OBJECT:

To implement and verify

a. Gray to BCD code converter and show the output on 7-segment display.

b. 4-line to 2-line Priority Encoder.

EQUIPMENT/APPARATUS USED:

S. No. Name of the equipment Range/Rating Make

1. ... ...

2.

BRIEF THEORY:

(I) Gray to BCD code converter and show the output on 7-segment display.

Code Converters: A code converter is a circuit that makes two digital systems using different

codes for the same information. It means that a code converter is a code translator from one code

to the other. Since the systems may use two different codes to represent same information, the

code converters are required.

Gray-to Binary Converter: An interesting application for the exclusive-OR gate is a logic gate

to change a gray number to its equivalent in binary Code. The logic circuit can be used to convert

a 4-bit gray-code number G3, G2, G1, G0 into its binary-code number, B3, B2, B1 and B0.

Application: Some sensors send information in Gray code. These must be converted to binary in

order to perform arithmetic operations on it.

LOGICDIAGRAM:

Figure 1: Circuit Diagram of Gray to BCD Code Converter

G3

G2

G1

G0

15

K Maps for Gray to BCD Code Converter

INPUTS OUTPUTS

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 1 0 0 1 0

0 0 1 0 0 0 1 1

0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

0 1 0 1 0 1 1 0

0 1 0 0 0 1 1 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 1 1 0 1 0

1 1 1 0 1 0 1 1

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 0 0 1 1 1 1 0

1 0 0 0 1 1 1 1

Table 1: Truth Table of Gray to BCD Code Converter

BOOLEAN EXPRESSIONS:

B3=G3

B2=G3 ⊕ G2

B1=G3 ⊕ G2 ⊕ G1

B0=G3 ⊕ G2 ⊕ G1 ⊕ G0

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PROCEDURE:

1. Make connections as shown in Figure1.

2. Apply various combinations of G3, G2, G1, and G0 using logic input switches.

3. Connect the output of the gates to the Seven Segment Display.

4. Once all connections have been done, turn on the power switch of the Digital IC Trainer.

5. Verify the Truth Table given in Table 1.

OBSERVATIONS:

Verify and note down the outputs for each input combination of Table 1.

II) 4-line to 2-line Priority Encoder.

BRIEF THEORY:

A priority encoder is an encoder that includes the priority function. If two or more inputs are equal

to 1 at the same time, the input having the highest priority will take precedence.

Applications of Priority Encoder: Priority encoders are used to select the inputs with highest

priority in many practical applications. This process of selection is called arbitration. One of the

most common examples of arbitration is in computer system in which there are numerous input

devices and several of these devices attempt to supply the data to the computer simultaneously, a

priority encoder in that case enables the input device having the highest priority among those

devices trying to access the computer at the same time.

Table 2: Truth Table of a 4-Input Priority Encoder

INPUTS OUTPUTS

D0 D1 D2 D3 x y V

0 0 0 0 x x 0

1 0 0 0 0 0 1

x 1 0 0 0 1 1

x x 1 0 1 0 1

x x x 1 1 1 1

17

Design of 4-Input Priority Encoder (4-line-to 2 line priority encoder):

In addition to two outputs x, and y, the truth table has a third output designated by V, which

is a valid bit indicator that is set 1 when one or more inputs are equal to 1. If all inputs are

0, there is no valid input and V is equal to 0.

X’s in the output column indicate don’t care conditions; the X’s in the input columns are

useful for representing a truth table in condensed form.

The higher the subscript number, the higher the priority of the input. Input D3 has the

highest priority, so regardless of the values of the other inputs, when this input is 1, the

output for xy is 11 (binary 3).

K-Maps for 4-input Priority Encoder

V=D0+D1+D2+D3

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Figure 2: Logic Diagram for 4-input priority encoder

PROCEDURE:

1. Make connections as shown in Figure 2.

2. Apply various combinations of D3 D2 D1 D0 using logic input switches.

3. Connect the output of the gates to the output LEDs.

4. Verify the Truth Table given in Table 2.

OBSERVATIONS:

Verify and note down the outputs for each input combination of Table 2.

REFERENCES:

1. Mano, M. M., ″Digital Logic and Computer Design″, PHI, 1989, 3rd Edition.

2. Ronald J. Tocci, ″Digital Systems – Principles and Applications″, PHI, 1995.

19

EXPERIMENT NO. 3

OBJECT:

To test a 4-bit programmable adder/subtracted.

EQUIPMENT/APPARATUS USED:

S. No. Name of the equipment Range/Rating Make

1. Digital IC Trainer .... ....

2. 4-bit adder/sub tractor (7483) ... ...

3. EX-OR gates (7486)

4. CMOS (CD4007)

5. ...... … ….

BRIEF THEORY:

Since digital systems deals with numbers and codes, the need of performing mathematical

operations is paramount. The addition and subtraction are simplest arithmetic operations. A half

adder is the fundamental block used for addition. It performs the binary addition on two bits, and

gives the output in sum and carry form. The addition of two multi-digit binary number is performed

serially, one column at a time from right to left. When two bits in a column are added, it is

necessary that the carry from addition in previous column is also added. The circuit for adding one

such column is called full adder, which can be designed by using two half adder and an OR gate.

IC-7483 performs addition of two 4-bit binary numbers, which can also be used as a sub tractor

(using concept of 2’s complement addition). Fig 2 shows the circuit for addition. Fig 3 shows the

circuit for subtraction.

IC-7483 may be programmed as adder as well as sub tractor, using EX-OR gates. Figure 1 shows

the pin diagram of IC-7483. A4 A3 A2 A1 bits are directly applied as one set of inputs. B4 B3 B2 B1

bits are applied through EX-OR gates as another set of inputs. All other inputs of each EX-OR

gate are shorted to ADD/SUB control input. When ADD/SUB = 0, B4 B3 B2 B1 input bits are

passed through EX-OR gate (Table 1) and added with A4 A3 A2 A1 bits. When ADD/SUB = 1, B4

B3 B2 B1 bits are inverted at the output of EX-OR gate (Table 1), giving 1’s complement of these

bits. Addition of 1 at C0 with these bits (B4 B3 B2 B1) gives 2’s complement of B4 B3 B2B1 (Fig 3

& 4), hence, circuit of (Fig 4) acts as a sub tractor.

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Figure 1. Pin diagram of 4 bit adder (IC-7483)

Logic Diagram:

FA4 FA3 FA2 FA1

A4 A3 A2 A1

B4 B3 B2 B1

C0 = 0 C1C2C3C4

S1S2S3S4

Other

input of

X-OR

Gates

21

Figure. 2: 4 bit adder

FA4 FA3 FA2 FA1

A4 A3 A2 A1

B4 B3 B2 B1

C0 = 1 C1C2C3C4

S1S2S3S4

Other

input of

X-OR

Gates

Figure 3: 4 bit subtractor

Figure 4: Four bit adder/subtractor using IC-7483 and EX-OR gates (IC-7486)

22

PROCEDURE:

1. Connect the circuit as shown in Figure 4.

2. Select ADD/SUB (C0) = 0 for adder and 1 for subtractor.

3. Apply various combinations of A4 A3 A2 A1 and B4 B3 B2 B1 using logic input switches.

4. Verify addition/subtraction operation for different combinations of input bits A4 A3 A2 A1

and B4 B3 B2 B1and form a truth table for C4S4 S3 S2 S1.

5. Also verify operation of subtraction for [A4 A3 A2 A1] > [B4 B3 B2 B1] as well as [A4

A3 A2 A1] < [B4 B3 B2 B1] to obtain the result in 2′s complement.

OBSERVATION:

For 4-bit adder:

ADD/SUB (C0) = 0

A4 A3 A2 A1 B4 B3 B2 B1 C4S4S3S2S1

For 4-bit subtractor:

for both [A4 A3 A2 A1] > [B4 B3 B2 B1] &[A4 A3 A2 A1] < [B4 B3 B2 B1]

ADD/SUB (C0) = 1

A4 A3 A2 A1 B4 B3 B2 B1 C4S4S3S2S1

REFERENCES:

1. Mano, M. M., and M. D. Ciletti, ″Digital Design with an Introduction to Verilog HDL″,

Pearson, 2013, 5th Edition.

2. R. J. Tocci, N Widmer, and G. L. Moss, ″Digital Systems, Principles and Applications″,

Pearson, 10th Edition, 2013.

3. Millman, and Grabel, A., ″Microelectronics″, New York: Mc Graw Hill, 2nd Edition,

2010.

23

EXPERIMENT NO. 4

OBJECT:

To test an 8-line-to-1-line multiplexer and using it implement a given 4-variable logical function.

EQUIPMENT/APPARATUS USED:

S. No. Name of the equipment Range/Rating Make

1. Digital IC Trainer .... IC 74151

2. …. ….. …..

BRIEF THEORY:

Multiplexing is transmitting a large number of signals over a smaller number of channels or lines.

A digital multiplexer is a combinational circuit that selects binary information from one of the

many input lines and directs its binary information to a single output line. The selection of a

particular input is controlled by a set of selection lines. Normally there are 2n input lines and n

selection lines whose bit combinations determine which input is selected.

BLOCK DIAGRAM:

Figure 1: 8:1 multiplexer.

24

Figure 2: Pin diagram

Table 1: Truth Table

Input Output

Select Y Y′

S2 S1 S0 Enable

x x x 1 0 1

0 0 0 0 D0 D0′

0 0 1 0 D1 D1′

0 1 0 0 D2 D2′

0 1 1 0 D3 D3′

1 0 0 0 D4 D4′

1 0 1 0 D5 D5′

1 1 0 0 D6 D6′

1 1 1 0 D7 D7′

PROCEDURE:

(a) Apply select input code one by one from 000 to 111 at select input lines S2,S1,S0 and verify

that the data (1/0) corresponding to each input lines from D0 to D7 is transmitted to output line Y,

as shown in table1.

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Example: S2 S1 S0 = 010 code which corresponds to D2 input data line. Now apply D2 =0/1, this

data 0/1 is transmitted to Y.

(b) First express the function in the sum of min-terms form e.g. F(A,B,C,D) = Σ(0,1,3,4,8,9,15),

where A is MSB and D is LSB. Connect three variables B, C, D to the selection lines of the

multiplexer with B connected to the highest order selection line S2 and the last variable D is

connected to the lowest order selection line S0. Consider now the single variable A, since this

variable is in the highest order position in the sequence of variables it will be complemented in the

min-terms 0 to 7 which comprise the first half in the list of min-terms. The second half of the min-

terms 8 to 15 will have their A variable uncompleted as shown in observation table (Table3).

List all the inputs of the multiplexer and under them list all the min-terms in the two rows.

The first row lists all those min-terms where A is complimented and the second row all the min

terms with un-complimented as shown in Table 2. Circle all min-terms. Of the function and

inspect each column separately.

1. If the two min-term in a column is not circled apply 0 to the corresponding multiplexer input.

2. If the two min-terms are circled, apply 1 to the corresponding multiplexer input.

3. If the bottom min-term is circled the top is not circled, Apply A to the corresponding multiplexer

input.

4. If the top min-term is circled and the bottom is not circled, apply A′ to the corresponding

multiplexer input.

Example: Implement the following function: F(A,B,C,D) = Σ (0,1,3,4,8,9,15).

Table2:

Figure 3

D0 D1 D2 D3 D4 D5 D6 D7

A’ 0 1 2 3 4 5 6 7

A 8 9 10 11 12 13 14 15

1 1 0 A’ A’ 0 0 A

26

OBSERVATIONS:

Truth table of the function:

Table 3:

A B C D F(A,B,C,D)

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

REFERENCES:

1. R. J. Tocci, N Widmer, and G. L. Moss, ″Digital Systems, Principles and Applications″,

Pearson, 10th Edition, 2013.

27

EXPERIMENT NO. 5

OBJECT:

To verify the truth table of the following types of Latches and Flip Flops with control inputs

(a) R-S (b) D (c) T (d) J-K

EQUIPMENT/APPARATUS USED:

S. No. Name of the equipment Range/Rating Make

1. Digital IC Trainer .... IC 74151

2. ... ... ...

BRIEF THEORY:

The SR Latch/FF is a basic flip-flop made with logic diagram as shown in figure 1. It has two

inputs S (SET) and R (RESET), and it has two outputs Q and Q’.

Figure 1: Logic diagram SR Latch/FF

PROCEDURE:

1. Construct the logic as shown in Figure 1 and connect the two input switches and the two outputs

to the indicator lamps.

2. Set the two switches to LOGIC-1, then momentarily turn each switch separately to the LOGIC-

0 position and back to the 1.

3. Obtain the Truth-Table of the circuit.

28

OBSERVATIONS:

Clock S R Q Q′ Comments

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Table 1: Truth-table SR Latch/FF

BRIEF THEORY:

A D-type latch/FF has a single data input in addition to the clock input as shown in figure 2. This

kind of flip flop prevents the value of D from reaching the output until a clock pulse occurs. The

action of circuit is as follows.

When the clock is low, both the AND gates are disabled, therefore D can change values without

affecting the value of Q. On the other hand when clock is high, both AND gates are enabled. In

this case, Q is forced equal to D when the clock again goes low, Q retains or stores the last value

of D.

Figure 2: D-Latch/FF

PROCEDURE:

1. Connect the circuit as shown in figure 2 and connect the input switch and the two outputs to

the indicator lamps.

2. Set the switches to LOGIC-1, then momentarily turn each switch separately to the LOGIC-0

position and back to the 1.

3. Obtain the Truth-Table of the circuit.

29

OBSERVATIONS:

Clock D Q Q′ Comments

0 0

0 1

1 0

1 1

Table 1: Truth-table D Latch/FF

BRIEF THEORY:

The J-K latch/flip-flop is the most versatile of the basic flip-flops. It has two inputs, traditionally

labeled J and K. If J and K are different then the output Q takes the value of J at the next clock

edge. If J and K are both low then no change occurs.

Figure 3: JK Latch diagram

Figure 4: JK Flip Flop diagram

30

PROCEDURE:

1. Connect the circuit as shown in Figure 4

2. Obtain the Truth-Table of the circuit.

OBSERVATIONS:

Inputs Output

PRE CLR CLK J K

0 0 x x x

0 1 x x x

1 0 x x x

1 1 x 0 0

1 1 1 0 1

1 1 1 1 0

1 1 1 1 1

Table 3: Truth table JK latch/FF

BRIEF THEORY:

A method of avoiding the indeterminate state found in the working of RS flip flop is to provide

only one input (the T input). Such flip flop acts as a toggle switch. Toggle means to change in the

previous state i.e. switch to opposite state.

Figure 5: Circuit Diagram T-Latch/FF

PROCEDURE:

1. Implement the circuit as shown in Figure 5.

2. Obtain the truth table for the above diagram.

31

OBSERVATIONS:

Clock T Q Q′ Comments

0 0

0 1

1 0

1 1

Table 4: Truth table T-latch/FF

REFERENCES:

1. R. J. Tocci, N Widmer, and G. L. Moss, ″Digital Systems, Principles and Applications″,

Pearson, 10th Edition, 2013.

32

EXPERIMENT NO. 6

OBJECTIVE:

To design and implement the circuit of MOD-8 asynchronous and MOD-6 synchronous counters

using J-K flip-flops.

EQUIPMENT/APPARATUS USED:

S. No. Name of the equipment Range/Rating Make

1. Digital IC Trainer .... IC 74151

2. ... ... ...

I) Mod-8 Asynchronous Counter

BRIEF THEORY:

Digital counters are sequential building blocks made by cascading flip-flops (FF) together. These

versatile units count the number of pulses arriving at its clock input. It counts in terms of binary

numbers.

Asynchronous/ripple counters are constructed in such a way that the count pulses in effect ripple

through FF chain. The output of first FF is the clock input to the second. Any state change in 2nd

FF occurs, after 1st FF changes its state. This continues down the chain. A 3 bit (modulo-8) counter

is shown in Fig. 1 and its transition table in table 1.

LOGIC DIAGRAM:

J

K

CLK

Q

Q

1

J

K

CLK

Q

Q

1

J

K

CLK

Q

Q

1

Clock

pulse

1

Q0Q1Q2

FF0FF1FF2

PR CL PR CL PR CL

Figure 1 (a): A 3 bit (MOD-8) ripple counter

33

1 2 3 4 5 6 7 8

CLOCK

Q0

Q1

Q2

000 001 010 011 100 101 110 111 000

01

1

11

1 1 1

1 1

1 1 1

0

0

0

0

00

0

0

0 0

00

0

0

Figure 1 (b): Timing Diagram of 3 bit ripple counter

Table 1:

No. of clock pulses input to FF0 Q2 Q1 Q0

0 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1

4 1 0 0

5 1 0 1

6 1 1 0

7 1 1 1

8 0 0 0

34

PROCEDURE:

1. Make connections as shown in Figure 1 (a). The JK FFs are converted to T FFs by connecting

JK inputs of all FFs to 1. Connect a pulser switch to the clock input to flip-flop FF0. Q0 goes

to clock input of FF1 and Q1 goes to clock input of FF2 and so on.

2. Put CL and PR high by means of logic input switches.

3. Apply the clock of pulses through the pulser switch to the clock input of FF0.

4. Verify the count sequences of Table 1.

OBSERVATIONS:

Verify and note down the count sequence for each clock input given in Table 1.

II) MOD-6 Synchronous Counter:

BRIEF THEORY:

In synchronous counter, all FFs are controlled by common clock input. Here all FF changes states

simultaneously.

LOGIC DIAGRAM:

J

K

CLK

Q

Q

J

K

CLK

Q

Q

J

K

CLK

Q

Q

1

Clock

Input

Q2

Q2

Q1

Q0

FF0FF1FF2

Q1

Q0

Q2

Q0

Q1

Q0

Figure 2: MOD-6 Synchronous Counter

DESIGN:

Number of FFs required = 3 (since 23 > 6)

35

Qn Qn+1 J K

0 0 0 x

0 1 1 x

1 0 x 1

1 1 x 0

Table 2: Excitation Table of JK FF

Qn: Present state, Qn+1: Next state, x: don′t care

Present State Next State Flip-flop inputs

Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 K0 K0

0 0 0 0 0 1 0 x 0 x 1 x

0 0 1 0 1 0 0 x 1 x x 1

0 1 0 0 1 1 0 x x 0 1 x

0 1 1 1 0 0 1 x x 1 x 1

1 0 0 1 0 1 x 0 0 x 1 x

1 0 1 0 0 0 x 1 0 x x 1

Table 3. Excitation Table of MOD-6 synchronous counter

K-map is used to obtain the expression for Ji and Ki in terms of Q2 Q1Q0.

Note: The states 110, 111 are not valid states for Mod-6 counter, hence considered as don’t care.

36

No. of clock pulses Outputs

Q2 Q1 Q0

0 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1

4 1 0 0

5 1 0 1

6 0 0 0

Table 4: Output sequence of MOD-6 Synchronous counter

PROCEDURE:

1. Make connections as shown in Figure 2.

2. Clear all the FFs.

3. Apply clock pulse and verify the count sequences for MOD-6 synchronous counter.

OBSERVATIONS:

Verify and note down the count sequence for each clock input given in Table 4.

REFERENCES:

1. R. J. Tocci, N Widmer, and G. L. Moss, ″Digital Systems, Principles and Applications″,

Pearson, 10th Edition, 2013.

2. Mano, M. M., ″Digital Logic and Computer Design″, PHI, 1989, 3rd Edition.

3. Millman, and Grabel, A., ″Microelectronics″, New York: Mc Graw Hill, 2nd Edition, 2010.

37

EXPERIMENT NO. 7

OBJECT:

Study and verify the load, shift and rotate operation of a 4-bit shift register.

EQUIPMENT/APPARATUS USED:

S. No. Name of the equipment Range/Rating Make

1. Digital IC Trainer .... IC 74151

2. IC 74195 ... ...

3. ... ... ...

BRIEF THEORY:

A register is a group of binary storage cells capable of holding binary information. A group of flip

flops constitutes a register, since each flip-flop can work as a binary cell. An n-bit register, has n

flip-flops and is capable of holding n-bits of information. In addition to flip-flops a register can

have a combinational part that performs data-processing tasks.

Shift Register: A register capable of shifting its binary contents either to the left or to the right is

called a shift register. The shift register permits the stored data to move from a particular location

to some other location within the register. Registers can be designed using discrete flip-flops (S-

R, J-K, and D-type). The data in a shift register can be shifted in two possible ways: (a) serial

shifting and (b) parallel shifting. The serial shifting method shifts one bit at a time for each clock

pulse in a serial manner, beginning with either LSB or MSB. On the other hand, in parallel shifting

operation, all the data (input or output) gets shifted simultaneously during a single clock pulse.

Hence, we may say that parallel shifting operation is much faster than serial shifting operation.

8-bit Universal Shift Register: IC 74195 is a 4-bit TTL MSI having both serial/parallel input and

serial/parallel output capability. The pinout diagram of IC 74195 is shown in Figure 1.

Figure 1: Pin diagram of IC 74195.

38

When the SH / LD input is LOW, the data on the parallel inputs, i.e., A, B, C, and D are entered

synchronously on the positive transition of the clock. When SH / LD is HIGH, the stored data will

shift right (QA to QD) synchronously with the clock. J and K are the serial inputs to the first stage

of the register (QA); QD can be used for getting a serial output data. The active low clear is

asynchronous.

39

Example:

Right Shift Operation

Input data: 1011

Clock QA QB QC QD

0 1 0 1 1

1 0 1 0 1

2 0 0 1 0

3 0 0 0 1

4 0 0 0 0

1 0 0 1 1 0 0 1

0 1 0 0 1 1 0 0

PROCEDURE:

1. Load data using parallel loading

2. Use clock 1(9)

3. Mode Control 6 OFF (0) connect logic input switch

4. Serial input 1 OFF (0) connect logic input switch

5. Press the clock button

Example:

Rotate Right Operation:

Input data: 1011

Clock QA QB QC QD

0 1 0 1 1

1 1 1 0 1

40

2 1 1 1 0

3 0 1 1 1

4 1 0 1 1

1 0 1 1 0 0 0 1

PROCEDURE:

1. Load data using parallel loading

2. Use clock 1(9)

3. Mode Control 6 OFF (0) connect logic input switch

4. Serial input 1 connects to the QD logic output switch

5. Press the clock button

REFERENCES:

1. R. J. Tocci, N Widmer, and G. L. Moss, ″Digital Systems, Principles and Applications″,

Pearson, 10th Edition, 2013.

41

EXPERIMENT NO. 8

OBJECT:

To design and test a 4-bit R-2R ladder type DAC.

BRIEF THEORY:

Operation of the R-2R ladder is straight forward. First, it can be shown by starting from the right

and working toward the left, that the resistance to the right of each ladder node is equal to 2R.

Thus the current flowing to the right, away from each node, is equal to the current flowing

downward to ground and twice those current flows into the node from the left side.

CIRCUIT DIAGRAM:

For the above circuit b4 is the MSB and b1 is the LSB.

The output Vo is given as: Vo= -ioRf

For io, the expression is given by

io = Vref

K1 b4 +

Vref

K2 b3 +

Vref

K3 b2 +

Vref

K4 b1

(Derive the expressions of K1, K2, K3, and K4 before reporting to the Lab)

42

The maximum value of output is obtained at b4b3b2b1= [1 1 1 1], for which D is 15

|V0|max = io max Rf = Vref

R(

15

16) Rf

Figure 2: Pin Diagram of 741 IC

OBSERVATIONS:

Set [b4 b3 b2 b1] = [0000]…….. [1111] and, measure the voltage Vo present the result in tabular

form. Also calculate the voltage change in the output for ONE 0-1 transition of B1.

Take Rf = R = 1kΩ and Vref = 8 to 15 V.

Binary input Output Percentage error

calculation

b4 b3 b2 b1 Vo

Theoretical

Vo

Practical

0 0 0 0

. . . .

. . . .

. . . .

. . . .

. . . .

1 1 1 1

REFERENCES:

1. R. J. Tocci, N Widmer, and G. L. Moss, ″Digital Systems, Principles and Applications″,

Pearson, 10th Edition, 2013.

2. Millman, and Grabel, A., ″Microelectronics″, New York: Mc Graw Hill, 2nd Edition, 2010.