Lab Assignment No 4

7/29/2019 Lab Assignment No 4

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COMPUTER ORGANIZATION

FULL ADDER AND 4-BIT ADDER BY

INSTANTIATION

Submitted to : TAHIR MUHAMMAD

Submitted by : ahmad

Registration No. :

Group : C1

DEPARTMENT OF ELECTRICAL ENGINEERING.



Lab Assignment No.2

Task -1:

1. Write verilog code for SR Latch as shown in figure 1.2. Write a test bench to verify the design.

VERILOG CODE:

modulesr_latch(Q,R,s,c,r);//interface of SR Latch

//declaration of ports

inputs,c,r;

output Q,R;

wire w1,w2;

//gate level modeling

nand g1(w1,c,s);

nand g2(w2,c,r);

nand g3(Q,w1,R);

nand g4(R,w2,Q);



endmodule

//test bench of SR Latch

moduletestSR_Latch();

//declaration of ports in test bench

regs,c,r;

wire Q,R;

//calling of SR Latch module

sr_latchg5(Q,R,s,c,r);

//initialization of inputs

initial

begin

c=0; s=0; r=1;

#10 c=0; s=1; r=0;

#10 c=1; s=0; r=1;#10 c=1; s=1; r=0;

#10 c=1; s=0; r=0;

#10 c=1; s=1; r=1;

#10 $stop;

end

endmodule



WAVE-FORM:



TASK-2:

1. Write Verilog code for D flip flop using Master/Slave latches as shown in

figure2.2. Write a test bench to verify the design

VERILOG CODE:

modulesr_latch(Q,R,s,c,r); //interface of SR Latch


inputs,c,r;

output Q,R;

wire w1,w2;


nand g1(w1,c,s);

nand g2(w2,c,r);

nand g3(Q,w1,R);

nand g4(R,w2,Q);

endmodule

moduleD_latch(Q,R,c,d); //interface of D Latch




inputc,d;

output Q,R;

wire w1,w2,w0;


not g0(w0,d);

nand g1(w1,c,d);

nand g2(w2,c,w0);

nand g3(Q,w1,R);

nand g4(R,w2,Q);

endmodule

module M_S_LATCH(Q,R,d,c);//interface of Master Slave Latch


inputd,c;output Q,R;

wire w0,w1,w2;

not g1(w0,c);

D_latchg3(w1,w2,w0,d);//instantiation of D_Latch

sr_latchg2(Q,R,w1,c,w2);//instantiation of SR_Latch

endmodule

//interface of test bench of Master Slave Latch

moduletestM_S_LATCH();

regd,c;



wire Q,R;

M_S_LATCH g4(Q,R,d,c);//instantiation of M_S_Latch

initial

begin

c=0; d=1;

#10 c=1;

#10 c=0; d=0;

#10 c=1;

end

endmodule

WAVE-FORM:



Task 3:

Write a Gate‐level code for figure3 JK Flip-flop .

Verilog Code:

modulejkflipflop(Q,Qnot,j,k,clk); // declaration of module with port list

inputj,k,clk; //deceleration of inputs & outputs

outputQ,Qnot;

wire w1,w2,w3,w4,w5,w6,w7; //wire used for in out


not g1(w7,clk);

nand gj1(w1,j,clk);

nand gj2(w2,k,clk);

nand gj3(w3,w1,Qnot);

nand gj4(w4,w2,Q);



SRlatchmaster(w5,w6,w3,w4,w7); //Module of SR latch is called as Master

SRlatchslave(Q,Qnot,w5,w6,clk); //Module of SR latch is called again to form

endmodule

moduleSRlatch(Q,Qn,s,c,r); // Complete module of SR latch

inputs,c,r;

outputQ,Qn;

wire w1,w2;


nand g1(w1,s,c);

nand g2(w2,r,c);

nand g3(Q,w1,Qn);

nand g4(Qn,w2,Q);

endmodule

module test();regj,k,clk;

wireQ,Qnot;

jkflipflophj(Q,Qnot,j,k,clk); /*insanitation of JK Flip-flop*/

initial

clk=0;

always//always key word to generate clock

#5 clk=~clk;

initial

begin



j=0;k=0;

#10 j=0;k=1;

#10 j=1;k=0;

#10 j=1;k=1;

#10 j=0; k=0;

end

endmodule

Wave-form:



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Lab Assignment No 4