Lab 14/D1: Logic Gates Contents

Chapter 14L

Lab 14/D1: Logic Gates

Contents

14LLab 14/D1: Logic Gates 114L.1Preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

14L.1.1Logic Probe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214L.1.2LED Indicators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314L.1.3Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

14L.2Input & Output Characteristics of Integrated Gates: TTL & CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514L.3Pathologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

14L.3.1Floating Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614L.3.2Effect of failing to connect power or ground to CMOS logic gate . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

14L.4Applying IC Gates to Generate Particular Logic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814L.4.1NAND Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814L.4.2Digital Comparators, using any gates you like . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

14L.5Two Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914L.5.1Passive Pullup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 914L.5.2Active Pullup: CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

14L.6Logic Functions from CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1114L.6.1CMOS NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1114L.6.2CMOS Three-State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

REV 11; October 5, 2014.Time: Total time:1:55 (1 hr, 55 min)

The first part of this lab invites you to try integrated gates, black boxes that work quite well, to carry out someBoolean logic operations.

The later sections of the lab ask you to look within the black box, in effect, by putting together a logic gatefrom transistors. Here, the point is to appreciate why the IC gates are designed as they are, and to notice some

1Revisions: insert one Ray redraw (10/14); add headerfile and index (6/14); add DIP switch wiring detail (1/11); add note warningthat only some 74HC00’s perform XOR when not powered (10/10); remove “peeping” and “wink,” words that offended Paul (2/06).

1

2 Lab 14/D1: Logic Gates

of the properties of the input and output stages of CMOS gates. We will concentrate in this lab, as we willthroughout the course, on CMOS. To overstate the point slightly, we might say that we will treat ordinaryTTL as a venerable antique.

But all of the work we do in this lab is rather antique—because logic now is seldom done with little packagesof a few gates. Normally, logic networks are built from large arrays of gates that are programmed to carry outa particular function. Soon you will be taking advantage of a modest version of such devices (1600 gates ina package). But, today, we’ll use just one or a few gates at a time because that’s a good way to start getting agrip on what a gate does.

14L.1 PreliminaryTime: 10 min.

Some ground rules in using logic:

1. Never apply a signal beyond the power supplies of any chip. For the logic gates that we use, thatmeans. . .

2. . . . keep signals between 0 and + 5 volts. (This rule, in its general form—‘stay between the supplies’—applies to analog circuits as well; what may be new to you is the nearly-universal use of single supplyin digital circuits.)

3. Power all your circuits from +5v. and ground only—until we reach the CPLD’s2or “PALs,”3 some ofwhich are powered with 3.3V instead. This applies equally to CMOS (in its traditional 5-volt form4)and to TTL. Power and ground pins on ordinary digital parts (not complex IC’s like PALs and micro-controllers) are the diagonally-opposite corner pins:

Figure 1: Ordinary digital parts take power and ground at their corner pins

14L.1.1 Logic Probe

The logic probe is a gizmo about the size of a thin hot dog, with a cord on one end and a sharp point on theother. It tells you what logic level it sees at its point; in return, it wants to be given power (+5v and ground)at the end of its cord. (N.b., the logic probe does NOT feed a signal to the oscilloscope!)

If you find a BNC connector on the probe cord, connect +5V to the center conductor, using one of thebreadboard jacks. If, instead, you find that the cord ends with alligator clips or a pair of strange-lookinggrabbers, use these to take hold of ground and +5.

2Complex Progammable Logic Devices, first mentioned in today’s classnotes.3Programmable Array Logic, as you may recall.4Lower supply voltages are widely displacing 5V. 3.3V, 2.5V and 1.8V are common supplies, at date of this writing. For the most

part we will use 5-volt logic.

Lab 14/D1: Logic Gates 3

How to Use the Probe

Most logic probes use different-colored LED’s to distinguish High from Low—and to distinguish both from“float” (simply “not driven at all; not connected”). This ability of the probe is extremely useful. (Could avoltmeter or oscilloscope make this distinction for you?5)

Use the probe to look at the output of the breadboard function generator when it is set to TTL. Crank thefrequency up to a few kilohertz. Does the probe blink at the frequency of the signal it is watching? Whynot?6

14L.1.2 LED Indicators

The eight LED‘s on the breadboard are buffered by logic gates. You can turn on an LED with a logic high,and the gate presents a conveniently high input impedance (100k to ground).

In order to appreciate what the logic probe did for you earlier, try looking at a fast square wave, using one ofthese LED’s rather than the logic probe: use the breadboard oscillator (TTL) at a kilohertz or so. Does whatyou see make sense? You may now recognize that the logic probe stretches short pulses to make them visibleto our sluggish eyes: it turns even a 30 ns pulse into a flash of about one-tenth of a second (the faster probescan do this trick with even narrower pulses).

14L.1.3 Switches

14L.1.3.1 Switches Available on the Powered Breadboards

The PB503 includes three sorts of switch on its front panel:

• two debounced pushbuttons (over on the left, marked PB1, PB2) These deliver an open collector output, and that means thatthey are capable of pulling to ground only, never to the positive supply. To let such an output go to a logic high, you will need toadd a pullup resistor, to 5V:

Figure 2: Pullup required on open-collector output (debounced pushbuttons on PB503)

Note that what looks like a discrete transistor in the drawing is included on the breadboard; you need add only the pullup resistor.

• an 8-position DIP switch, fed from a +5V/0V slide switch (marked DIP switch S1)

5No! The special virtue of the logic probe is the ability to distinguish a logic LOW from the plain old “zero volts” that a DVM mightshow you. The DVM cannot distinguish a float—no connection to anything—from a good solid connection to ground, which the logicprobe understands is what we mean by Low.

6Why not? Because your eyes are not quick enough to see a 1KHz blink rate (you probably can’t notice a blink rate beyond about 25Hz). The logic probe slows fast switching to the lazy rate of a few Hz, so that we humans can see it.


Figure 3: DIP switch in-line with output of onecommon slide switchThis looks as if it could give you 8 independent outputs, but it cannot; at least, not conveniently. The DIP switch on mostbreadboards is simply an in-line switch that delivers the level set by the slide switch, if closed—and nothing (a float: neither highnor low) if the DIP switch is open. To get 8 independent levels you need 8 pullup resistors, while setting the slide switch alwaysLow. That’s a nuisance, so most of the time you’ll probably want to use this 8-position switch to provide just one logic level. Toget that, close the DIP switch; to avoid fooling yourself later, probably it’s a good idea to leave all the DIP’s switches closed.

• two uncommitted slide switches (SPDT) These are on the lower right, and are bouncy (not debounced, anyway). To make themuseful, tie one end to ground, the other to +5, and use the common terminal as output. You might as well wire these now, usethem today, and then leave them so wired for use in later labs.

14L.1.3.2 A Good Way to Generate Digital Inputs

An easy way to provide levels where you want them is to wire a DIP switch so that one side ties directly tothe ground bus:

Figure 4: DIP switch installed on breadboard can provide logic levels

The DIP switch should be inserted upside-down, so that the slider down position (which looks like a Low)generates a logic Low. The switch shown is providing a 00 combination.

If the switch is wired directly to an IC’s inputs, the pullups may have to run sideways:

Figure 5: DIP switch can provide logic levels just where you want them

Again, the switch is shown providing a 00 combination, this time going to the two inputs of a NAND gate, ina 74HC00.


A. Applying Integrated Gates

14L.2 Input & Output Characteristics of Integrated Gates: TTL &CMOS

Output Voltage Levels:Time: 10 min.

Power and Ground

As we suggested back in § 14L.1 on page 2, a 14-pin DIP like the ones you meet in this lab takes power andground at its corner pins: Northwest and Southeast, pins 14 (VCC: +5V) and 7 (ground).

Input Signals

Use a DIP switch or other source to provide 0 or +5 v to the two inputs of a NAND gates, driving bothTTL and CMOS, simultaneously. If you want to be really fancy and lazy, show the two inputs on two of thepowered-breadboards LED’s, and the output on a third LED. Doing that helps you to see inputs and outputssimultaneously, as if you were looking at one line of a truth table.

74XX00 pinout:

Figure 6: NAND gates: TTL & CMOSThe TTL part is 74LS00.7

The CMOS part is 74HC00.8

Note: for the CMOS part (but not TTL), tie all the six unused input lines to a common line, and temporarilyground that line. Take the trouble to tie the unused inputs together, rather than ground each separately, becausesoon we will want to drive them with a common signal (in § 14L.3.1.2 on the next page)).

Now note both logic and voltage levels out, as you apply the four input combinations. (Only one logic-outcolumn is provided, below, because here TTL and CMOS should agree.) As load, use a 10k resistor toground.

INPUT OUTPUTLogic Levels Volts: TTL Volts: CMOS

0 00 11 01 1

7“LS” stands for “low power Schottky,” a process that speeds up switching. At the time when this LS prefix was chosen (1976) TTLwas thought to go without saying; thus there’s no T in the designation, in contrast to CMOS, the late-bloomer, which always announcesitself with a C somewhere in its prefix: HC, HCT, AC, ACT, etc. See the 74HC00, just below. )

8The “74” shows that the part follows the part-numbering and pinout scheme established by the dominant logic family, Texas In-struments’ 74xx TTL series; “C” indicates CMOS; “H” stands for “high speed”: speed equal to that of the then-dominant TTL family,74LS.


14L.3 Pathologies

14L.3.1 Floating InputsTime: 15 min.

14L.3.1.1 TTL

Disconnect both inputs to the NAND, and note the output logic level (henceforth we will not worry aboutoutput voltages; just logic levels will do). What input does the TTL “think” it sees, therefore, when its inputfloats?9

14L.3.1.2 CMOSAoE §10.8.3.2

Here the story is more complicated, so we will run the experiment in two stages:

1- Floating Input: effective logic level in:

Tie HIGH one input to the NAND, tie the other to 6 inches or so of wire; leave the end of that wire floating,and watch the gate’s output with a logic probe or scope as you hold your hand near the floating-input wire,or take hold of it at an insulated section. (Here you are repeating an experiment you did with the powerMOSFET a few labs back.) Try touching your other hand to + 5 v., to ground, to the TTL oscillator output orhold your free hand near the transformer of the breadboard’s internal power supply. We hope that what yousee will convince you that floating CMOS inputs are less predictable than floating TTL inputs, although weurge you to leave no logic inputs floating.

2- Floating Input: Effect on CMOS power consumption:

You may have read that one should not leave unused CMOS inputs floating. Now we would like you to seewhy this rule is sound (though, like most rules, it deserves to be broken now and then10).

Figure 7: Test setup: applying intermediate input level raises power consumption

Tie the two NAND inputs to the other six, earlier grounded; disconnect the whole set from ground, andinstead connect it to a potentiometer that can deliver a voltage between 0 and +5v. Rotate the pot to one of itslimits, applying a good logic level input to all four of the NAND gates in the package.

9It thinks it sees a high—though a high that is vulnerable to noise. A look at the innards of the gate, shown in today’s class notes, inthe section “Gate Innards. . . ,” reveals the internal resistive pullup on the base of the first transistor. That transistor therefore is held on,when inputs are open, as if driven by a genuine High input.

10In particular, we don’t want you to feel obliged, when breadboarding circuits in this lab, to drive all unused inputs. That’s requiredin a circuit that you build in permanent form, but your lab time is more valuable than the extra power that your circuit may consumewhen inputs are left floating—and your time is more valuable even than the IC that conceivably might be damaged by your failure todrive all its unused inputs.


Now (with power off) insert a current meter (VOM or DVM) between the +5v supply and the V+ pin (14) onthe CMOS chip. Restore power and watch the chip’s supply current on the meter’s most sensitive scale. Thechip should show you that it is using very little current: low power consumption is, of course, one of CMOS’great virtues.

Now switch the current meter to its 150 mA scale (or similar range) and gradually turn the pot so thatthe inputs to all four NAND gates move toward the threshold region where the gate output is not firmlyswitched high or low. Here, you are frustrating CMOS’ neat scheme that assures that one and only one of thetransistors in the output stage is on. When input voltage is close to VDD/2, the typical switching threshold,both transistors can be partially on. You can see on the current meter dial the price for this inelegance: powerconsumption thousands of times higher than normal.

Floating inputs thus are likely to cause a CMOS device to waste considerable power. Manufacturers warnthat this power use can also overheat and damage the device. In this course we will sometimes allow CMOSinputs to float while breadboarding, as we have said. But you now know that you should never do this in anycircuit that you build to keep.

14L.3.2 Effect of failing to connect power or ground to CMOS logic gateTime: 10 min.

Now we ask you to do, purposely, what students often do inadvertently,11 as they breadboard logic circuits:omit power and ground connections. The effect is not what one might expect. Perhaps you would expect anun-powered IC to deliver a constant Low output, or a Floating output.

But the protection clamps on input and output of each gate complicate the behavior. The clamps look likethis, for 74HC parts12:

VDDDD

VSSSS

INPUT

200 ΩCMOSGATE

OUTPUT

Figure 8: 74HC logic gate protection circuitry

The clamps allow inputs (and sometimes outputs) to provide current that can power the IC. So, a High inputcan feed the +5 supply line through the upper clamp diodes (though these don’t look connected); a Lowcan feed the ground line through the lower clamp diode—though both +5 and ground so driven would reachcompromised levels. So, if you apply both a high and a low to inputs somewhere on the chip, you havepowered the chip! As you can imagine, the result is a very strange pattern of misbehavior: everything seemsto be working—till an unlucky combination of input levels occurs.

If you let the output of 74HC00 NAND gate drive a 10k load resistor (other end tied to ground), and putthat output on one of the breadboard’s buffered LED’s (to make it easy for you to see the logic level out)you may see the HC00 NAND generating an XOR function. Why?13 We should confess we can’t promise

11You wouldn’t make this mistake—butmany others do. One term the error became so common in our class that the teaching assistantsbegan to distribute candy rewards to the students who did not make this error: who applied power and ground first, rather than postponethe chore till after they had wired the more interesting connections.

12Fairchild/National App. Note AN248.13The argument for XOR is that only this input combination provides both +5 and ground, and therefore makes the gate put out the

HIGH that a NAND ought to put out in response to a 01 or 10 input. 00 input provides no +5, so the gate cannot put out a high (as theNAND should). 11 is more problematic: the gate is not powered, but some 74HC00’s (Motorola’s, for example) put out a HIGH for thisinput, while others (National’s) put out a low. In neither case is the gate functioning. The HIGH from the Motorola chip seems to be


the XOR result: variations in protection circuitry among manufacturers make the outcome unpredictable: wefound National Semiconductor 74HC00’s follow this script, but Motorola 74HC00’s do not. But one rule isreliable: a CMOS gate that has not been powered will perform very strangely.

14L.4 Applying IC Gates to Generate Particular Logic Functions

Before we look into the gritty details of what lies within a logic IC, let’s have some fun with these gates.First, we’ll do three tasks with NAND’s, so as to get used to the remarkable fact that with NANDs you canbuild any logic function. Then we’ll invite you to apply any of the standard logic functions, including XOR,to make a digital comparator in two forms.

Most people prefer these brain teasers to a session of wiring. Don’t let these problems bring your lab work toa dead stop! Please don’t give any of these problems more than ten minutes of your precious lab time. Youcan always finish these brain teasers at home.

14L.4.1 NAND Applications Time: 15 min.

14L.4.1.1 1- “BOTH”

Use NANDs (CMOS or TTL) to light one of the breadboard’s buffered LEDs when both inputs are high.

NANDs to light an LED when both inputs are high (your design)

14L.4.1.2 2- “EITHER”

Use NANDs (CMOS or TTL) to light one of the LEDs when either of the inputs is low (here we mean a plainOR operation, not exclusive-or, by the way). (Trick question! Don’t work too hard.)

NANDs to light an LED when either input is low (your design)

14L.4.2 Digital Comparators, using any gates you likeTime: 20 min.—don’t let this gamegobble your after-noon!

14L.4.2.1 2-bit Equality Detector

Use any gates to make a comparator that detects equality between two 2-bit numbers. (This circuit, widened,is used a lot in computers, where a device often needs to watch the public “address bus,” so as to respondupon seeing its own distinctive “address.”)

Hint: the XOR function is a big help, here (XOR is 74HC86; pinout is same as for ’00: in fact, all 2-input74XX gates use the same pinout—except the oddball ’02, which is laid out backwards). You can think ofXOR as a 1-bit equality*/inequality detector.14

simply passed through, with the entire IC presumably hanging close to +5V.14This may be your first encounter with the convention that uses an asterisk (“equality*”) to indicate a signal that is active-low. The

same low/high meanings could be written with an overbar: “equality/inequality.”


2-bit equality detector: your design)

14L.4.2.2 2-bit A > B Detector

Use any gates to make a comparator that detects when one of a pair of two bit number (call it “A”) is largerthan the other (call it “B”). You need not make the circuit symmetrical: it need not detect B>A, only A>Bversus A not-greater-than B.

Warning: this circuit can get pretty complicated. We’d like to urge you, once again, not to use a lot of labtime on this problem. If you like this kind of game, and have not prepared a solution by lab time, maybe youshould postpone the task till you’re trying to fall asleep tonight.

B. Gate Innards: Looking Within the Black Box of CMOS Logic

In the following experiments, we will use two CD4007 (or CA3600) packages; this part is an array of com-plementary MOS transistors:

Figure 9: ’4007 (or “CA3600”) MOS transistor array

14L.5 Two InvertersTime: 15 min.

14L.5.1 Passive Pullup

Build the following circuit, using one of the MOSFETs in a ’4007 package. Be sure to tie the two “body”connections appropriately: pin 14 to +5V, pin 7 to ground. This will look familiar to you: it is one moreinstance of the convention we mentioned earlier, in § 14L.1 on page 2: corner pins carry power and ground.(In fact, you will find that this is automatic for the particular FETs in the package that we show below; butyou should be alert to this issue as you use MOSFETs.)

Figure 10: Simplest inverter: passive pullup

Confirm that this familiar circuit does invert, as you drive it with a TTL level from an external function


generator (the breadboard oscillator is too slow to make this circuit look really bad, as we soon will wantit to). The function generator’s “TTL” output provides a VOH that is not high enough to satisfy CMOS’spreference for a High of close to 5V (though TTL usually will make the CMOS gate switch).15 The usualremedy is to “pull up” the TTL output, with a resistor of a few kΩ to +5V.16 Watch the output on a scope(voltmeter or logic probe will not do, from this point on).

Now crank up the frequency as high as you can. Do you see what goes wrong, and why?17 Draw what thewaveform looks like:

Figure 11: Passive-pullup MOS inverter: at two frequencies

14L.5.2 Active Pullup: CMOS

Now replace the 10k resistor with a P-channel MOSFET, to build the following inverter:

Figure 12: Active pullup: CMOS inverter

Look at the output as you try high and low input frequencies.

The high-frequency waveform should reveal to you why all respectable logic gates use active pullup circuitsin their output stages. (The passive-pullup type, called open collector for TTL or open drain for MOS,appears now and then in special applications such as driving a load returned to a voltage other than the + 5vsupply, or letting several devices drive a single line. Usually that last case is better handled by a 3-state. See§ 14L.6.2 on the facing page.)

15If you don’t recall TTL’s VOH value, you might look again at the VOH numbers you got in § 14L.2 on page 5, above.16This pullup may work on your function generator; it did not work on ours (Krohn-Hite), because their outputs labelled “TTL” are

not true TTL: their TTL output cannot be pulled above 4V. A real TTL gate rises easily to +5v when pulled up. But 4V is sufficient todrive the CMOS gates.

17The rise is slow, because the usual stray capacitance is driven by the 10k pullup resistor, forming a lazy RC.


14L.6 Logic Functions from CMOS

14L.6.1 CMOS NANDTime: 10 min.

Build the circuit below, and confirm that it performs the NAND function.

Figure 13: CMOS NAND

14L.6.2 CMOS Three-StateTime: 15 min.

The three-state output stage can go into a third condition, besides High and Low: off. This ability is extremelyuseful in computers: it allows multiple drivers to share a single driven wire, or bus line. Here, you will builda buffer (a gate that does nothing except give a fresh start to a signal), and you will be able to switch its outputto the OFF state. It is a “three-state buffer.”

Figure 14: Three-state buffer: block diagram

The trick, you will recognize, is just to add some logic that can turn off both the pull-up and pull-downtransistors. When that happens, the output is disconnected from both +5 and ground; the output then is off,or “floating.” One usually says such a gate has been “three-stated” or put into its “high-impedance” state.

If you’re in the mood to design some logic, try to design the gating that will do the job, using NANDs alongwith the ’4007 MOSFETs. Here’s the way we want it to behave:

• If a line called Enable is low, turn off both the pull-up and pull-down transistors. That means—

– drive the gate of the upper transistor high;

– drive the gate of the lower transistor low.

• If Enable is high, let the Input signal drive one or the other of the upper and lower transistors on: thatmeans—


– drive the gates of the upper and lower transistors the same way—high or low—turning one on,the other off (because one is P-channel, the other N-channel, of course).

That probably sounds complicated, but the circuit is straightforward. If you’re eager to get on with building,peek at our solution, below.

Figure 15: 3-state circuit: qualifies gate signals to Qup and Qdown , using 74HC00 NAND gates

Use a slide switch to control the 3-state’s enable, as shown in fig. 16. A second slide switch drives a 100kresistor tied to the 3-state’s output. The slide switch can be set to ground or +5V: this slide switch, feeblydriving the common output line through the 100k, is included so that we can see whether the 3-state is enabledor not. A scope or voltmeter by itself is not able to detect the “off” condition, as you know.

Test your circuit by driving the input with the breadboard oscillator, and watching the effect of ENABLE.When the 3-state is disabled, even the feeble 100k should be able to determine the output level. Whenenabled, the 3-state should drive its square wave firmly onto the common output line. This “common outputline” provides our first glimpse of a data bus.

At the moment, before you have seen applications, this trick—the 3-state’s ability to disappear, electrically—may not seem exciting. Later, when you build your computer you will find 3-states invaluable, if not exciting.

Figure 16: Circuit to demonstrate operation of 3-state buffer

Figure 17: Three-states driving a shared “bus” line (do not bother to build this!)

Fig. 17 we show only to suggest why 3-states might be useful. This is meant to illustrate a single line of a“bus” or shared line, whereas a real parallel computer bus is at least 8 lines wide, and often much wider.18

lab14 d1 headerfile june14.tex;October 5, 2014)

18Recent designs have begun sometimes to exploit fast single line buses sending data serially. But parallel buses remain more usual.

Index

74HC00 (lab), 574LS00 (lab), 5

active pullup gate output: CMOS (lab), 11

CA3600 (lab), 9CD4007 (lab), 9

floating logic inputs (lab), 6–8

input protection clamp (lab), 7

logic probe (lab), 2

open-collector (lab), 3

three-state (lab), 11three-state buffer (lab), 11

13

Documents

Lab 14/D1: Logic Gates Contents