Lab 1 Report
2. a) The schematic for obtaining the IV characteristics of NMOS
transistor was made using the cadence tool. The schematic can be
seen in the first figure below.The circuit was simulated using
HSPICE and the result was viewed using Waveview. The (Ids vs. Vds)
plot can be seen in the second figure for Vgs values ranging from
0.15V to 1.05V, in steps of 0.15V.The plot of (log(Ids) vs. Vgs)
can be seen in the third figure for two different values of Vgs,
which are 0.15V and 1.05V.
Q2a. Ids vs. Vgs (Vds = {0.15V, 1.05V})
Q2a. Ids vs. Vds (Vgs {0.15V to 1.05V})Q2a. Schematic for NMOS
Characteristics
b) The schematic for obtaining the IV characteristics of PMOS
transistor can be seen in the first figure below. The corresponding
IV characteristics (Ids vs. Vds plot) for Vgs varying from 0.15V to
1.05V in steps of 0.15V can be seen in the second figure below.
Q2b. Schematic for PMOS Characteristics Q2b. Ids vs. Vds (Vgs
{0.15V-1.05V})
3. The schematic of the CMOS inverter made in cadence can be
seen in the figure below. We notice that the output capacitor is
missing in the figure below. The capacitor was added in the test
bench while simulating circuit.
Q3. Schematic of CMOS inverter
a) The transfer characteristics of the CMOS inverter can be seen
in the figure below. The white line represents the variation of the
output voltage (white) with respect to the input voltage
(yellow).
Q3a. VTC of CMOS inverter
b) The output of the CMOS inverter, given a ramp function as an
input can be seen in the figures below. As in the previous plot,
the white lines correspond to the output voltage, and he yellow
ones correspond to the input voltage. The figures correspond to the
same plot. However, four different figures have been presented to
indicate the values of 50% delay (both during rise and fall), the
rise time and the fall time. These values, as measured in the
simulation are given as follows: 50% Delay time during input rise:
63.8ps 50% Delay time during input fall: 123ps Fall time: 175ps
Rise time: 228ps
Q3b. 50% Delay time during input fallQ3b. 50% Delay time during
input rise
Q3b. Rise TimeQ3b. Fall Time
c) The value of the width of PMOS transistor for making both the
rise and fall times equal comes equal to 625nm. The plot of the
output voltage when the width of the PMOS transistor is made 625 nm
can be seen if the figure below. As in the previous plots, the
white lines correspond to the output voltage, and he yellow ones
correspond to the input voltage.
Q3c. Rise Time
4. The schematic for the NMOS only inverter can be seen in the
figure below.
Q4. NMOS only inverter
a) The plot for the variation of output voltage (white) with
respect to the input voltage (yellow) can be seen in the figure
below. According to the plot, the maximum value of the output
voltage is 0.85V then the input voltage is 0V. The minimum value of
the output voltage is 0.3V, when the input is 1.05V.
Q4a. NMOS only inverter output variation
b) The voltage transfer characteristics of an NMOS only inverter
can be seen in the figure below. As in the previous plots, the
white lines correspond to the output voltage, and he yellow ones
correspond to the input voltage.Q4. NMOS only inverter VTC
c) The main disadvantage of the NMOS only inverter, when
compared to a CMOS inverter is the amount of static power
dissipation. NMOS only inverter has a large static power
dissipation, when the input it high, as both the transistors are on
and there is a steady current flowing from VDD to VGND (as labeled
in schematic). CMOS inverter does not have any static power
dissipation, as one of the transistors is always off. The other
disadvantage of NMOS inverter, as is evident from its voltage
transfer characteristics is that its noise margin is less than CMOS
inverter. This is because NMOS transistor can pull up the output
pin only up to a voltage of (Vdd Vth) when the input is low. When
the input is high, there is a static current flowing from VDD to
VGND, which causes a potential drop across the bottom transistor,
increasing the voltage of the output.
