Dr. Abhijit R AsatiEEE Department,BITS, Pilani

A VIEW OF IC DESIGN

Complexity of VLSI Design Task

Problem Domain complexity•Completing or contradictory requirements(speed, power, area)“i d i t h” b t d d i•“impedance mismatch” between users and designers

•Application area specialization and knowledge•Changing/evolving specification •Specification capture issues•Cost of design/development

Complexity of ChoiceMany technologiesMan methodologies (FPGA Semi c stom/F ll c stom ASIC )Many methodologies (FPGA, Semi-custom/Full custom ASIC,….)Many logic forms (Static, Dynamic, 2-phase, 4-phase, ...)Combinatorial explosion as one goes down in abstraction levelMany possible partitions at each level

Other Complexities:•Clocking and Timing issuesClocking and Timing issues•Testing – related issues•Packaging – related issues

Different design methodologies differ inThe choice of number and levels of design abstractions usedduring the design processduring the design processManner of constraints on the translations between theabstraction levels.

For example, while translating from the logic level abstraction tophysical level, popular design methodologies are:

Field Programmable: (Semi-custom)PAL - Configurable interconnectsPAL Configurable interconnects PLA-Configurable interconnectsPROM- Configurable interconnectsFPGA C fi bl l i + i t tFPGA -Configurable logic + interconnect

ASIC•Semi-custom:Gate Array Standard CellsStandard Cells

•Full Custom:

The semicustom design do not require depth device level (transistorlevel) knowledge.

Reprogrammable method:

•Reserved primarily for emulations and prototypes

FPGA:

Reserved primarily for emulations and prototypes•FPGA gradually becoming mature and efficient•FPGA could offer an attractive alternative for low-volume

i l d t bcommercial products because:Lower NRE cost (Engineering costs, Prototypemanufacturing costs)Shorter time to marketCan be reprogrammed in the field to fix bugsMuch higher unit cost as compared to ASICMuch higher unit cost as compared to ASIC

Routing ChannelsProgrammableCells

Basic Structure of a Gate Array

• Xilinx Spartan‐II Family FPGA Block Diagram

. . .DLL DLL

IOBs

BlockRAM

BlockRAM

. . .

.

...

.

...

.

...

CLBs

Routing Channels

Block

.. .

Block

. ..Routing Channels

Delay‐locked loop (DLL) BlockRAM

BlockRAM. . .

Delay locked loop (DLL)‐ can be used for clocking

. . .DLL DLL

Gate Array Approach:

Channeled Gate-Arrays.Sea-of- Gates (SOG) Gate-Arrays.

•A vendor stocks the master or base wafers that have beend h f l i d l ili (i hprocessed upto the stage of laying down poly-silicon (i.e. the

transistors have been formed).•Personalization is then achieved by using design specificy g g pinterconnections (metallization and contacts).•Only 2-5 masks need to be generated, thus keeping mask costslowlow.

Conventional gate array and gate array with two embedded g y g ymemory bank.

•Chip area for a given function is large and speed is sub-optimal:The layout format is rigid and function aspecificThe layout format is rigid and function aspecific,W/Ls (transistor sizes)are also fixed and function aspecific.Mostly static logic is used.

•SOG gate arrays typically provide: Higher gate densities/smaller chip areasbetter suited for implementing storage elements and memoriesp g g(for small on-chip needs).

Gate Array Synthesis &Verification tools:Gate Array Synthesis &Verification tools:

•‘Synplify ASIC’ (for NEC Electronics gate array)

Standard Cell Approach:(Development of cell library and sub blocks)•Bottom up design implies designing a higher level function by•Bottom-up design implies designing a higher level function bycombining given/available parts of simpler functionalitye.g. designing a 2-input NAND gate by: bi i iCombining MOS transistorsCombining features on different mask layers to realize a transistorlevel circuit diagramgSizes of the transistors (W,L) are then obtained to get the desiredelectrical characteristics:

oSpeed Noise margins Power consumptionoSpeed, Noise margins, Power consumptionoOutput drive strengths: e.g. Inverter group has 1× drive cell(INV1), a 3× drive cell (INV3), and INV5, INV7, and INV9

llcells.The optimized transistor circuit is the converted to an areaefficient layout with the constraints of the layout form/style.y y y

•Basic logic gates (INV, BUF, NAND, NOR, AND, OR, XOR, Booleanfunctions) and sequential elements (Latches, Flip-flops, scan flip-flop)

•The standard cell style imposes constraints on:

Cell height (the width varies depending upon the gate/ functionCell height (the width varies depending upon the gate/ function

complexity)

L f t l i l tiLayer for external signal connections

Layer for supply and ground lines must be laid out.

•Design rule checks (DRC) are performed on the cells to ensure their

manufacturability.

•The extracted circuit is then characterized through circuit simulation to

produce:p

The detailed timing data under various load conditions

Circuit power consumption under various load conditionsCircuit power consumption under various load conditions

•Circuits are also characterized through simulation for variation in the

transistor parameters resulting fromtransistor parameters resulting from

Process variations:

L W t N N VoL, W, tox, NA, ND, Vt

otypical (or nominal), fast, slow

Environmental variations:

oEffect of elevated temperatures

Commercial (0oC–70oC), Industrial (-40oC–85oC), Military

(-55oC– 125oC)( )

oPower supply voltage variations ( 10 %)

Voltage regulator IR drops along supply rails di/dt noiseVoltage regulator, IR drops along supply rails, di/dt noise

otypical (or nominal), fast, slow

The delay of a path of 16 cells as a function of voltage and temperature

This phenomenon is caused by a competition between mobility and th h ld lt t d i t ll d lthreshold voltage to dominate cell delay.

Process variations combined with environmental variations arecalled design corners (PVT corners).

Design corners:

•The cells can be contacted from top or bottom for input(s) and

output(s).

•Horizontal metal lines for VDD and VSS run through each cell at the

same positions for all standard cells.

•Thus a horizontal row of abutting cells needs no routing of VDD andg g DD

VSS lines for the cells within the row.

•Mega Cells/System-level blocksMultipliersUARTs,RISC CoresRISC Cores

•Regular elements such as:•Register files,•RAMs•RAMs,•ROMs etc.•made available as parameterized macro cells (via cellgenerators).

•Compared to gate arrays, standard cell design provides a density

advantage at the cost of

Increased prototyping costs

Increased design complexity.

•Compared to gate arrays, standard cell design provides followingCompared to gate arrays, standard cell design provides following

advantages:

Increased speed ad antageIncreased speed advantage

Reduced area

Full custom Design:

•For the full custom design, layout constraints on the cells/blocks, ifany, are purely for the designer to decide.• Typically full custom designers also do impose certain constraints• Typically, full custom designers also do impose certain constraintson the layout:to make them fit closely into an overall block-leveli iinterconnection strategy.

• Design rule checks (DRC) are performed on the cells to ensuretheir manufacturability.y

Design EconomicsNonrecurring Engineering Costs (NREC)g g g ( )•Engineering costs•Prototype manufacturing costsMask costsMask costsTest fixture costsPackage tooling

R i CRecurring Costs•Wafer cost•Processing costg•Die yield•Package yield•Final test yieldFinal test yield•Testing