Lecture 10 & 11

Data Converters

A/D and D/A Conversion

A/D and D/A Conversion

A/D Conversion

D/A Conversion

fsampling ≥ 2 fmax

A/D Converters

Quantization

⋅

N inout

FS

VDivision : D = 2

V

• Quantization = division + normalization + truncation

• Full-scale range (VFS) is determined by Vref

...

Nyquist-Rate ADC (N-Bit, Binary)

• Word-at-a-time (1 step)† ← fast

– Flash

• Level-at-a-time (2N steps) ← slow

– Integrating (Serial)

• Bit-at-a-1me (N steps) ← medium

– Successive approximation

Accuracy-Speed Tradeoff

0

Resolution

[Bits]

5

10

15

20

1k 10k 100k 1M 10M 100M 1G 10G

Sample Rate [Hz]

Integrating

Successive Approximation

Algorithmic

Interpolating

Flash

100G

Quantization Error

FSout in out inN

Vε =D ∆ - V =D - V

2

FS

N

V∆ = =LSB

2

[ ]∈in FSV 0, V

≤ ≤∆ ∆

- ε2 2

Dout

0

Vin

∆ 2∆ 3∆

1

3

5

0

2

4

6

7

VFS

2

-∆-2∆-3∆

VFS

2

“Random” quantization error is

usually regarded as noise

N = 3

Single-Slope Integrating ADC

• Sampled-and-held input (Vi)

• Counter keeps counting until comparator output toggles

• Simple, inherently monotonic, but very slow (2N*Tclk/sample)

Vi

Control

CI

fclk Counter Do

VX

VY

Single-Slope Integrating ADC

• INL depends on the linearity of the ramp signal

• Precision capacitor (C), current source (I), and clock (Tclk) required

• Comparator must handle wide input range of [0, VFS]

⋅

⇒ ⋅

⋅

1i 1 o

clk

io

clk

clk

tIV = t , D =

C T

V D = ,

I T

C

I T LSB =

C

Successive Approximation ADC

• Binary search algorithm → N*Tclk to complete N bits

• Conversion speed is limited by comparator, DAC, and digital logic (successive

approximation register or SAR)

...

...

Binary Search Algorithm

• DAC output gradually approaches the input voltage

• Comparator differential input gradually approaches zero

Flash ADC Architecture

• Reference ladder

consists of 2N equal

size resistors

• Input is compared

to 2N-1 reference

voltages

• Massive parallelism

• Very fast ADC

architecture

• Latency = 1 T = 1/fs

• Throughput = fs

• Complexity = 2N

� �

En

cod

er

VFS Vi

fs

Strobe

Dout

2N-1

comparators

�

Do 0

Vi

∆

2∆

5∆

6∆

7∆

VFS

��

0

1

5

6

7

1

1

0

1

b2 b1 b0

001

010

110

111

000

ROM encoder

Thermometer Code

VFS Vi

fs

Strobe

2N-1

comparators

1

1

1

0

Thermometer code

1-of-n code

Static Performance

of ADC

Ideal ADC Transfer Characteristic

Dout

000 Vin

001

011

101

010

100

110

111

VFSVFS/20

Note the systematic offset! (floor, ceiling, and round)

Dout

000 Vin

001

011

101

010

100

110

111

VFSVFS/20

DNL and Missing Code

DNL = deviation of an input step width from 1 LSB (= VFS/2N = Δ)

• DNL = ?

th

i

i Step Size - ∆DNL =

∆

DNL and NonmonotonicityDout

000 Vin

001

011

101

010

100

110

111

VFSVFS/20

DNL = deviation of an input step width from 1 LSB (= VFS/2N = Δ)

D/A Converters

DAC Transfer Characteristic

Note: Vout (bi = 1, for all i) = VFS - Δ = VFS(1-2-N) ≠ VFS

⋅ ⋅ ⋅∑ ∑N N

N-iiout FS ii

i=1 i=1

bV = V = ∆ b 2

2

D/Abn

Digital input

Vout

Analog output

b1

...

Vref

• N = # of bits

• VFS = Full-scale input

• Δ = VFS/2N = 1LSB

• bi = 0 or 1

• Multiplication

Weighted Sum DAC

Inverted R-2R Ladder DAC

• A very common DAC circuit architecture with good precision.

• Currents in the ladder and the reference source are independent of digital

input. This contributes to good conversion precision.

• The “bit switches” need to have very low on-resistance to minimize

conversion errors.

– 23 –

Static Performance

of DAC

Ideal DAC Transfer Curve

Vout

000Din

001 011 101010 100 110 111

VFS-∆

VFS

2

Offset

Vout

000Din

001 011 101010 100 110 111

VFS

2

VFS-∆

Vos

Gain Error

Vout

000Din

001 011 101010 100 110 111

VFS

2

VFS-∆