KC705 Reference Design

User Guide

UG845 (v1.1) July 9, 2012

KC705 Reference Design User Guide www.xilinx.com UG845 (v1.1) July 9, 2012

Notice of DisclaimerThe information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available “AS IS” and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps.

© Copyright 2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

Revision HistoryThe following table shows the revision history for this document.

Date Version Revision

01/31/12 1.0 Initial Xilinx release.

07/09/12 1.1 Deleted Kintex-7 capability paragraph. Updated feature list. Added Tri-Mode Ethernet and AMS to list of example designs. Highlighted SW13 on board image. Replaced MIG GUI screen shot. Added MIG and IBERT setup instructions. Added Base TRD block diagram. Added BPI/SPI FLASH content table. Added Tutorials, Demonstrations, and Design files table to Additional Resources.

KC705 Reference Design User Guide www.xilinx.com 3UG845 (v1.1) July 9, 2012

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Chapter 1: KC705 Reference DesignsIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5KC705 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Restoring Flash Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Appendix A: Additional ResourcesXilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table of Contents

4 www.xilinx.com KC705 Reference Design User GuideUG845 (v1.1) July 9, 2012

KC705 Reference Design User Guide www.xilinx.com 5UG845 (v1.1) July 9, 2012

Chapter 1

KC705 Reference Designs

IntroductionThe KC705 Evaluation Kit is based on the XC7K325T-2FFG900 Kintex-7 FPGA. This FPGA contains 326,080 logic cells and supports a 10.3125 Gb/s serial line rate. For additional information, see the Kintex-7 Family FPGAs Product Table.

A built-in self test (BIST), feature demonstrations, and reference design files are provided with the KC705 Evaluation Kit. The BIST provides a convenient way to test many of the board's features on power-up and upon reconfiguration. After running through the tutorial provided in UG883, Kintex-7 FPGA Base Targeted Reference Design Getting Started Guide, the tutorials and reference designs available on the KC705 Web page can be used to further explore the capabilities of the KC705 and the Kintex-7 FPGA.

For the most up-to-date information on the tutorial content provided with the KC705 Evaluation Kit, see the KC705 Reference Design Web page athttp://www.xilinx.com/KC705.

KC705 FeaturesThe KC705 designs demonstrate Kintex™-7 FPGA features using the KC705 evaluation board. These features include:

• Kintex-7 XC7K325T-2FFG900C FPGA

• 1 GB DDR3 memory SODIMM

• 128 MB Linear BPI Flash memory

• 128 Mb Quad-SPI Flash memory

• Secure Digital (SD) connector

• USB JTAG via Digilent module

• Clock Generation

• Fixed 200 MHz LVDS oscillator (differential)

• I2C programmable LVDS oscillator (differential)

• SMA connectors (differential)

• SMA connectors for GTX transceiver clocking

• GTX transceivers

• FMC HPC connector (four GTX transceivers)

• FMC LPC connector (one GTX transceiver)

• SMA connectors (one pair each for TX, RX and REFCLK)

• PCI Express (eight lanes)

6 www.xilinx.com KC705 Reference Design User GuideUG845 (v1.1) July 9, 2012

KC705 Features

• Small form-factor pluggable plus (SFP+) connector

• Ethernet PHY SGMII interface (RJ-45 connector)

• PCI Express endpoint connectivity

• Gen1 8-lane (x8)

• Gen2 8-lane (x8)

• SFP+ Connector

• 10/100/1000 tri-speed Ethernet PHY

• USB-to-UART bridge

• HDMI codec

• I2C bus

• I2C MUX

• I2C EEPROM (1 KB)

• USER I2C programmable LVDS oscillator

• DDR3 SODIMM socket

• HDMI codec

• FMC HPC connector

• FMC LPC connector

• SFP+ connector

• I2C programmable jitter-attenuating precision clock multiplier

• Status LEDs

• Ethernet status

• Power good

• FPGA INIT

• FPGA DONE

• User I/O

• USER LEDs (eight GPIO)

• User pushbuttons (five directional)

• CPU reset pushbutton

• User DIP switch (4-pole GPIO)

• User SMA GPIO connectors (one pair)

• LCD character display (16 characters x 2 lines)

• Switches

• Power on/off slide switch

• Configuration mode DIP switch

• VITA 57.1 FMC HPC Connector

• VITA 57.1 FMC LPC Connector

• Power management

• PMBus voltage and current monitoring via TI power controller

• XADC header

KC705 Reference Design User Guide www.xilinx.com 7UG845 (v1.1) July 9, 2012

Reference Designs

• Configuration options

• Linear BPI Flash memory

• Quad SPI

• USB JTAG configuration port

• Platform cable header JTAG configuration port

Reference DesignsReference designs include:

• Built-In Self Test (BIST) Design

• Memory Interface Generator (MIG) Design

• Integrated Endpoint Block for PCI Express Design

• MultiBoot Design

• ChipScope Pro IBERT Design

• LogiCORE Tri-Mode Ethernet Design

• Agile Mixed Signal (AMS) Example design

• Base Targeted Reference Design

Built-In Self Test (BIST) DesignTo run the BIST, attach a power cable and USB-UART cable (see Figure 1-1), then set the KC705 configuration mode and flash address switch (SW13) to 11010 and power on the board.X-Ref Target - Figure 1-1

Figure 1-1: KC705 Board

UG845_06_053112

8 www.xilinx.com KC705 Reference Design User GuideUG845 (v1.1) July 9, 2012

Reference Designs

The BIST tests many of the features offered by the KC705 evaluation kit. When the configuration mode and flash address switch is set for Master BPI mode, the BIST menu appears on power-up (Figure 1-2).

Start a terminal program, such as TeraTerm, to view the expected output.The default location of the BIST program is the on-board BPI linear flash. The KC705 Restoring Flash Contents tutorial provides instructions for restoring the non-volatile flash memory to its factory default content.

X-Ref Target - Figure 1-2

Figure 1-2: BIST Initial Screen

UG845_01_011212

KC705 Reference Design User Guide www.xilinx.com 9UG845 (v1.1) July 9, 2012

Reference Designs

Memory Interface Generator (MIG) DesignThe 7 series FPGAs memory interface solutions core is a combined pre-engineered controller and physical layer (PHY) for interfacing 7 series FPGA user designs and advanced extensible interface (AXI4) slave interfaces to DDR3 SDRAM devices. Refer to UG586, 7 Series FPGAs Memory Interface Solutions User Guide for more information about the 7 series FPGAs memory interface solutions.

For the logic designer, the MIG tool (Figure 1-3) can be use to create a simple user interface that abstracts away the complexity of memory transactions. The integrated memory controller block's assembly and signal connectivity is made transparent to the user.

The LogiCORE™ MIG example debug design tests the DDR3 memory interface through a series of writes and reads with pattern verification. The example design was generated using the option to include the debug interface. The results can be viewed in the ChipScope Pro™ Analyzer tool as shown in Figure 1-4.

X-Ref Target - Figure 1-3

Figure 1-3: MIG Graphical User Interface

UG585_02_053112

10 www.xilinx.com KC705 Reference Design User GuideUG845 (v1.1) July 9, 2012

Reference Designs

To run the MIG design, attach a power cable and USB-UART cable (see Figure 1-1), then set the KC705 configuration mode and flash address switch (SW13) to 01010 and power on the board.

For more information on the MCB, refer to UG586, 7 Series FPGAs Memory Interface Solutions User Guide. For information about the ChipScope Pro Analyzer tool, refer to UG029, ChipScope Pro Software and Cores User Guide.

Integrated Endpoint Block for PCI Express DesignThe LogiCORE IP Kintex-7 FPGA integrated Endpoint block for PCI Express® core is a high-bandwidth, scalable, and reliable serial interconnect building block for use with Kintex-7 FPGA devices. The Kintex-7 FPGA integrated Endpoint block for PCI Express (PCIe®) solution supports a 1-lane configuration that is protocol-compliant and electrically compatible with the PCI Express Base Specification v1.1.

The integrated Endpoint block solution is compatible with industry-standard application form factors such as the PCI Express Card Electromechanical (CEM) v1.1 and the PCI Industrial Computer Manufacturers Group (PICMG) 3.4 specifications. For more information, refer to UG477, 7 Series FPGAs Integrated Block for PCI Express User Guide.

X-Ref Target - Figure 1-4

Figure 1-4: ChipScope Pro Analyzer Tool

UG845_03_011112

KC705 Reference Design User Guide www.xilinx.com 11UG845 (v1.1) July 9, 2012

Reference Designs

Xilinx provides the Kintex-7 FPGA integrated Endpoint block for PCI Express solution to configure the Kintex-7 FPGA integrated Endpoint block for PCIe Express core in the FPGA and includes additional logic to create a complete Endpoint solution for PCIe (see Figure 1-5). This Xilinx integrated Endpoint block wrapper for PCIe simplifies the design process and reduces time-to-market.

The 8-lane PCIe edge connector performs data transfers at the rate of 2.5 GT/s for a Gen1 application. The provided designs cover Gen1 8-lane and Gen2 4-lane functionality.

See the KC705 PCIe x8 Gen1 Design Creation tutorials for more information.

MultiBoot DesignFigure 1-6 illustrates the MultiBoot operation. The 7 series FPGAs MultiBoot and fallback features support updating systems in the field. Bitstream images can be upgraded dynamically in the field. The FPGA MultiBoot feature enables switching between images on the fly. When an error is detected during the MultiBoot configuration process, the FPGA can trigger a fallback feature that ensures a known good design can be loaded into the device.

Implementation of a robust in-system update solution involves a set of decisions. First, a method for system setup needs to be determined. Next design considerations can be added for a specific configuration mode. Finally, HDL design considerations need to be taken into account and files need to be generated properly.

The golden image is loaded from address space 0 at power up. Next, the golden image design triggers a MultiBoot image to be loaded. This step is beneficial when initial system checking is required prior to loading a run-time image. The system checking or diagnostics can be contained in the golden image, and the run-time operation can be contained in the MultiBoot image. At power up, the golden image is always loaded. This design triggers booting from an upper address space. Multiple MultiBoot images can also exist, and any

X-Ref Target - Figure 1-5

Figure 1-5: Integrated Endpoint Block for PCI Express Solution

LogiCORE IP 7 Series FPGAs Integrated Block for PCI Express Core

7 Series FPGAs Integrated Block for

PCI Express (PCIE_2_1)

Transceivers

Optional Debug

System(SYS)

User Logic

UG845_07_011312

PCIExpressLogic

ClockandReset

PCI Express(PCI_EXP)

UserLogic

Physical LayerControl and Status

HostInterface

Transaction(AXI-ST)

UserLogic

Optional Debug(DRP)

Physical(PL)

Configuration(CFG)

TX Block RAM

RX Block RAM

12 www.xilinx.com KC705 Reference Design User GuideUG845 (v1.1) July 9, 2012

Reference Designs

design can trigger any another image to be loaded. If an error occurs during loading of the MultiBoot image from the upper address space, the fallback circuitry triggers the golden image to be loaded from address 0.

For additional information on the Kintex-7 FPGA MultiBoot feature, see UG470, 7 Series FPGAs Configuration User Guide. For a demonstration of this operation on the Kintex-7FPGA, see the KC705 MultiBoot Demonstration.

ChipScope Pro IBERT DesignThe CORE Generator tool provides designers using the Kintex-7 GTX transceivers the ability to generate a hardware design containing an Integrated Bit Error Ratio Test (IBERT) core. The IBERT core instantiates a design with Kintex-7 GTX transceivers, data pattern generators, and data pattern checkers (see Figure 1-7). The generated hardware design is based on user input for the device part and package, the location of a system clock pin, the desired GTX reference clock, and the expected line rate. When configured, the IBERT design running in the FPGA is controlled through the ChipScope Pro Analyzer's IBERT console to set GTX transceiver attributes and to exercise the high-speed serial GTX transceivers.

X-Ref Target - Figure 1-6

Figure 1-6: MultiBoot Operation

UG845_04_011612

Memory Map of Flash

Upper Address

Base Address

MultiBoot Image

BIT File Stored inUpper Address

Golden Image

BIT File Stored atAddress 0

Boot Golden Image

Power Up

Trigger MultiBoot

ConfigurationPasses?

No

Yes

Run MultiBoot Image

KC705 Reference Design User Guide www.xilinx.com 13UG845 (v1.1) July 9, 2012

Reference Designs

The LogiCORE IBERT designs verify loopback connections over the following interfaces that use the GTX transceivers:

• FMC HPC connector (four GTX transceivers)

• FMC LPC connector (one GTX transceiver)

• SMA connectors (one pair each for TX, RX and REFCLK)

• PCI Express (eight lanes)

• Small form-factor pluggable plus (SFP+) connector

• Ethernet PHY SGMII interface (RJ-45 connector)

The KC705 GTX IBERT Design Creation tutorials and accompanying reference designs illustrate how to use the CORE Generator tool and the ChipScope Pro Analyzer software to exercise the KC705 GTX transceivers.

To run the IBERT design, attach a power cable and USB-UART cable (see Figure 1-1), then set the KC705 configuration mode and flash address switch (SW13) to 10010 and power on the board.

For information about the ChipScope Pro Analyzer tool, refer to UG029, ChipScope Pro Software and Cores User Guide.

LogiCORE Tri-Mode Ethernet DesignThe Tri-Mode Ethernet MAC (TEMAC) design comprises the 10/100/1000 Mb/s, 1 Gb/s and 10/100 Mb/s IP cores which are fully-verified designs that support Verilog HDL and

X-Ref Target - Figure 1-7

Figure 1-7: IBERT Core (Generated Using ChipScope Pro Software)

UG845_06_011112

Board-Under-Test

Host Computer with ChipScope Pro Software

JTAGConnections

ChipScopePro

Target Device Under Test

UserFunction

UserFunction

UserFunction

ILA Pro

ICON Pro

ILA Pro

ILA Pro

ParallelCable

14 www.xilinx.com KC705 Reference Design User GuideUG845 (v1.1) July 9, 2012

Reference Designs

VHDL. In addition, the example design provided with the core is in both Verilog and VHDL.

The Ethernet MAC block (Figure 1-8) is provided as part of the HDL example design and includes the basic blocks required to use the Ethernet MAC netlist. The Ethernet MAC Block should be instantiated in all designs that use the core. The AXI4-Lite Wrapper allows the MAC netlist to be connected to an AXI4-Lite Interface and drives the Ethernet MAC netlist through a processor independent IPIF.

The reference design provided with the KC705 walks the user through generating the core via Xilinx CORE generator. The activity of the core can then be observed using ChipScope in conjunction with Wireshark (Figure 1-9).

X-Ref Target - Figure 1-8

Figure 1-8: Tri-Mode Ethernet MAC Block Diagram

Receive Engine

Configuration

Optional Frame

Filter

MDIO

AXI4 StreamRX Interface

GM

II / M

II B

lock

Optional Management

Ethernet MAC Netlist

Statistics Counters Interrupt Control

PH

YIn

terf

ace

RG

MII/

GM

II/M

II

Ethernet MAC Block

AXI4-LiteWrapper

StatisticsVector

Decode

AXI4-LiteInterface

AXI4 StreamTX Interface

UG845_c1_08_062212

To PhysicalLayers

Transmit Engine

Flow Control

KC705 Reference Design User Guide www.xilinx.com 15UG845 (v1.1) July 9, 2012

Reference Designs

F

Agile Mixed Signal (AMS) Example designThe AMS (Agile Mixed Signal) Evaluation Platform enables hardware and software developers to evaluate the XADC block and AMS technology integrated with all of the Xilinx 7 series FPGAs.

The XADC block integrated in the FPGA offers:

• 12-bit, 1Msps dual ADCs

• 17 differential channels

• Internal temperature sensor

• FPGA supply voltage sensors

The AMS Evaluator GUI is constructed in National Instruments’ LabView. It allows designers to quickly evaluate the analog signals in the time domain, frequency domain, display linearity, verify the XADC register settings, measure the internal temperature sensor and supply voltages, and debug. The AMS Evaluator GUI also lets users perform decimation on the XADC output data to enhance the performance.

For more information, see the Agile Mixed Signal webpage at www.xilinx.com/ams.

Base Targeted Reference DesignThe base targeted reference design (TRD) included with the KC705 evaluation kit is designed to encompass multiple board features. The primary components of the TRD are the integrated Endpoint Block for PCI Express, Northwest Logic's Packet DMA, and a multiport virtual FIFO (Figure 1-10). The TRD system is capable of sustaining up to 10

X-Ref Target - Figure 1-9

Figure 1-9: Wireshark Screen Image

UG845_c1_09_062212

16 www.xilinx.com KC705 Reference Design User GuideUG845 (v1.1) July 9, 2012

Restoring Flash Contents

gigabits per second (Gb/s) throughput end to end.

The Kintex-7 FPGA Integrated Endpoint block for PCI Express and the packet DMA are responsible for data transfers from host system to Endpoint card (S2C) and Endpoint card to host system (C2S). Data to and from the host is stored in a virtual FIFO built around the DDR3 memory. This multiport virtual FIFO abstraction layer around the DDR3 memory allows the user to move traffic efficiently without the need to manage addressing and arbitration on the memory interface. It also provides a larger depth when compared to storage implemented using block RAMs.

The integrated Endpoint block for PCI Express, packet DMA, and multiport virtual FIFO can be considered as the base system. The base system can bridge the host to any user application running on the other end. The raw data packet module is a dummy application which generates and consumes packets. It can easily be replaced by any user specific protocol such as Aurora or XAUI.

Note: In Figure 1-10 the arrows indicate AXI interface directions (from master to slave). They do not indicate data flow directions.

For further explanation of the content in the Base TRD, as well as instructions on how to run it, see UG883, Kintex-7 FPGA Base Targeted Reference Design Getting Started Guide,

Restoring Flash ContentsThe KC705 evaluation kit contains several non-volatile memories (linear BPI flash, SPI flash) that can be overwritten by user created designs. The Restoring Flash Contents tutorial provides a means to re-establish the original functionality programmed into the linear BPI flash.

For more information on configuration of the FPGA via a flash interface, see UG470, 7 Series FPGAs Configuration User Guide. For more information on the specific flash

X-Ref Target - Figure 1-10

Figure 1-10: Kintex-7 FPGA Base TRD Block Diagram

UG845_09_053112

Multiport Virtual FIFO

DD

R3

I/O

Software

Multi-ChannelDMA for PCIe DDR3

Cha

nnel

-0C

2SS

2CC

hann

el-1

S2C

C2S

64 x1,600 Mb/s

PC

Ie x

4Gen

2 Li

nk /

PC

Ie x

8Gen

1 Li

nk

VFIFOController

SoftwareDriver

Interface Blocks in FPGA Third Party IPXilinx IP On BoardCustom Logic

AXI-ST AXI-MM

Hardware

VFIFOController

VFIFOController

VFIFOController

Raw Packet Data Block

Checker

Generator

Loop

back

Loop

back

Raw Packet Data Block

Generator

Checker

User SpaceRegisters

Target InterfaceAXI Master

256 x200 MHz

64 x

250

MH

z

64 x250 MHz

64 x250 MHz

64 x250 MHz

64 x250 MHz

PerformanceMonitor

GU

I

GT

X T

rans

ceiv

er

Inte

grat

ed E

ndpo

int B

lock

for

PC

I Exp

ress

AX

I-S

T B

asic

Wra

pper

AXIMIG

AXIInterconnect

SI SI

SI SI

MI

KC705 Reference Design User Guide www.xilinx.com 17UG845 (v1.1) July 9, 2012

Restoring Flash Contents

modules on the KC705 Evaluation Kit, see UG810, KC705 Evaluation Board for the Kintex-7 FPGA User Guide.

Table 1-1: List of Designs Stored in BPI/SPI FLASH

Location Description

SPI Empty

BPI configuration address 0 Base TRD Design

BPI configuration address 1 MIG

BPI configuration address 2 IBERT

BPI configuration address 3 BIST

18 www.xilinx.com KC705 Reference Design User GuideUG845 (v1.1) July 9, 2012

Restoring Flash Contents

KC705 Reference Design User Guide www.xilinx.com 19UG845 (v1.1) July 9, 2012

Appendix A

Additional Resources

Xilinx ResourcesFor support resources such as Answers, Documentation, Downloads, and Forums, see the Xilinx Support website at:

http://www.xilinx.com/support.

For a glossary of technical terms used in Xilinx documentation, see:

http://www.xilinx.com/company/terms.htm.

References These documents provide supplemental material useful with this user guide:

• Kintex-7 FPGAs Product Tablehttp://www.xilinx.com/publications/prod_mktg/Kintex7-Product-Table.pdf.

• UG883, Kintex-7 FPGA Base Targeted Reference Design Getting Started Guide

• UG882, Kintex-7 FPGA Base Targeted Reference Design User Guide

• UG810, KC705 Evaluation Board for the Kintex-7 FPGA User Guide

• UG586, 7 Series FPGAs Memory Interface Solutions User Guide

• UG029, ChipScope Pro 12.3 Software and Cores User Guide

• UG477, 7 Series FPGAs Integrated Block for PCI Express User Guide

• UG470, 7 Series FPGAs Configuration User Guide

• PCI-SIG Documentation (www.pcisig.com/specifications)

• PCI Express Base Specification 1.1

• PCI Express Card Electromechanical (CEM) Specification 1.1

KC705 tutorials, demonstration, and design files are located athttp://www.xilinx.com/KC705.

Table A-1: KC705 Tutorials, Demonstrations, and Designs

Item Documents

KC705 BIST RDF0102, XTP102

KC705 IBERT RDF0103, XTP103

KC705 Multiboot RDF0104, XTP104

KC705 MIG RDF0105, XTP105

20 www.xilinx.com KC705 Reference Design User GuideUG845 (v1.1) July 9, 2012

Appendix A: Additional Resources

KC705 PCIe RDF0106, XTP106

KC705 Restoring Flash RDF0145, XTP131

Table A-1: KC705 Tutorials, Demonstrations, and Designs (Cont’d)

Item Documents