The Role of JTAG in system debug & test throughout the embedded system development lifecycle

At the heart of contemporary embedded solutions are systems on chip (SOCs) with millions of gates, integrating cache, scratchpad random access memory (RAM), and peripheral functions onto one chip; many component interfaces are buried within the chip and no longer available at the pin or board level for system test/debug. The CPU core is now running at hundreds of megahertz (MHz), and has integrated many of the hardware interfaces, so historical test methodology is no longer possible.

The Joint Test Action Group (JTAG) began solving board-level test problems in the 1990's by standardizing a serial scan chain method (JTAG; IEEE 1149.1) for accessing on-chip resources and additional shift registers built into the I/O paths of every IC for boundary scan testing.

The boundary scan testing methodology addresses this issue. As illustrated in Figure 1, a serial scan path through I/O registers was added and exercised by a sophisticated test program unique to each board to help identify a faulty chip or other device, so that these can be reworked or replaced. In the diagram in Figure 1, each grey box represents a category of device function, e.g., flash, peripherals, I/O ports, etc.

JTAG to the Rescue - Boundary Scan Testing

The JTAG approach provides a method to test very complex systems, while keeping the pin count low. Specifically, the IEEE1149.1 specification requires only 5 pins for the JTAG connection, no matter how long the scan chain register path is. The standard pin functions for the JTAG Test Access Port include:

TRST Test Reset (output from JTAG probe to chip to reset JTAG test logic)

TCK Test Clock (output from JTAG probe to chip to set JTAG scan rate)

TDI Test Data Input (serial test data input to chip)

TDO Test Data Output (serial test data output from chip)

TMS Test Mode Select (determines run or debug mode by state at TCK rising edge)

The 2nd Role of JTAG - CPU Core Access for Software/Hardware Debug

he 2nd Role of JTAG - CPU Core Access for Software/Hardware DebugGiven that the CPU processor core is now hidden from observation or control by integrated caches in the core, by local on chip busses, by an MMU that dynamically allocates memory, and by other SOC peripherals and I/O blocks, the JTAG path provides a direct connection into the debug logic inside the CPU. Thus, we now have a means of observing and controlling program execution. Since caches and peripherals have moved on chip, so must the debug logic (Figure 2 below).

With this direct core access, host-based debugger software can now assert a "debug exception", redirecting the processor to get the next instruction from the debug logic registers instead of the program counter, thus effectively taking control of the processor to perform software debug operations:

* Run-control: Start, Stop, Single-Step, Step Into/Over (source or instruction) * Set hardware and software breakpoints* Specify conditions to be met or scripts to be executed at breakpoints* Control reset and initialization of the target system* Download code to be debugged or code to be programmed into flash* Execute flash programming and other semi-hosting utilities

Note that in both of the above applications, boundary scan and software debug, the role of JTAG is only to provide the physical layer communications interface, analogous to the PHY layer in the ISO Open Systems Interconnect model.

The protocol for what debug functions are supported is embodied in the debug logic, designed into the CPU core and the debugger software capabilities running on the host computer.

JTAG Debug AdvantagesThe primary advantages of using a debugger with JTAG access are:* The JTAG connection provides direct access to the otherwise hidden CPU core * The JTAG interface consumes no system I/O ports (serial, Ethernet) * The JTAG debug method uses little or no system memory allocation (as in monitors) * There is no monitor to crash along with a system crash (not useful at board bring-up) * The JTAG connection does not require target system power (except some USB-only probes) * A JTAG debugger can "steal cycles" to read registers/memory without stopping CPU (assuming that the debug logic built into the CPU provides this capability) * A JTAG debug session can reset and/or initialize the system (Note: System reset is not part of JTAG. Rather, it is an adjunct to using JTAG for remote debugging, enabling a remote reset of a JTAG probe and target over a network.) * A JTAG debugger can connect to the debug logic without perturbing the system* Provides the only reasonable means to connect to targets that do not yet have working bootcode or I/O drivers

n addition to hardware/software debug and boundary scan testing, the JTAG connection is also being used by various tool providers for direct in-circuit flash programming, sending command scripts for execution on the target board, programming field programmable logic devices (FPLDs), and providing similar specialized debug capabilities for other functional blocks such as digital signal processor(DSP). Many sophisticated ICs include built-in self test capabilities that are initiated and post analyzed via JTAG.

ConclusionSince the JTAG scan path provides direct core access, the benefits of applying JTAG methodology span from chip design through all phases of system development and product lifecycle of embedded devices. As shown in table one, there are considerable value considerations behind applying the JTAG methodology to each of the major life cycle phases--from initial validation of the chip design, prior to tape-out--to the implantation of system field support diagnostics and software updates.