IWCE 10 Purdue University October 24-27 2004 Intrinsic Parameter Fluctuations in Conventional MOSFETs at the scaling Limit: A Statistical Study *F. Adamu-Lema,

IWCE 10 Purdue University October 24-27 2004

Intrinsic Parameter Fluctuations in Conventional MOSFETs at the scaling Limit:

A Statistical Study

*F. Adamu-Lema, G. Roy, A. R. Brown,

A. Asenov and S. Roy

Device Modelling Group, University of Glasgow,

Department of EEE, Rankine Building,

G12 8LT, Scotland, UK

* [email protected]


Outline

IntroductionMethodology

Calibration Scaling Atomistic Simulation

ResultsConclusions


Outline

IntroductionMethodology


ResultsConclusions


The road map requirements

Year of Production 2019 2022 2025

Technology Node 15 10 7

Printed Gate length 9 6 4

Physical Gate Length (nm) 6 4 3

Year of Production 2010 2012 2013 2015 2016 2018

Technology Node hp45 hp32 hp22

DRAM ½ Pitch (nm) 45 35 32 25 22 18

MPU/ASIC M1 ½ Pitch (nm) 54 42 38 30 27 21

MPU/ASIC Poli Si ½ Pitch (nm) 45 35 32 25 22 18

Printed Gate Length (nm) 25 20 18 14 13 10

Physical Gate Length (nm) 18 14 13 10 9 7

M. Ieong, NPMS/SIMDMaui Dec. 2003

Year of Production 2003 2004 2005 2006 2007 2008 2009

Technology Node hp90 hp65

DRAM ½ Pitch (nm) 100 90 80 70 65 57 50

MPU/ASIC M1 ½ Pitch (nm) 120 107 95 85 75 67 60

MPU/ASIC Poli Si ½ Pitch (nm) 100 90 80 70 65 57 50

MPU Printed Gate length (nm) 65 53 45 40 35 32 28

MPU Physical Gate Length (nm) 45 37 32 28 25 22 20

ITRS 2003 Near-Term TN characteristics

Long-Term TN characteristics

IBM roadmap


When the number and position of dopants matter MOST!

Atomistic device and process simulation is important to resolve the impact of eachindividual dopant in the device in terms of electrostatics and transport

H. Wakabayashi et al. IEDM 03


Intrinsic parameter fluctuations already affect real circuit

0.0 0.2 0.4 0.6 0.8 1.00.0

0.2

0.4

0.6

0.8

1.0

Vou

t2(V

)

Vout1

(V) 0.00 0.05 0.10 0.15 0.200

10

20

30

40

Fre

quen

cy

SNM (V)

Cell ratio=1 Cell ratio=2 Cell ratio=3 Cell ratio=4

35 nm MOSFET

B. Cheng ULIS ‘04


OutlineIntroductionMethodology


ResultsConclusions


Methodology I: calibration

The device simulations have been calibrated In respect of a real reference 35 nm MOSFET* used as a base for further scaling.

Full process simulation was performed to obtain device structure and channel doping profiles of the 35n n-channel device.

Device simulation was used in order to verify the structure and to extract the relevant transport parameters.

* S. Enaba, et. al., IEDM ‘02


The calibrated doping profiles

Source Drain

Ga

te

Substrate

GL = 35nm

Xj =

20

.3n

m

To

x =

1.2

nm

Y

X

30o 30o

Poly gate

P - well

Source Drain

Halo doping

•The calibrated device structure, •1D channel doping profile and,• Halo doping profile in the S/D extension region


The calibrated device characteristics

Id-Vg characteristics of the calibrated and the measured data of the 35nm device at high drain voltage Vdd = .85V, at low drain voltage of Vdd = 0.05V and the Id-Vd characteristics

0.0 0.2 0.4 0.6 0.8 1.00.0

3.0x10-5

6.0x10-5

9.0x10-5

1.2x10-4

1.5x10-4

I d [A/

m]

Gate Voltage [V]

This work Toshiba Device

Vdd

= 50mV

VT = 198mV

S = 83.57mV/dec

0.0 0.2 0.4 0.6 0.8 1.0

1E-7

1E-6

1E-5

1E-4

1E-3

log(

I d) [

A/

m]

Gate Voltage [V]

This Work Toshiba Device

Vdd

= 850 mV

Ion

= 676 A (Extracted)

Ion

= 709 A (Simulated)

Ioff

= 0.1 A

0.0 0.2 0.4 0.6 0.8 1.0

0.0

1.0x10-4

2.0x10-4

3.0x10-4

4.0x10-4

5.0x10-4

6.0x10-4

7.0x10-4

8.0x10-4

Vg = 150mVVg = 250mVVg = 350mV

Vg = 450mV

Vg = 550mV

Vg = 650mV

Vg = 750mV

Dra

in C

urr

en

t

Drain Voltage [V]

Toshiba Data This work Vg = 850mV




ResultsConclusions


Methodology II: Scaling

The scaling strategy is based on the generalised scaling rules* and the ITRS roadmap predictions for high performance devices up to the year 2018

The well calibrated 35 nm real MOSFET has been used as a base for further scaling of the 25, 18, 13 and 9 nm transistors (required for 65, 45, 32 and 22 nm technology nodes respectively)

All the device structures are obtained from full process simulations on which the device simulation analyses have been performed

* G. Baccarani, et. al, 1984


Scaling MOSFETs up to the end of ITRS

0.0 0.2 0.4 0.6 0.8

10-7

10-6

10-5

10-4

10-3

log

( I d

) [

A/

m ]

VG

[V]

35nm Calibrated @ Vd = 850mV

35nm Experimental @ Vd = 850mV

25nm Scaled @ Vd = 800mV




0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.161017

1018

1019

1020

1021

Co

nc

en

tra

tio

n [I

on

s/cm

3]

Vertical Depth [ m ]

Indium Experimental Indium Simulation Arsenic Toshiba Arsenic Simulation

Projected range R

P 66nm

35nm25nm

18nm13nm9nm

Back ground doping level

35 nm (Toshiba IEDM 02)35 nm (Toshiba IEDM 02)

6nm nm (VLSI ‘04 )6nm nm (VLSI ‘04 )




ResultsConclusions


From continuous doping to Atomistic


Quantum correction using Density Gradient

Classical Charge

Quantum Charge

Classical potential

Quantum potential




ResultsConclusions


VT variation induced by discrete random dopants in scaled devices

10 15 20 25 30 3520

40

60

80

100

120

140

160

180

VT [

mV

]

Physical Gate Length [ nm ]

The variation in the threshold voltage increases in every TNBelow 20 nm gate length VT = 60mV, and 6 = 360mV.For the 9nm device the VT=170mV and 6 = 1020mV.


Ion and Ioff distribution in the scaled devices

Ion distribution of three scaled devices

Ioff distribution of three scaled devices


Conclusions

We have estimated the magnitude of intrinsic parameter fluctuations in realistically scaled devices, which corresponds to all technology node in ITRS 2003 edition.

VT increases in every technology node and reaches more than 150 mV at the end of technology roadmap

The sub-threshold drain current distribution of the scaled devices highly skewed away from the normal distribution and the log of the off-current should be used for statistical analysis

Documents

IWCE 10 Purdue University October 24-27 2004 Intrinsic Parameter Fluctuations in Conventional MOSFETs at the scaling Limit: A Statistical Study *F. Adamu-Lema,