2
DEVICE RESEARCH CONFERENCE 1259 The planar GaAs devices show anomalous phenomena such as the hysteresis of I-V characteristics, current drift and substrate bias effect, which seem to originate from interface traps.l In this paper, we conclude that theanomalous phenomena are mainly due to deep centers located in the substrate near the interface at theenergy above the Fermi level. The density and the acti- vation energy are estimated by measuring a current reduction and the time constants of current decay. The reduction factorof the channel current was measured by applying dc negative voltage to the back contact of the semi-insulating substrate. The width of the excess charge density in the negative space-charge region were calculated so as to make fitting to the measurement of currect reduction factors. In a typical TED, the width ranges from 0.2 to 0.4 pm and the excess charge-density from 1.5 to 8 X 1016 cm-3 when the interfacial n-i junction voltage changes from 2 to 16 V. The channel current slowly decays after the gate voltage is switched on and recovers after itis off. The time constantwas measured at various temperatures by applying a pulse technique and the activation energy was obtained. The time constant was typically 40 ps at room temperature and the activation energy was 0.44 eV. The anode dc bias also leads to slow decay of the channel current. The time constant is almost equal to that of the gate dc bias. The similar current drift was observed in GaAs FET’s made in VPE layer without a buffer layer.The activation energy of the time constant was 0.62 eV when the drain voltage was switched off and 0.65 eVwhen the substrate bias was switched off. The gate dc bias gave two activation energies, 0.13 eV and 0.66 eV. The potential distribution was analyzed in the vicinity of the interfacial n-i junction in both cases with and without trap cen- ters, to show how trap centers affect the channel current. For the trap-free case, the potential drop in the active layer isin the order of magnitude of kT/q, which is too small to have an influence to the channel current. However, when there are trap centers lo- cated above the Fermi level at thermal equilibrium, as is the case of the trap around 0.44 eV, the potential drop inside the active layer becomes large and the depletion layer extends to modulate the channel current. Electron density and electric field distri- butions were calculated as a function of trap density, trap energy, carrier densityand current density flowing across the interface. For instance, when the trap density is 1017 ~ m-~, the energy 0.44 eV, the carrier density 10l6 ~ m - ~ and the current density 6 mA/ cm2, a depletion layer extends into the active layer as deep as 0.5 pm. Thus, the current reduction factor can be calculated and be fitted to the measurement. According to themodel, the excess charge density divided by the current density shouldbe inde- pendent from the current density and this was verified by the experiments. The typical results show that the deep centers are from 1 to 4 X 1017cm-3. The exact numerical calculations were also carriedout and supported the simplified analysis. The details of the results will be presented. mance,” 5th Bienn. Cornell Elec. Eng. Conf., Sec. 111.3, August 1975. * J. Barrera, “The importance of substrate properties on GaAs FET Perfor- IVB-6 An In-Situ Technique for Anodic Etch to Voltage Preparation of GaAs Read Diodes1-D. J. Coleman, Jr., Texas Instruments Incorporated, Dallas, Texas 75222 and R. L. Adms, Teledyne, MEC, Palo Alto, CA 94304. GaAs Read diode structures employa thin epitaxial surface layer whose thickness must be precisely controlled. The surface layers are commonly grown thicker than necessary and etched back to the desired thickness. A self-limiting anodic oxidation technique ideally suited to accomplish this etching was recently proposed by Niehaus and Schwartz.2 However, the technique which they have reported requires many transfers of the slice between the anodic oxidation electrolyte and an etchant which dissolves the oxide. Using 0.02M N,H2P04 as an electrolyte, we have found that the oxide growth proceeds as described by Nie- haus and Schwartz with the slice anodically biased and that the oxide is removed when the slice is cathodically biased. It is therefore possible to thin the surface layer of a GaAs Read diode slice held insitu in an electrolyte by simply reversing the polarity of the applied bias. Sequential stages of the cathodic oxide removal process will be shown which suggest that the oxide is lifted off of the GaAs. Surface properties of the GaAs surface having undergone ca- thodic oxideremoval will be discussed and comparedwith chemically etched surfaces. Experiments comparing the surface tension of water droplets and Pt Schottky Barrier characteristics havebeenperformedindicating that the surface of wafers subjected to cathodic bias is not degraded for device preparation. Recent results obtained with devices fabricated by this technique will be presented. technique for fabrication of modified Read-IMPAT’rs,” Solid-State Electronics, W. C. Niehaus and B. Schwartz, “A self-limiting anodic etch-to-voltage (AETV) vol. 19, p. 175,1976. IVB-7 Capless Annealing of Ion Implanted GaAsl-A. A. Immorlica, Jr. and F. H. Eisen, Science Center, Rockwell Inter- national, ThousandOaks, CA 91360. A new technique is reported for the annealing of ion implanted GaAs. This method, which is essentially an open tube process, eliminates the necessity for sealed ampoules or intimate dielectric caps, thus greatly simplifying device fabrication in GaAs where ion implan,tation is employed. This technique is thus especially ameanable to the annealing of “thru the mask” implants used in the fabrication of integrated circuits. In this process, a layer of high purity pulverized graphite is placed on a layer of crushed GaAs and suitably baked in a Pd purified Hz atmosphere. The sample to be annealed is then placed face down in the graphite for the annealing cycle, typically 850°C for 30 minutes. The surface morphology is found to be unaffected. The activation of wafers implanted at 400 keV with 1.8 X 1Ol2 Se ions/cm2 is found to be nearly identical to that obtained with similarly implanted and annealed wafers having sputtered silicon nitride caps. Effective mobilities of 5300 cm2/V - s have been obtained, comparing favorably with the highest mobilities measured in n-type epitaxial layers with similar electron con- centrations of 1 X 1017 cm-3. Thus, the material is suitable for fabrication of field effect transistors. High dose implanted ma- terial suitable for N+ contact regions has also been annealed with this process, giving results similar to those obtainedwith material having sputtered aluminum oxy-nitride caps. Peak carrier con- centrations of -4 X l0ls cm-3 with an associated mobility of 1400 cm2/V - s have been measured forcapless annealed wafers which were implanted at 400 keV with 2 X 1014Se ions/cm2. The capless annealing process has been exploited to produce microwave device quality material. GaAs FETs with 1 pm gates have been fabricated from Se implanted, capless annealed GaAs. An optimum noise figure of 3.4 dB was measured at 10 GHz while a maximum gain in excess of 10 dB was obtained. These results No. F33615-75-C-1019. 1 This work was supported by the Air Force Avionics Laboratory under Contract Work partially supported by the Defense Advanced Research Projects Agency under Contract No. F19628-75-(2-0113.

IVB-7 capless annealing of ion implanted GaAs

  • Upload
    fh

  • View
    220

  • Download
    2

Embed Size (px)

Citation preview

Page 1: IVB-7 capless annealing of ion implanted GaAs

DEVICE RESEARCH CONFERENCE 1259

The planar GaAs devices show anomalous phenomena such as the hysteresis of I-V characteristics, current drift and substrate bias effect, which seem to originate from interface traps.l In this paper, we conclude that the anomalous phenomena are mainly due to deep centers located in the substrate near the interface at the energy above the Fermi level. The density and the acti- vation energy are estimated by measuring a current reduction and the time constants of current decay. The reduction factor of the channel current was measured by applying dc negative voltage to the back contact of the semi-insulating substrate. The width of the excess charge density in the negative space-charge region were calculated so as to make fitting to the measurement of currect reduction factors. In a typical TED, the width ranges from 0.2 to 0.4 pm and the excess charge-density from 1.5 to 8 X 1016 cm-3 when the interfacial n-i junction voltage changes from 2 to 16 V.

The channel current slowly decays after the gate voltage is switched on and recovers after it is off. The time constant was measured at various temperatures by applying a pulse technique and the activation energy was obtained. The time constant was typically 40 ps at room temperature and the activation energy was 0.44 eV. The anode dc bias also leads to slow decay of the channel current. The time constant is almost equal to that of the gate dc bias. The similar current drift was observed in GaAs FET’s made in VPE layer without a buffer layer. The activation energy of the time constant was 0.62 eV when the drain voltage was switched off and 0.65 eV when the substrate bias was switched off. The gate dc bias gave two activation energies, 0.13 eV and 0.66 eV.

The potential distribution was analyzed in the vicinity of the interfacial n-i junction in both cases with and without trap cen- ters, to show how trap centers affect the channel current. For the trap-free case, the potential drop in the active layer is in the order of magnitude of kT/q, which is too small to have an influence to the channel current. However, when there are trap centers lo- cated above the Fermi level at thermal equilibrium, as is the case of the trap around 0.44 eV, the potential drop inside the active layer becomes large and the depletion layer extends to modulate the channel current. Electron density and electric field distri- butions were calculated as a function of trap density, trap energy, carrier density and current density flowing across the interface. For instance, when the trap density is 1017 ~ m - ~ , the energy 0.44 eV, the carrier density 10l6 ~ m - ~ and the current density 6 mA/ cm2, a depletion layer extends into the active layer as deep as 0.5 pm. Thus, the current reduction factor can be calculated and be fitted to the measurement. According to the model, the excess charge density divided by the current density should be inde- pendent from the current density and this was verified by the experiments. The typical results show that the deep centers are from 1 to 4 X 1017 cm-3. The exact numerical calculations were also carried out and supported the simplified analysis.

The details of the results will be presented.

mance,” 5th Bienn. Cornell Elec. Eng. Conf., Sec. 111.3, August 1975. * J. Barrera, “The importance of substrate properties on GaAs FET Perfor-

IVB-6 An In-Situ Technique for Anodic Etch to Voltage Preparation of GaAs Read Diodes1-D. J. Coleman, Jr., Texas Instruments Incorporated, Dallas, Texas 75222 and R. L. Adms, Teledyne, MEC, Palo Alto, CA 94304.

GaAs Read diode structures employ a thin epitaxial surface layer whose thickness must be precisely controlled. The surface

layers are commonly grown thicker than necessary and etched back to the desired thickness. A self-limiting anodic oxidation technique ideally suited to accomplish this etching was recently proposed by Niehaus and Schwartz.2 However, the technique which they have reported requires many transfers of the slice between the anodic oxidation electrolyte and an etchant which dissolves the oxide. Using 0.02M N,H2P04 as an electrolyte, we have found that the oxide growth proceeds as described by Nie- haus and Schwartz with the slice anodically biased and that the oxide is removed when the slice is cathodically biased. I t is therefore possible to thin the surface layer of a GaAs Read diode slice held in situ in an electrolyte by simply reversing the polarity of the applied bias.

Sequential stages of the cathodic oxide removal process will be shown which suggest that the oxide is lifted off of the GaAs. Surface properties of the GaAs surface having undergone ca- thodic oxide removal will be discussed and compared with chemically etched surfaces. Experiments comparing the surface tension of water droplets and Pt Schottky Barrier characteristics have been performed indicating that the surface of wafers subjected to cathodic bias is not degraded for device preparation. Recent results obtained with devices fabricated by this technique will be presented.

technique for fabrication of modified Read-IMPAT’rs,” Solid-State Electronics, W. C. Niehaus and B. Schwartz, “A self-limiting anodic etch-to-voltage (AETV)

vol. 19, p. 175,1976.

IVB-7 Capless Annealing of Ion Implanted GaAsl-A. A. Immorlica, Jr. and F. H. Eisen, Science Center, Rockwell Inter- national, Thousand Oaks, CA 91360.

A new technique is reported for the annealing of ion implanted GaAs. This method, which is essentially an open tube process, eliminates the necessity for sealed ampoules or intimate dielectric caps, thus greatly simplifying device fabrication in GaAs where ion implan,tation is employed. This technique is thus especially ameanable to the annealing of “thru the mask” implants used in the fabrication of integrated circuits.

In this process, a layer of high purity pulverized graphite is placed on a layer of crushed GaAs and suitably baked in a Pd purified Hz atmosphere. The sample to be annealed is then placed face down in the graphite for the annealing cycle, typically 850°C for 30 minutes. The surface morphology is found to be unaffected.

The activation of wafers implanted at 400 keV with 1.8 X 1Ol2 Se ions/cm2 is found to be nearly identical to that obtained with similarly implanted and annealed wafers having sputtered silicon nitride caps. Effective mobilities of 5300 cm2/V - s have been obtained, comparing favorably with the highest mobilities measured in n-type epitaxial layers with similar electron con- centrations of 1 X 1017 cm-3. Thus, the material is suitable for fabrication of field effect transistors. High dose implanted ma- terial suitable for N+ contact regions has also been annealed with this process, giving results similar to those obtained with material having sputtered aluminum oxy-nitride caps. Peak carrier con- centrations of -4 X l0ls cm-3 with an associated mobility of 1400 cm2/V - s have been measured for capless annealed wafers which were implanted a t 400 keV with 2 X 1014 Se ions/cm2.

The capless annealing process has been exploited to produce microwave device quality material. GaAs FETs with 1 pm gates have been fabricated from Se implanted, capless annealed GaAs. An optimum noise figure of 3.4 dB was measured at 10 GHz while a maximum gain in excess of 10 dB was obtained. These results

No. F33615-75-C-1019. 1 This work was supported by the Air Force Avionics Laboratory under Contract Work partially supported by the Defense Advanced Research Projects Agency

under Contract No. F19628-75-(2-0113.

Page 2: IVB-7 capless annealing of ion implanted GaAs

1260 IEEE TRANSACTIONS ON ELECTRON DEVICES, NOVEMBER 1976

demonstrate that state-of-the-art device performance can be realized with capless annealed GaAs material.

In this paper, the capless annealing process will be described and the results will be presented. An explanation of the mecha- nisms involved in capless annealing will be offered, based on a comparison of photoluminescence spectra from both capless and dielectrically capped annealed wafers.

SESSION v Semiconductor Laser Devices and Reliability

V-1 Localized Gain Region GaAs/GaAlAs Injection Lasers (Invited)-G. H. B. Thompson, G. D. Henshall, J. E. A. SVhi- teaway, and P. A. Kirkby, Standard Telecommunications lAab- oratory, Harlow, Essex, England CM179NA.

The localized gain region laser is a refinement of the well es- tablished double heterostructure laser. In the double hetero- structure laser the functions of optical and carrier confinement are both performed by the abrupt increase in AMs content which occurs at the boundary between the active layer and the n- and p-type passive layers which flank it. The localized gain region laser has an extra pair of heterojunctions formed by two further AlAs content steps some distance on either side of the active layer. This produces a 5-layer double sandwich structure 'with the gain region localized to a small proportion of the op.;ical wave-guide. The function of carrier confinement is now per- formed mainly by the center active layer, and the waveguiliing mainly by the outer pair of heterojunctions. This separaticn of the functions of carrier and optical confinement gives a larger degree of design flexibility which results in lasers with perfor- mance which is superior to that of the double heterostructure.

This paper will show how the concept of the LGR laser has been utilized to produce injection lasers optimized for CW optical communication applications and for high peak pulsed ou;put power. The published results will be reviewed and the results of recent work by the authors will be given.

For CW optical communications applications it is always an advantage to minimize the threshold current density. This entails minimizing the thickness of the electrically active gain layer ,and the width of the optical distribution. The minimum thres.mold of a double heterostructure laser occurs at about 0.1 pm active region width. Below this width optical confinement begir.s to breakdown and the width of the optical distribution incremes. The active region width of the LGR laser can be made narrower than 0.05 pm, with the optical confinement provided by the outpair of heterojunctions. This produces lasers with similar optical properties to the normal d.h. laser but with lower threshold' current densities. The range 550-650 A cm-2 can be achieved reproducibly with the best units in the range 470-530 A . cm-2. If such LGR wafers are processed to produce conven- tional oxide insulated stripe geometry lasers then the low threshold current density gives a considerable advantage 1 her- mally. Such lasers have been operated CW a t temperatures up to 135OC; the maximum operating temperature was limited by the melting of the indium solder on which the device was mounted rather than the properties of the laser itself.

Designing the LGR laser for high pulsed peak output power operation is a complex problem hvolving many interrelated parameters. The design problems and some of the practical so- lutions will be reviewed. One solution which has shown success is to use a wide optical cavity (-1-2 pm) with the dielectric step on one side very small to allow only the zero order mode. The electrical active region is very narrow (4 .08 pm) and placed near the larger dielectric step. Devices such as this have been made with threshold currents well below 1000 A cm-2, emission pal tern widths below 20' and peak power limits in excess of 40 W - m rn-1.

The detailed fabrication and performance parameters of these devices will be presented.

V-2 Derivative Measurements of the Light-Current- Voltage Characteristics of (A1,Ga)As Double Hetero- structure Lasers and Comparison with the Theory of an Ideal Laser-R. W. Dixon and W. B. Joyce, Bell Laboratories, Murray Hill, NJ 07974.

It appears that derivative techniques will become quite useful in the characterization of semiconductor lasers.1.2 In this paper, a simple modulation and detection scheme for applying deriva- tive techniques to the investigation of stripe-geometry (A1,Ga)As double-heterostructure lasers is described. It is shown that modulating the current at constant modulation index (Ai/i = constant) allows the desired quantities i dV/di and i2d2V/di2 to be directly and sensitively obtained, in the same apparatus, at the first and second harmonics of the modulation frequency, respectively. Particularly strong indications of laser threshold and of other optoelectronic interactions in the laser are contained in the second-harmonic-voltage response. The same apparatus may be used to obtain derivatives of the light-current relation. These are found to sensitively reveal light-current nonlinearities which are believed due to filaments and other spatial inhomo- geneities and instabilities. This paper also clarifies the signal responses expected with the derivative techniques by calculating the fundamental and second-harmonic voltages which would be observed in the case of an ideal laser driven with a component of its current sinusoidally modulated. The previously untreated, nonanalytic, lasing-threshold region is explicitly included and the results are exact for any modulation amplitude. The harmonic voltages are then related to the first and second voltage deriva- tives and to the parameters characterizing (A1,Ga)As double- heterostructure lasers.

P. A. Barnes, Electrochemical Society Mtg., Washington, DC, May 2-7, 1976.

2 T. L. Paoli and P. A. Barnes, Appl. Phys. Lett . , to be published.

V-3 Threshold Current Variations and Optical Scattering Losses in (A1,Ga)As Double-Heterostructure Lasers-F. R. Nash, W. R. Wagner and R. L. Brown, Bell Laboratories, Murray Hill, NJ 07974.

Photoluminescence studies1 have revealed that the active layer waveguide of our (A1,Ga)As double-heterostructure laser material often contains significant local thickness variations which ac- company epitaxial growth. Angle-tap techniques have been used to provide detailed characterizations of the discrete deformities which tend to fall into two main classes, growth-terraces2 and meniscus-dissolution-lines. The waveguide imperfections may be adequately modeled by step-function thickness discontinuities (with and without missing sections of active layer), tapered thickness discontinuities, periodic variations in both waveguide thickness and direction, etc. Optical scattering losses for the model defects may be computed as functions of the parameters which detail the severity of the actual flaws. If representative values of the experimentally observed severity-parameters are incorporated into the formula for scattering losses, and these losses are in turn related to threshold current density (Jth), it is found: (i) that imperfections of the kind which we have docu- mented are predicted to unambiguously yield values of AJth/Jth of the order of tens to hundreds of percent; (ii) that, furthermore,

F. R. Nash, R. W. Dixon, P. A. Barnes, and N. E. Schumaker, Appl. Phys. Lett.,

D. L. Rode, J . Crystal Growth, vol. 27, p. 313,1974; Phys. Stat. Solidi, vol. A32, vol. 27, p. 234,1975.

p. 425,1975.