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ITRS Design ITWG 2010 1
ITRS Design + System Drivers
July, 2010
Design ITWG
Juan-Antonio CarballoTamotsu Hiwatashi William Joyner Andrew Kahng Noel Menezes Shireesh Verma
ITRS Design ITWG 2010 22011 Roadmap Work in Progress – Do Not Publish!
2
2004
2005
2006
2007
ExploreDesign metrics
Design Technology metrics
Revised Design metrics
Revised Design Technology Metrics
ConsumerPortableDriver
Consumer Stationary, PortableDrivers
Consumer Stationary,Portable,Networking Drivers
More Than Moore (MTM)analysis + iNEMI
Driver study
System DriversChapter
DesignChapter
2008
Revised Design MetricsDFM extension
Updated Consumer Stationary,Portable,and Networking Drivers
MTM extension+ iNEMI+ SW !!
2009
AdditionalDesign MetricsDFM ExtensionSystem level extension
Updated Consumer Stationary,Portable architecture,and Networking Drivers
MTM extension+ iNEMI synch+ SW !!
Overview (2004-Today)
1. Increasingly quantitative roadmap2. Increasingly complete driver set
MTMRF+AMS Driver
UpdatedConsumer,MPU, and Networking Drivers
Power roadmap chartUpgraded RF+AMS section
2010
ITRS Design ITWG 2010 3
Selected Messages 20101. Design productivity continues to be center focus of design
technology roadmap, as scaling depends on time to market• Accurate design productivity and cost models are key
2. Power consumption has become the key technical parameter that controls feasible semiconductor scaling• Power-driven device roadmap, frequency pushed to flat trend
3. More Than Moore has become a necessary component of semiconductor product scaling • Mixed SiP-SoC analog-digital drivers need to be roadmapped
ITRS Design ITWG 2010 4
Design / System Drivers 2010*-2011* Plans1. Design chapter
• Improvement of design productivity and cost models *• Develop “Power Chart” based on STRJ & productivity chart *• Ensure 3D / TSV content consistent with other chapters *• Improve DFM section, including Design for reliability rows *• Overhaul of Verification *, L/C/P sections *
2. System Drivers chapter• Update MPU frequency roadmap (flat trend), evaluate impact *• Update of SOC-CP and SOC-CS models (driven from TWGs) *• Update AMS/RF Driver / fabric with Wireless TWG *• More-Than-Moore RF+AMS driver SiP-SoC (based on SoC-P) *
3. Other Cross-TWG and public activity• PIDS: increase design-driven requirements definition *• 3D/TSV: hold for ACTION *• Continue other key interactions: A&P, Interconnect, Test *• Incorporate input from 2nd EDA Roadmap Workshop (@DAC)*
ITRS Design ITWG 2010 5
Design / System Drivers 2010*-2011* Plans1. Design chapter
• Improvement of design productivity and cost models *• Develop “Power Chart” based on STRJ & productivity chart *• Ensure 3D / TSV content consistent with other chapters *• Improve DFM section, including Design for reliability rows *• Overhaul of Verification *, L/C/P sections *
2. System Drivers chapter• Update MPU frequency roadmap (flat trend), evaluate impact *• Update of SOC-CP and SOC-CS models (driven from TWGs) *• Update AMS/RF Driver / fabric with Wireless TWG *• More-Than-Moore RF+AMS driver SiP-SoC (based on SoC-P) *
3. Other Cross-TWG and public activity• PIDS: increase design-driven requirements definition *• 3D/TSV: hold for ACTION *• Continue other key interactions: A&P, Interconnect, Test *• Incorporate input from 2nd EDA Roadmap Workshop (@DAC)*
ITRS Design ITWG 2010 6
ITRS Design Productivity RoadmapModel for upcoming Power Management Roadmap
6
IC Im
plem
enta
tion
Too
l Set
RT
L F
unct
iona
l Ver
if. T
ool S
uite
Tra
nsac
tion
Leve
l Mod
elin
g
Ver
y la
rge
bloc
k re
use
AM
P P
aral
lel P
roce
ssin
g
Inte
llige
nt T
estb
ench
Man
y C
ore
Dev
el. T
ools
SM
P P
aral
lel P
roce
ssin
g
Exe
cuta
ble
Spe
cific
atio
n
Tra
nsac
tiona
l Mem
ory
Sys
tem
Des
ign
Aut
omat
ion
Source: ITRS
ITRS Design ITWG 2010 7
ITRS Design Productivity RoadmapModel for upcoming Power Management Roadmap
7
IC Im
plem
enta
tion
Too
l Set
RT
L F
unct
iona
l Ver
if. T
ool S
uite
Tra
nsac
tion
Leve
l Mod
elin
g
Ver
y la
rge
bloc
k re
use
AM
P P
aral
lel P
roce
ssin
g
Inte
llige
nt T
estb
ench
Man
y C
ore
Dev
el. T
ools
SM
P P
aral
lel P
roce
ssin
g
Exe
cuta
ble
Spe
cific
atio
n
Tra
nsac
tiona
l Mem
ory
Sys
tem
Des
ign
Aut
omat
ion
Source: ITRS
Design ProductivityINNOVATIONS
Design Cost
ITRS Design ITWG 2010 8
ITRS Design Productivity RoadmapExpected upcoming Power Management Roadmap
8
IC Im
plem
enta
tion
Too
l Set
RT
L F
unct
iona
l Ver
if. T
ool S
uite
Tra
nsac
tion
Leve
l Mod
elin
g
Ver
y la
rge
bloc
k re
use
AM
P P
aral
lel P
roce
ssin
g
Inte
llige
nt T
estb
ench
Man
y C
ore
Dev
el. T
ools
SM
P P
aral
lel P
roce
ssin
g
Exe
cuta
ble
Spe
cific
atio
n
Tra
nsac
tiona
l Mem
ory
Sys
tem
Des
ign
Aut
omat
ion
Source: ITRS
Design for Power INNOVATIONS
Power Efficiency
ITRS Design ITWG 2010 9
SOC Modeling by Japan STRJ-WG1
ITRS Design ITWG 2010 10
Design / System Drivers 2010*-2011* Plans1. Design chapter
• Improvement of design productivity and cost models *• Develop “Power Chart” based on STRJ & productivity chart *• Ensure 3D / TSV content consistent with other chapters *• Improve DFM section, including Design for reliability rows *• Overhaul of Verification *, L/C/P sections *
2. System Drivers chapter• Update MPU frequency roadmap (flat trend), evaluate impact *• Update of SOC-CP and SOC-CS models (driven from TWGs) *• Update AMS/RF Driver / fabric with Wireless TWG *• More-Than-Moore RF+AMS driver SiP-SoC (based on SoC-P) *
3. Other Cross-TWG and public activity• PIDS: increase design-driven requirements definition *• 3D/TSV: hold for ACTION *• Continue other key interactions: A&P, Interconnect, Test *• Incorporate input from 2nd EDA Roadmap Workshop (@DAC)*
ITRS Design ITWG 2010 112011 Roadmap Work in Progress – Do Not Publish!
11
Design and System DriversITRS-iNEMI Domain Space
Chip level System level
Techrequirements
Marketrequirements
iNEMI(emulators)
ITRS(Drivers)
*Source: ITRS Design/System Drivers TWG Chairman, Dr. Juan-Antonio Carballo
ITRS Design ITWG 2010 12A&DNetwork ConsumerPortable
OfficeMedical Automotive ConsumerStationary
MPU
PE/DSP
AMS
Memory
Fabrics
Markets
20062007 2006 20062010?2010?
SIP
New System Drivers? At the right pace…
• Is SIP a new fabric ?• What application is the right driver for (leading edge) 3D/TSVs ?
2010?
?
ITRS Design ITWG 2010 13
ITRS-iNEMI Domain SpaceSiP-SoC More-than-Moore Proposal
Chip level System level
Techrequirements
Marketrequirements
Portable emulator
RF/AMS Driver
Portable consumer
driver1 2 3
Update portable driver
Update portable emulator
PA Case Study(SoC v. SiP)
ITRS Design ITWG 2010 14
h
An Alternative Driver Tuner / Demodulator
Inclusion of AMS/RF sub-driver from ITRS AMS driver
Equivalent cost = NRE + non-NRE per-board cost
14
Power (SiP)
Power (SoC)
Equivalent cost (SoC)
Equivalent cost (SiP)
Tuner-demod case Study
Requirement Description
Tuner Resolution, operating freqs, power
ADC/DAC #bits, order, power, etc.
Demodulator/FEC decoder
Gain-bandwidth, power
Additional “rows” for combined analog-digital model
ITRS Design ITWG 2010 15
SOC Modeling by Japan STRJ-WG1
ITRS Design ITWG 2010 16
Power-Constrained Frequency Scaling Intrinsic frequency scaling + activity scaling 13% per year
Still exceed 150W in 2015 2009:
– To meet market needs frequency growth limited 8% per year 2010 (expected):
– To meet market needs / additional constraints: flat YTY trend
8% frequency scaling
Power < 150W
ITRS Design ITWG 2010 17
Cross-TWG Interaction: Design-PIDS Device speed scaling: HiPerf CV/I improves by 13%/year
– Use “headroom” for further power savings? Three devices in the ITRS roadmap
– High Performance (HP): Highest Ion and Ioff, lowest CV/I– Low Operating Power (LOP): Lowest VDD, medium Ion, Ioff and CV/I– Low Standby Power (LSTP): Lowest leakage, low Ion, high CV/I
Design providing guidance as to targeted ratio of device characteristics– Preferred order of dynamic power: LOP < LSTP << HP– Preferred order of leakage power: LSTP < LOP << HP
Ratio of HP : LOP : LSTP
R1
R2
R3
Parameters
Target design freq.(GHz)
Device CV/I
Device Ioff
INPUT
FEEDBACK
Application driven Technology driven
Design Group PIDS Group
ITRS Design ITWG 2010 18
Design / System Drivers 2010*-2011* Plans1. Design chapter
• Improvement of design productivity and cost models *• Develop “Power Chart” based on STRJ & productivity chart *• Ensure 3D / TSV content consistent with other chapters *• Improve DFM section, including Design for reliability rows *• Overhaul of Verification *, L/C/P sections *
2. System Drivers chapter• Update MPU frequency roadmap (flat trend), evaluate impact *• Update of SOC-CP and SOC-CS models (driven from TWGs) *• Update AMS/RF Driver / fabric with Wireless TWG *• More-Than-Moore RF+AMS driver SiP-SoC (based on SoC-P) *
3. Other Cross-TWG and public activity• PIDS: increase design-driven requirements definition *• 3D/TSV: hold for ACTION *• Continue other key interactions: A&P, Interconnect, Test *• Incorporate input from 2nd EDA Roadmap Workshop (@DAC)*
ITRS Design ITWG 2010 19
h
ITRS-iNEMI MTM SOC/SIP Design/IntegrationUpdate of ITRS and iNEMI Portable Drivers
Inclusion of AMS/RF sub-driver from ITRS AMS driver
Equivalent cost = NRE + non-NRE per-board cost19
Other AMS
PA (RF)
Power (SiP)
Power (SoC)
Equivalent cost (SoC)
Equivalent cost (SiP)
PA Case Study
ITRS Design ITWG 2010 20
Gaps in EDA (IEEE DAC Roadmap Workshop 2010
20
Technology
EDA nature
Metrics
ITRS Design ITWG 2010 21
Selected Messages 20101. Design productivity continues to be center focus of design
technology roadmap, as scaling depends on time to market• Accurate design productivity and cost models are key
2. Power consumption has become the key technical parameter that controls feasible semiconductor scaling• Power-driven device roadmap, frequency pushed to flat trend
3. More Than Moore has become a necessary component of semiconductor product scaling • Mixed SiP-SoC analog-digital drivers need to be roadmapped