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Open Issues in the SoCDesign

IES 2006

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Panelists

Pierre BRICAUD Synopsys

Gal CLAVE Texas Instruments

Jean-Franois DUBOC FITechno

Robert de SIMONE INRIA

Charles ANDRE University of NICE

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IES2006

Panel: Open Issues in SoCDesign

Pierre Bricaud

Director, R&DSolutions Group

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Targeted SoC Set Top Box

BootRom

CPU + DSPCustomBlock

EthernetEthernet PHYPHY

1394 PHY

InterruptController

UART

AMBA AHB

AMBA APB

Arbitration& Decode

& Mux

GPIOWatchdog

Timer

AHB/APBBridge

SDRAM

I/F

AHB/PCIeBridge

USB 2.0

USB 1.1 Ethernet

SATA1394a

USB PHY

PCI Express

PCIe PHY

SATA PHY

VIPVIP VIPVIP

VIPVIP VIPVIP

VIPVIP

VIPVIPVIPVIP

VIPVIP

VIPVIP

InterruptInterrupt

ControllerController

UARTUART

AMBA AHBAMBA AHB

AMBA APBAMBA APB

ArbitrationArbitration

& Decode& Decode

& Mux& Mux

DesignWareElements

GPIOGPIOWatchdogWatchdog

TimerTimer

AHB/APBAHB/APBBridgeBridge

SDRAMSDRAM

I/FI/F

AHB/AHB/PCIePCIeBridgeBridge

USB 2.0USB 2.0 EthernetEthernet

SATASATA1394a1394a

USB PHYUSB PHY

PCI ExpressPCI Express

PCIe PHYPCIe PHY

SATA PHYSATA PHY

EthernetEthernet PHY

C fi bili i C i i l &

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U

SB

F

irewire1394

PCI

PCIExpress

D

VI/HDMI

F

astEthernet

G

bEthernet

S

ATA

AMBA

OCB

G

PIO

A

udio

E

JTAG/Deubg

U

ART

A

TA/IDE

8

02.11

B

luetooth

W

irelessUSB

P

rocessor

M

icro-controller

S

DRAM

D

DRSRAM

L

PSDRAM

S

RAM/Flash

Configurability is Critical &

Complex

Cell Phones

PDAs

MP3 Players

DVD

PVR/TivoSet-top box

Digital TV

Games station

Digital Camera

Camcorder

Printer/Scanner

PC/PC Motherboard

LAN Switch

XX

X XXX

X

XX

X

XX

X

XX

X

XX

X

XX

X

XX

XX

X

XX

X

XX

X

X

X

X

X

X

X

X X

X X X X

XXX

X

XX

X

X

X

XX

X

X X X

XX X X

X

X

X X XX X

X

X

XX

X

XX

X

XX

XX

XX X X

X

X X XX X X X

X X XX XX X XX X

X X

XX XX

XX X

XX XX X

X

X

X XX X

X X

X

X

M

obileStorage

XX X

X

X XX

X

X

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DAC StudyWhat is the biggest challenge for the IP User of the future?Integration

Quality

Verification

Qualifying IP

Cost

Lack of Stds

Timing

ReuseVendor Relationships

0% 5% 10% 15% 20% 25%

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What are the solutions ?

All Industry Successful High Volume SoC

are based on Industry Standards. Applications Standards ( Set Top BoxDVD

Mobile Phones)

IP Interconnect/InterOperability ( SPIRIT IPXACT)

IP Quality ( VSIA QIP )

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Issue

Why are there so littleUniversities/Research OrganisationsAssociate Members in StandardOrganisations ?

VSIA CNRS Brazil , STARC

SPIRIT STARC

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IndustrialEmbedded Systems 2006

Gael Clave TI -W TBU

1 0 .2 0 0 6

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IES-06 : New Challenges for SoC The new SoC generation shows a very large content ofembedded Sw with OSs, Multimedia codes, Cryptos,

Modems , Software Define Radio , Power Management,which are supported by more and more complex platforms.

A convergence between Hw and Sw communities createsnew needs in term of input formalism and specifications.

The ever growing SW sizes and multicores platforms areasking for advance modeling technologies and ultra highspeed simulator.

Time to Market to implement new standards or upgradefeatures pave the way for Behavioral Synthesis.

Verification as usual is the bottleneck.

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IES-06 : New Challenges for SoCInput formalism and specifications:Beyond fashions, the reality is a deep disconnect between Sw and Hw

development methodologies and languages.

The Java wave is gone away for SW, the ubiquitous SystemC is therefor HW.modeling.

Most of used SW code running on a SoC platform are written in C or

C++ .All Hw is described using HDL Vhdl/Verilog. This Hw may be either nonprogrammable and only need parameterization sequences as DMAcaches or programmable/reconfigurable/networked as Cpu arrays

within a NoC.

How to federate these needs in a common framework?

How to bridge?

How to partition Sws between Cpus and wired FUs

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IES-06 : New Challenges for SoCModeling and simulation:

A simple link setup when a telephone is powered up may take 10sec

with 2 Cpu cores running at 250Mhz plus massive Hw accelerator.

Sw simulation speed requirement for a full SoC platform is now in therange of 10 to 100Mips/per core with more demand on cycle accuracy.

Early architecture tradeoff to handle all system uses-cases and grantperformances push the modeling effort up front a SoC development.

Which formalism allows very early architecture description withSystemC/RTL co-generation?

How to spin off easily a Cpu ISS, regenerate its tool kit and refresh theSoC model?

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IES-06 : New Challenges for SoCImplementing Sw standards:

The multimedia Sw requirement in wireless applicationforce SoC developers to off load regular Cpu cores indedicated Hw or dedicated cores.

Behavioral Synthesis technologies have now reach anindustrial quality and challenge handcrafted Hw toimplement C based data flow in wired Hw.

Routing the data through the SoC is always the most powerconsuming task

How to partition Sw in multicore environment andreconfigurable data routing?

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Low Power and design Reuse

Jean-Franois DUBOC

www.fitechno.com

Contact@fitechno.com

http://www.fitechno.com/http://www.fitechno.com/

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Reusability background

Design Reuse is 10 years old

It appears with the general usage of embedded

processors and standard interfaces

It generates rules like synchronous design, bi-

directional busses . It was the way to

Keep control of project schedule while complexity

increase Minimize risk

Control development cost

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How was handle low power?

For technologies above 90 nm, leakage currents werenegligible

Goal was to stop the clock in a block or sub part ofsystem when this part was not used

Gated clock strategy driven by software Automatic detection by hardware in processor cores

Instruction decoding in pipeline allows to enable the

clock in the units which are used by instructionexecution

Register controlled by embedded processor Writing to a bit in a register enables or disable the

clock in the block No limitations for Design Reuse of IPs

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What has changed

Below 90 nm, leakage currents have thesame magnitude than current than dynamiccurrent when a block is used

Stopping the clock is not enough

Power supply has to be cut to really avoid

leakage current Requires physical isolation

How to handle context saving

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Power isolation

When the power is cut in a block, its I/O candischarge the transistors in the neighborhood

The bloc has to be physically decoupled by theusage of level shifters on each I/O

Challenge:

In each system, the isolation of an IP can be different(used alone in one device, with other blocks in another one)

Level Shifters are analogue cells and the back enddesign becomes mixed signal back end design,increasing complexity and issues

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Context Saving

If a block has to be initialized before anyusage, there is no issue

Between two burst mode, a GSM chip has no

activity but has to restart very quickly onregular basis: Complete reset not acceptable

Keep power all the time is not acceptable Methodology: Keep power in some parts of the registers to save

the context

Transfer thru serial link context to an alwayspower on part of the design and restore in thesame way

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Conclusion

Power isolation is system specific and willimpact any IP on each usage

Context saving will depend of the block, thesystem where it is used, various modes ofthe system .

IP and Design Reuse are less easy thanbefore

Work to be done for any IP reuse acrossvarious designs