Is Ple Verv 31 Release Notes for Pc

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ispLEVER Release Notes

Version 3.1 - PC

Technical Support Line: 1-800-LATTICE or (408) 826-6002

Web Update: To view the most current version of this document, go to www.latticesemi.com.

LEVER-RN-PC 3.1.2 (Supersedes Rev 3.1.1)


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ii ispLEVER 3.1 Release Notes - PC

Copyright

This document may not, in whole or part, be copied, photocopied, reproduced,

translated, or reduced to any electronic medium or machine-readable form without

prior written consent from Lattice Semiconductor Corporation.

The software described in this manual is copyrighted and all rights are reserved byLattice Semiconductor Corporation. Information in this document is subject to change

without notice.

The distribution and sale of this product is intended for the use of the original purchaser

only and for use only on the computer system specified. Lawful users of this product

are hereby licensed only to read the programs on the disks, cassettes, or tapes from

their medium into the memory of a computer solely for the purpose of executing them.

Unauthorized copying, duplicating, selling, or otherwise distributing this product is a

violation of the law.

Trademarks

Copyright (c) 2003 Lattice Semiconductor Corporation.

Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation (logo), L

(stylized), L (design), Lattice (design), LSC, Beyond Performance, E2CMOS,

FIRST-TIME-FIT, GAL, Generic Array Logic, In-System Programmable, In-System

Programmability, ISP, ispATE, ispDesignEXPERT, ispDOWNLOAD, ispGAL,

ispGDS, ispGDX, ispGDXVA, ispJTAG, ispLEVER, ispLSI, ispMACH, ispPAC,

ispSOC, ispSVF, ispTURBO, ispVIRTUAL MACHINE, ispVM, LINE2AR, MACH,

MMI (logo), ORCA, PAC, PAC-Designer, PAL, PALCE, Performance Analyst,

Silicon Forest, Speedlocked, Speed Locking, SuperBIG, SuperCOOL, SuperFAST,SuperWIDE, UltraMOS, V Vantis (design), Vantis, Vantis (design), Variable-Grain-

Block, and Variable-Length-Interconnect are either registered trademarks or

trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United

States and/or other countries. ISP is a service mark of Lattice Semiconductor

Corporation.

GENERAL NOTICE: Other product names used in this publication are for

identification purposes only and may be trademarks of their respective companies.

Lattice Semiconductor Corporation

5555 NE Moore Court

Hillsboro, OR 97124

(503) 268-8000

November 2003


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ispLEVER 3.1 Release Notes - PC iii

Limited Warranty

Lattice Semiconductor Corporation warrants the original purchaser that the Lattice

Semiconductor software shall be free from defects in material and workmanship for a

period of ninety days from the date of purchase. If a defect covered by this limited

warranty occurs during this 90-day warranty period, Lattice Semiconductor will

repair or replace the component part at its option free of charge.

This limited warranty does not apply if the defects have been caused by negligence,

accident, unreasonable or unintended use, modification, or any causes not related to

defective materials or workmanship.

To receive service during the 90-day warranty period, contact Lattice Semiconductor

Corporation at:

Phone: 1-800-LATTICE or (408) 826-6002

E-mail: [email protected]

If the Lattice Semiconductor support personnel are unable to solve your problem over

the phone, we will provide you with instructions on returning your defective software

to us. The cost of returning the software to the Lattice Semiconductor Service Center

shall be paid by the purchaser.

Limitations on Warranty

Any applicable implied warranties, including warranties of merchantability and

fitness for a particular purpose, are hereby limited to ninety days from the date of

purchase and are subject to the conditions set forth herein. In no event shall Lattice

Semiconductor Corporation be liable for consequential or incidental damages

resulting from the breach of any expressed or implied warranties.

Purchaser’s sole remedy for any cause whatsoever, regardless of the form of action,

shall be limited to the price paid to Lattice Semiconductor for the Lattice

Semiconductor software.

The provisions of this limited warranty are valid in the United States only. Some states

do not allow limitations on how long an implied warranty lasts, or exclusion of

consequential or incidental damages, so the above limitation or exclusion may not

apply to you.

This warranty provides you with specific legal rights. You may have other rights which

vary from state to state.


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iv ispLEVER 3.1 Release Notes - PC


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ispLEVER 3.1 Release Notes - PC v

Contents

ispLEVER 3.1 Release Notes - PC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1New Features and Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

New Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

New Production Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Preliminary Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Software Installation Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Project Navigator Enhancements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

Revision Control Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Project Archiving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

LPC Source File Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Query for Synthesis Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

View and Edit Unrelated Files When a Process is Running . . . . . . . . . . . . . . . . . . . 5

Console for Running the ispLEVER software from the Command Line. . . . . . . . . . 5

ispVM Icon on the Tool Bar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

ISC-1532 File Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

New Reentrant Feature for ORCA4 and Above. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Text Editor Enhancements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Wheel Mouse Scrolling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Syntax Color Customizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Boundary Checking for Parenthesis, Brackets, and Braces . . . . . . . . . . . . . . . . . . . . 7

File > New VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

ispXPLD 5000MX Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Constraint Editor Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Fast Bypass Value Change for ispXPLD 5000MX Devices . . . . . . . . . . . . . . . . . . . 8

Multiple Columns Sorting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Nodal Constraints Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Verify Bank Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Multiple Signals Selection & Pin Locking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

New Global Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Preference Editor for ORCA Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Module/IP Manager Support for ispXPLD Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Expanded Source Constraints Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

LVDS Macro Support for ispXPLD 5000MX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

http://-/?-http://-/?-


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ispLEVER 3.1 Release Notes - PC vi

Enhanced CPLD Unified Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Floorplanner Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

EPIC Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Performance Analyst Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Online Documentation Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

The ispLEVER Software Documentation Library . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Comprehensive Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Restructured Help Toolbars and Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

ORCA Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

ORCA FPSC Kit Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

ORCA PROM Generation Command Line -t Option Usage. . . . . . . . . . . . . . . . . . . . . . .20

Use of GSR/PUR in Verilog for ORCA4 and Later Libraries . . . . . . . . . . . . . . . . . . . . 20

Ability To Run Multiple Versions of the ispLEVER Software. . . . . . . . . . . . . . . . . . . . 20

Known Issues and Solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Constraint Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Floorplanner. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23ispLSI Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

ispVM Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

ispXPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

ispXPLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Lattice Logic Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

legacy2lci. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Module/IP Manager. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Online Help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

ORCA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Performance Analyst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Place and Route . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Preference Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Project Navigator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38


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ispLEVER 3.1 Release Notes - PC 1

ispLEVER 3.1 Release Notes - PC

This section describes the ispLEVER™ software support for Lattice CPLD,

ispXPLD, ispXPGA, and ORCA FPGA devices. The following topics are discussed

in this section:

❑ New Features and Enhancements

❑ Known Issues and Solutions

New Features and EnhancementsNew features and enhancements are available in the ispLEVER 3.1 software. The

following topics are discussed in this section:

❑ New Device Support

❑ Software Installation Changes

❑ Project Navigator Enhancements

❑ Text Editor Enhancements

❑ Constraint Editor Enhancements

❑ Preference Editor for ORCA Designs

❑ Module/IP Manager Support for ispXPLDs

❑ Expanded Source Constraints Support

❑ LVDS Macro Support for ispXPLD 5000MX

❑ Enhanced CPLD Unified Report

❑ Floorplanner Enhancements

❑ EPIC Enhancements

❑ Performance Analyst Enhancements

❑ Online Documentation Enhancements

❑ Use of GSR/PUR in Verilog for ORCA4 and Later Libraries

❑ ORCA PROM Generation Command Line -t Option Usage

❑ Ability to Run Multiple Versions of the ispLEVER software


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4 ispLEVER 3.1 Release Notes - PC

Option to Show/Not Show Revision Window in the Project Navigator. In the

Environment Options dialog box, you have an option (Figure 2) to close the Revision

window whenever Revision Control is turned off. To display the Environment Options

dialog box, click Options > Environment.

Figure 2. Option to Show/Not Show Revision Window

Project Archiving

File > Archive Current Project and File > Open Archived Project are two new

commands in the Project Navigator. You can use them to save your project to a .zip

archive, and reload it as necessary.

LPC Source File Support

For ispXPLD, ispXPGA, and ORCA designs, the Project Navigator has been

enhanced to support a Lattice Parameter Configuration File (*.lpc) as source file.

The LPC file contains the configuration parameter data that has been selected using

the Module/IP Manager. This file is used to order custom IP configurations from

Lattice.

You can import an LPC file into the Project Navigator and double-click it for quick

editing. For more information, see “Importing a Module/IP Source” and “Modifying

a Source in Module/IP Manager” in Project Navigator Help.


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Query for Synthesis Tool

Each time you create a new Verilog or VHDL design, the Project Navigator now

prompts you to choose a synthesis tool (Figure 3). You can keep the default synthesis

tool selected in the prompt dialog box, or choose the other tool for the new project.

Figure 3. Query for Synthesis Tool

View and Edit Unrelated Files When a Process is RunningWhen running a process in the Project Navigator, you can open other source files

unrelated to the process in any text editor for viewing and editing.

Console for Running the ispLEVER software from the Command Line

Window > ispLEVER Console is a new command in the Project Navigator. You can

use this command to open a command line prompt window if you want to run the

ispLEVER software from the command line.

ispVM Icon on the Tool Bar

An ispVM icon (Figure 4) has been added to the Toolbar of the Project Navigator.

The icon is equivalent to Tools > ispVM System.

Figure 4. ispVM icon

ISC-1532 File Process

For ispGAL22V10A, ispLSI 2KVE/VL, MACH 4A, ispGDXVA, ispGDX2,

ispLSI 5000VE, ispMACH 4000, ispMACH 5000B, ispMACH 5000VG,

ispXPLD 5000MX devices, you can use the newly-added process “ISC-1532 File” to

convert any ISP programmable part’s JEDEC to an ISC format that supports IEEE

1532 standard.


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New Reentrant Feature for ORCA4 and Above

This new process allows you to use a routed physical database (.ncd) file as the

starting point for running additional routing iterations. This process is available for

ORCA4 and FPSC devices.The process is highlighted (Figure 5) in the Project

Navigator Processes Window.

Figure 5. Reentrant Route Design Process for ORCA4 and Above


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Text Editor Enhancements

The following enhancements are available in the Text Editor.

Wheel Mouse Scrolling

Wheel mouse scrolling is supported.

Syntax Color Customizing

The Text Editor displays different syntax elements with different colors to improve

readability. Click Options > Set Color. You can then customize colors in the Set

Color dialog box (Figure 6).

Figure 6. Set Color Dialog Box

Boundary Checking for Parenthesis, Brackets, and Braces

The Text Editor has been enhanced to monitor parenthesis ( ), bracket [ ] and brace

{ } constructs in a text file. You can match an opening parenthesis, bracket, or brace

with a closing one, and vice versa. For details, see “ Matching Parenthesis, Brackets,

and Braces” in Text Editor Help.

File > New VHDL

This new menu command in the Text Editor opens a VHDL template. The template

automatically creates entity and architecture pairs, making VHDL source creation

easier.


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Multiple Columns Sorting

You can sort multiple columns of lists in the Data Sheet pane of the Constraint Editor

via the newly-added Sort dialog box (Figure 7). The list will be sorted first by the

column specified in the Sort by box, then by the additional columns in the Then by

boxes in sequence. To display the Sort dialog box, click View > Sort in the Constraint

Editor.

Figure 7. Sort Dialog Box

Nodal Constraints Sheet

For ispLSI 5000VE, ispMACH 4000, ispMACH 5000B, ispMACH 5000VG, and

ispXPLD 5000MX devices, you can set nodal constraints using the Constraint

Editor’s Nodal Constraints sheet.

Choose Tools > Nodal Constraints in the Project Navigator, and the Constraint Editor

will open with the Nodal Constraints sheet only. You can set constraints for individual

output and node signals in the sheet, save the settings and go back to the Project

Navigator.

The Nodal Constraints sheet is not available for normal Constraint Editor flow.


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Verify Bank Setting

Pin Attribute > Verify Bank Setting is a new command in the Constraint Editor. Use

this command to check the current bank setting and to display the check results in a

pop-up window. If the current device of your project has no bank, this command is

disabled.

Multiple Signals Selection & Pin Locking

The Constraint Editor lets you select multiple signals in the Element List pane and Pin

Attributes sheet, or select multiple pins in the Package View by using the Shift and

Ctrl keys.

You can also drag and drop multiple signals from the Element List pane to the desired

location in the Package View for locking multiple pins at the same time.

New Global ConstraintsThe following two global constraints have been added to the Global Constraints sheet

of the Constraint Editor. They are supported by ispLSI 5000VE, ispMACH 4000,

ispMACH 5000B, ispMACH 5000VG, and ispXPLD 5000MX devices.

Auto_buffering_for_high_glb(mfb)_fanin. Defaults to “Off.” If you set it to “On” in

the Constraint Editor, the automatic buffer insertion function is enabled to reduce the

total input number to a GLB/MFB when the AND array input number exceeds the

device limitation.

Clock_enable_optimization. Defaults to “keep_all.” Listed below are the threeoptions of this constraint and their descriptions:

Wrap_all – No clock enable is used. The software folds clock enable into

register data equation.

Keep_all – If the number of clock enable product terms is greater than the

maximum clock enable PT limit of the target device, the software will insert

clock enable nodes, otherwise it just keeps the clock enable equation.

Auto – If the number of clock enable product terms is greater than the

maximum clock enable PT limit of the target device, the software will wrap

the clock enable equation into register data equation to avoid a timing delay

issue, otherwise it just keeps the clock enable equation.


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Preference Editor for ORCA Designs

The Preference Editor (Figure 8) is a dedicated tool for ORCA FPGA designs. It lets

you specify many ORCA preferences, thus saving the time it normally takes to write

out preference syntax manually to the preference file (*.prf

). The Preference Editorreads the PRF file and displays the preference settings. You can use the Pin Attributes

sheet and the function dialog boxes to define groups, pin locations, IO types, as well

as various timing preferences such as MULTICYCLE, BLOCK, PERIOD,

FREQUENCY, INPUT_SETUP, and CLOCK_TO_OUT. You can also make pin

assignments in the Package View using drag-and-drop functionality.

Preference Editor is available pre-map and post-map. Editing IO types is only

available pre-map, so attributes associate with IO types are not visible in the post-map

preference editor. Groups (available both pre- and post- map) allow definition of cell,

port, or ASIC groups for use in timing preferences. For example, a group of all flip-

flops which share a particular clock is easily defined. Timing between groups can bespecified using MULTICYCLE or BLOCKed.

The Preference Editor only supports Lattice ORCA FPGA device families. For

designs of other Lattice devices, use the Constraint Editor.

For more information, choose Help > Help Topics in the Preference Editor.

Figure 8. Preference Editor


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Module/IP Manager Support for ispXPLD Devices

Module/IP Manager now supports ispXPLD devices (5KMX) with seven new Lattice

Parameterized Modules (LPMs). EBR modules for ispXPLD include:

❑ CAM

❑ FIFO_DC

❑ FIFO_DCX

❑ RAM_DP

❑ RAM_DP_TRUE

❑ RAM_DQ

❑ ROM

Figure 9. Module/IP Manager


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Expanded Source Constraints Support

More source constraints are supported. Most Lattice constraints can be added into

your schematic or ABEL design source files.

LVDS Macro Support for ispXPLD 5000MX

This release of the ispLEVER software supports LVDS macros for ispXPLD

5000MX device family.

Enhanced CPLD Unified Report

The HTML format report file for all CPLD families has been enhanced as follows:

Added a field to the Device Resource Summary section for Usable

Macrocells/Product Terms

Added Totals field at the bottom of the GLB Resource Summary section

Added a column for IO Bank Number in the Pinout Listing section

Added a column for Fan In per macrocell in the GLB Cluster sections

Added a single line indicating the number of signals per GLB in the GLB

Logic Array Fanin sections

Added a column to the GLB Logic Array Fanin sections that indicates thefanout load inside the GLB for each signal


20/44


Floorplanner Enhancements

A separate Floorplanner interface has been added for ORCA FPGA devices. The

ORCA Floorplanner displays a completely separate window for the Package, Pre-

Mapped, Post-Mapped, and Floorplan views.

Figure 10. ORCA FPGA Floorplanner

The appropriate view opens automatically from the Project Navigator when you run

one of the following processes:

Pre-Map Logical Design Floorplan. This process opens only the Pre-Mapped View,

allowing you to create logical groups (Ugroups) before mapping the design. The

changes that you save are applied to the logical design file (.ngd).

Post-Map Physical Design Floorplan. This process opens all four Floorplanner

windows. Any Ugroups that you created in the Pre-Mapped Floorplan are converted to

physical groups (Pgroups). You can create other Pgroups, make pin assignments, and

specify regions before placing and routing the design.

Post-PAR Design Floorplan. This process opens all four windows for the placed and

routed design. You can make further adjustments to the design and rerun the Place and

Route process.


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EPIC Enhancements

Enhancements for EPIC (Editor for Programmable ICs) include:

❑ GUI enhancements to the EPIC Main Window.

❑ Menu reorganization.

❑ New-look push button panel.

❑ Improved Objects dialog box with wildcard filtering feature.

❑ Layers dialog auto-toggles layers on check boxes.

❑ Green dashed boundary lines show viewable area in Editing Area.

❑ Locator area features new boundaries for active area and cross-hair zoom-in

feature.

❑ Improved zooming and panning capability in Editing Area.

❑ New EPIC Start dialog box has been added. The EPIC Start dialog box appears

after you start the EPIC program independently or when you launch EPIC

initially from within Project Navigator.

Figure 11. EPIC Enhancements


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Performance Analyst Enhancements

❑ Improved filtering functionality in Timing Analysis type option dialog boxes.

❑ Delay Table enhancements.

New corresponding MHz value column

New Delay Constraint column that displays closest timing constraint

New Slack column that displays difference between real and required delay

Constraint ID column that displays the matching timing constraint ID in the

.lct file for fMAX timing analysis.

❑ New Path Tracing Options and point selection dialog functionality for tP2P

timing delay type.

❑ New Preferences > Save GUI Settings command that allows you to maintain

preferred dialog box sizes and fonts.

❑ New information on timing constraints available in Delay Table columns, for

example, now shows slack or difference between real delay and required delay.

Figure 12. Improved Performance Analyst GUI


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Online Documentation Enhancements

The ispLEVER Software Documentation Library

The ispLEVER software Documentation Library provides links to all Online Help,

User Guides, Release Notes, Installation Notice, Application Notes, Tutorials, Legacy

Manuals, and Third-Party Manuals. You can view this list by selecting it from the

Project Navigator Help menu or by clicking Library in the toolbar.

Figure 13. The ispLEVER Software Documentation Library


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Comprehensive Glossary

The Online Help now features a comprehensive glossary of terms commonly used

with the ispLEVER software. You can view the Glossary by selecting it from the

Project Navigator Help menu or by clicking Glossary in the Toolbar.

Figure 14. Glossary

Restructured Help Toolbars and Menu

Help toolbars and the Project Navigator Help menu have been restructured to giveyou quick access to online and printable documentation. From the Help toolbar of

each application, click the appropriate button to access the Flow Help, Document

Library, or Glossary.

Figure 15. Help Toolbar


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ORCA PROM Generation Command Line -t Option Usage

Previously, the –t option required a file argument:

promgen -p exo -t 256 orca.bit

However, now it is a separate parameter. To do the same action, do the following:

promgen -p exo -t 256 -u 0 orca.bit

Use of GSR/PUR in Verilog for ORCA4 and Later Libraries

The global set/reset function in front-end Verilog simulation for ORCA Series 4 and

higher must be done differently than in prior architectures. To ensure propersimulation, it is necessary to instantiate GSR, PUR, and TSALL elements in your

designs which contain any library elements that are affected by them.

For instance, when you instantiate a flip-flop, for example, that is affected by global

set/reset in front-end Verilog netlists, then you must instantiate the GSR and PUR

elements in the top-level module with the instance names GSR_INST and PUR_INST,

respectively. Similarly, for any output or bidirectional buffer instantiation, you must

instantiate TSALL with the instance name TSALL_INST.

The example below shows proper syntax for instantiating GSR and PUR elements:

GSR GSR_INST (.GSR ());

PUR PUR_INST (.PUR ());

The example below shows proper syntax for instantiating TSALL:

TSALL TSALL_INST (.TSALL ());

Ability To Run Multiple Versions of the ispLEVER Software

The new ispLEVER user interface allows you to use 3.1 and previous version without

the need to reset the environment variables. Refer to the “ispLEVER Installation

Notice Version 3.1 - PC” document for more information on running multiple

versions of the ispLEVER software.


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Known Issues and Solutions

Constraint Editor

Issue: Routing of memory blocks and arithmetic functions to I/O pins is highly

restrictive. It is very difficult to manually assign pins for these functions so that

the assignments will be compatible with the device architecture. Incompatible

pin assignments are likely to cause the fitter to fail to partition the design.

Workaround: First, let the design run through the software flow without any pin locking.

This allows the fitter to choose compatible placement for the functions (you

should allow the fitter to run without any pin locking constraints until you

absolutely have to lock down the pinout). Second, backannotate the pin

assignments (the location assignments of the memory and arithmetic will be

automatically written into the constraints file) as you continue to make changes

to your design. This gives the fitter a known compatible placement of these

functions.

Devices Affected: ispXPLD 5000 MX

Issue: The “Disable” right-click drop-down menu command is visible in the

Constraint Editor Package View for CPLD devices, but the command is not

applicable for CPLD Devices, and should not be used.

Workaround: Ignore the “Disable” right-click drop-down menu command when viewing

CPLD devices in Constraint Editor Package View.

Devices Affected: CPLD

Issue: IO_TYPES attribute is not supported for ORCA devices.

Workaround: Use LEVELMODE instead of IO_TYPES attribute for ORCA devices.

Device Affected: ORCA FPGA and FPSC


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Issue: When you try to save changes to the project’s constraint file (.lct) using the

Constraint Editor, a message instructs you to close the other application that

has the LCT file open. This message appears after you’ve attempted to import

the .lct file.

Workaround: Do not try to import the .lct file.

Devices Affected: All

Issue: The following warning messages appear in the Constraint Editor output panel

after fitting a design, backannotating constraints, and then running the Post-Fit

Pinouts process in the Project Navigator.

C:\ispTOOLS31_starter\ispcpld\examples\ispXPLD\Veril

og\test_ramdq16kx2\test_ramdq16kx2.lco : :

IO Types Setting ’Reset’ : bank setting ’2’ is

conflict with Pin locking.

C:\ispTOOLS31_starter\ispcpld\examples\ispXPLD\Veril

og\test_ramdq16kx2\test_ramdq16kx2.lco : :

IO Types Setting ’Reset’ : bank setting ’2’ is

conflict with Pin locking.

Loading Lattice Constraint File

’C:\ispTOOLS31_starter\ispcpld\examples\ispXPLD\Veri

log\test_ramdq16kx2\test_ramdq16kx2.lco’ done!

Workaround: None. Ignore the warnings.

Device Affected: All

Floorplanner

Issue: The pins on the ASIC (non-FPGA core) side of an FPSC device are fixed, but

the Floorplanner allows them to be moved via drag and drop. The placer will

issue a warning and disregard the invalid assignment.

Workaround: None needed.

Devices Affected: FPSC


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Issue: If you right-click in the Package View in the Floorplanner, the pop-up menu’s

Package Property command displays the Package Property dialog box.

However, the Package Property dialog box does not give any information

about the properties of the selected device.

Workaround: To view package properties of the selected device, in the Project NavigatorSources window, double-click the target device icon to open the Device

Selector dialog box. The Device Selector dialog box contains package property

information, such as family and speed grade.

Devices Affected: ispXPGA

Issue: Some features on the right edges of Floorplan View in the Floorplanner may

not be visibible if you zoom in.

Workaround: None.


Installation

Issue: EPIC can crash with a message saying the system is running low on virtual

memory.

Workaround: Before running the EPIC software, increase the range of virtual memory on

your local computer to accommodate the EPIC software and any other

applications that you will be running simultaneously.

Devices Affected: ORCA FPGA

Issue: The Synplify software license agreement goes blank when the Synplify

software is started for the first time.

Workaround: In the Synplicity software, choose Help > License Agreement to view thelicense agreement.



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Issue: The “Lattice Semiconductor Setup Program” window is minimized as an icon

at the bottom of your screen after you click the "Finished" button at the end of

installation. If you click the “Lattice Semiconductor Setup Program” icon at

the bottom of your screen to enlarge the window, the window can appear to

“hang.”

Workaround: Don’t click the “Lattice Semiconductor Setup Program” icon at the bottom of

the screen after you click the "Finished" button, and don’t manually attempt to

stop the installation process. Allow the InstallShield program to completely

install the ispLEVER software. The icon at the bottom of the screen will

disappear by itself when the installation is complete.


Issue: When installing ispLEVER software on a client server that has never had v3.x

(v3.0 or v3.1) ispLEVER software previously installed on it, the Product

Options dialog box will only have one checkbox choice named Starter.

Workaround. Select the Starter checkbox option and click Next to continue with

installation.


ispLSI MacrosIssue: When an ispLSI Macro with OE port is used for an ispLSI5000VE

VHDL/Verilog design, a BLO file is generated. This causes design failure. The

following macros are involved:

Workaround: Do not use the macro in such a design. Use the behavior description instead.

Devices Affected: ispLSI 5000VE

OT11 OT14 OT18

OT21 OT24 OT28

OT31 OT34 OT38

OT41 OT44 OT48


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ispVM Software

Issue: You will receive an error message with Code 001 if you attempt to run the

ispVM software from the Project Navigator and the ispVM software is not

installed.

Workaround: Ensure the ispVM software is installed before running ispVM software from

the Project Navigator.


ispXPGA

Issue: When LVDS sysIO Type is configured for a clock signal, ispXPGA preventsthis setting from being placed on an I/O pin because of possible skew that will

degrade the LVDS signal. You can assign a normal clock to an I/O pin. Any

LVDS type clock signal needs to be assigned to a GCLK pin. This causes a

warning message from the ispXPGA placer. However, the warning incorrectly

specifies “BLVDS” type instead of “LVDS” type.

Incorrect Error Message:

F51104: Clock signal Clk0_nside$implicit_buf

with BLVDS sysIO type cannot be assigned to an I/O

pin.It must be assigned to a GCLKn pin.

F54031: Proper placement of sysCLOCK instance

failed.

Message should be:

F51104: Clock signal Clk0_nside$implicit_buf

with LVDS sysIO type cannot be assigned to an I/O

pin.It must be assigned to a GCLKn pin.

F54031: Proper placement of sysCLOCK instance

failed.

Workaround: Replace the “BLVDS” with “LVDS” in the error message.



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Issue: For Module FIFO_DC, the EDI/EDO feature will not work in functional RTL

Verilog simulation. VHDL simulation works.

Workaround: None.

Device Affected: ispXPGA

ispXPLD

Issue: VHDL examples cause errors due to unknown LC5KMX library when RTL

synthesis is switched to Synplicity. The errors are caused by the LC5KMX

library which is primarily used for logic simulation.

Workaround: Add a directive “Translate_off/Translate_on” in the source. The

usage of this directive can be found in the Synplicity for Lattice Reference

Manual. (From the Project Navigator, choose Help >ispLEVER

Documentation Library >Third-Party Manuals.)

Usage:

The use of these directives is to prevent the synthesis of stimulus source code

that only has meaning for logic simulation. You can use

Translate_off/Translate_on to skip over simulation-specific lines

of code that cannot be synthesized.

Syntax and Example:

library IEEE;

use IEEE.std_logic_1164.all;

-- synthesis translate_off //Anything below this

would be skip during synthesis

LIBRARY lc5kmx;

USE lc5kmx.components.all;

--synthesis translate_on //Now..anything below this

are now synthesizable

.....

.....

Device Affected: ispXPLD 5000MX


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Lattice Logic Simulator

Issue: When using the Lattice Logic Simulator, you can get incorrect simulation

results for Functional Simulation of a D flip-flop and associated logic.

Discussion: The Lattice Logic Simulator will take the D signal value at thetime just prior to the clock edge and reflect that value after the transition of the

clock. In a functional simulation, the data and clock edges will most likely

occur at the same time. In order to catch possible race states in a functional

simulation, the D state just prior to a clock edge is considered in a stable state.

By sampling the data signal prior to the clock edge, the Lattice Logic

Simulator can emulate a setup time requirement similar to a timing simulation.

Workaround: Adjust the test bench stimulus to transition the data prior to the clock edge or

run the timing simulation.

Device Affected: CPLD

Issue: When you simulate a sub-block of a design using the Lattice Logic Simulator,

the functional simulation process sometimes displays incorrect logic

information.

Workaround: When the clock and data change at the same time for a register, you can

simulate using the previous value or future value of the D port. The Lattice

Logic Simulator uses the previous value known as the t- approach. You can

change the stimulus to prevent the conflict and show a correct value. Or you

can run timing simulation, and the timing simulation can show you the correct

value.

Devices Affected: CPLD and ispGDX


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legacy2lci

Issue: When converting ispDesignEXPERT files using the legacy2lci conversion

tool, the pin names in the LCT file are all capitalized and the ABEL source

code signal pin names are not. The ispDesignEXPERT software created the Pinfile using all capital letters. The ispLEVER fitter cannot correlate the LCT files

to the ABEL Signal names causing it to ignore the pin locks. The legacy2lci

tool will give the following warning message when running on this type of

project:

“WARNING: The pin names do not preserve case-sensitive names, may cause

warnings in ispLEVER.”

Workaround: 1. Change the PPN file names to reflect the case of the ABEL signal names;

or

Go back to ispDesignEXPERT and change case sensitive property to True

and regenerate your pin file.

2. Run the legacy2lci tool to convert the pin names correctly for ispLEVER.

Devices Affected: All devices supported in the ispDesignEXPERT software


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Module/IP Manager

Issue: When using Module IP/Manager for pipelined multiplier, the D-flops used for

pipeline can only have the reset as global reset. The routed reset is not

available.

Workaround: None


Issue: When generating a CAM, RAM, or ROM module in Module/IP Manager, a

memory initialization file is created with a .mem extension. This MEM

extension must be removed for ispXPLD.

Workaround: Remove the MEM extension on ispXPLD CAM, RAM, or ROM memoryinitialization files. To open a memory initialization file in Module/IP Manager

for ispXPGA CAM, RAM, or ROM modules, in the Files of Type box of the

Open dialog box, select All Files (.*.). and open the file.

Devices Affected: ispXPLD

Issue: A FIFO 512x32 memory block, with 28 or less data outputs can be

implemented with one MFB. The software currently uses two MFBs to

implement the memory block. The data portion of the FIFO is placed in one

MFB and the FIFO Flag logic in a second MFB. The portion of the second

MFB not used for the FIFO flag logic is available for non-memory logic

function placement.

Workaround: None

Devices affected: ispXPLD 5000 MX

Issue: Numerous ORCA module and FPSC CORE dialog boxes have non-

functioning links to datasheets.

Workaround: Click on Help button for more information on modules and FPSC cores. More

information on all modules and cores, including data sheets, brochures, and

downloads, can be found on the Lattice Semiconductor Corporation web site at

the following URL:http://www.latticesemi.com/products.

Devices Affected: ORCA FPGA and FPSC


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Issue: A synchronous FIFO with some parameters (or any other block using a

ROM16X1 element) generated for an ORCA4 device with Module/IP

Manager can cause an error message when run through the Project Navigator

ORCA design flow. The error states that there is a problem converting ROM

init.

Workaround: This is a problem with Synplicity 7.3.3. The initval attributes in the Verilog

HDL or VHDL source code should be written in the form “OxAEAE.”

However, Synplicity writes the initval attribute in the form “OxOxAEAE” for

ROM16X1 elements for ORCA 4. Edit the HDL source code to remove the

extra “Ox” and re-run the design flow in Project Navigator. Later versions of

Synplify, such as 7.5.3, should fix this problem.

Devices Affected: ORCA4

Online Help

Issue: Clicking the Help button on the ispUPDATE dialog box produces a dialog box

that displays the following error message:

Cannot find the ..\..\ispcpld\bin\concepts.hlp file.

Do you want to try to find this file yourself?

Workaround: Click No in the error message dialog box. Navigate to the

..\isptools\ispcpld\bin directory, and manually open the

flow.hlp file. Click the Help Topics button in the toolbar, expand any of theFlow books, expand the Introduction book, and select the “Updating

ispLEVER from the Web” topic.


Issue: Adobe Acrobat documents (.pdf) may not display artwork correctly if using a

version of Adobe Acrobat Reader that is older than version 4.0.

Workaround: Install Adobe Acrobat Reader 4.0 or higher to view PDF documents.



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ORCA

Issue: Before you perform a JTAG Read and Save operation on an ORCA4 or FPSC

device, you must first instantiate the BNDSCAN library element into your

design, enable the appropriate bitgen settings, and program the device.

Workaround: In the Project Navigator:

1. Using a text editor, instantiate the BNDSCAN library element into your

design.

2. In the Processes window, right-click the Generate Bitstream Data process

and select Properties.

3. In the Properties dialog box,

- Select JTAG After Configuration from the Properties list, and then

Select True from values list at the top of the dialog box.

- Select Allow Readback from the Properties list, and then select

Command from the values list.4. Click Close.

5. In the Processes window of the Project Navigator, click the Bitstream

Data File process.

In the ispVM System:

6. Add the ORCA4 or FPSC device, set the chain operation to Program and

Verify, and select the Bitstream Data file generated by Project Navigator.

7. Choose Project > Download to program the device.

8. After the device has been programmed, set the chain operation to Read and

Save.9. Choose Project > Download to perform the Read and Save operation.



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Issue: There two versions of bitgen in the ispLEVER software: one for CPLD devices

located under \ispcpld\bin, and one for ORCA

devices under \ispfpga\bin\NT. The Project

Navigator will always use the correct version of bitgen, depending on your

project. However, when running ispLEVER programs via command line in

ispLEVER Console for ORCA devices, the CPLD bitgen will be selectedbecause the default path points to \ispcpld\bin first.

Workaround: To use the ORCA bitgen using command line, you must first manually set

\ispfpga\bin\NT in the PATH.


Issue: For better compatibility with simulators, all negative setup/hold delay numbers

in the Standard Delay Format (.sdf) file are set to 0 by default. This may

cause some discrepancies between back annotation and the TRACE (trce)

timing analysis result.

Workaround: Use the new -neg option to get the negative numbers in the SDF file and back

annotation will match the TRACE report. But make sure that the simulator will

be able to handle negative numbers in the SDF file. For example, the following

command generates Verilog netlist and SDF file without setting the negative

setup/hold delays to 0:

ldbanno -neg -n verilog design.ncd



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Performance Analyst

Issue: When running Performance Analyst, when there are no timing paths for a

specific analysis type in a design (e.g. tCOE), and an option is enabled by

opening the Options dialog box and clicking OK, the Performance Analystmay exit abruptly. If the enabled option does provide timing paths, then

Performance Analyst works as expected. If the enabled option does not provide

any timing paths, then Performance Analyst does not inform you that no timing

paths exist, and exits abruptly.

Workaround: If the enabled options in the Options dialog box do not provide timing paths

and Performance Analyst exits abruptly, simply restart Performance Analyst

from Project Navigator.

Device Affected: ispXPGA

Place and Route

Issue: Input registers should be assigned automatically for the M4A devices, but it is

possible that no input registers will be assigned. This is due to the fitter

requirement that all GLBs have a consistent macrocell to pin ratio, such as

16/8. In some M4A devices, the ratio in one GLB may be different than the

ratio in another GLB. Therefore, the input registers will not be assigned

properly for this device.

Workaround: You can target the M4A3512/256 device and reserve pins so that the pinout of

the desired device is meet. You can then program the M4A3-512/160 device,

or the M4A3-512/192 device, using the M4A3-512/256 JEDEC file. Contact

Lattice Technical Support to obtain a constraint file with the correct pins

reserved for the device being used.

Devices Affected: ispMACH4A3-512/160 and ispMACH4A3-512/160


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PLL

Issue: PLL implementation of Schematic/Verilog PLL design is incorrect for

ispMACH 5000VG. Though the design compiles correctly, the fitter report

shows that one of the internal nodes is automatically forced by the software asan output. Though signals appear in the report correctly, the summary shows

that another output is generated: the internal node has become an output and

the output is locked to a specific pin.

Workaround: None.

Devices Affected: ispMACH 5000VG

Issue: If the PLL clock output is connected to logic, it should also be connected to a

pin. This will not introduce extra pin usage because the PLL clock output canbe connected to logic only through the pin feedback.A buffer is not considered

logic. If the PLL clock output is connected to a pin through an inverter, an

extra clock output connection to a pin is not needed, unless the output of the

inverter has a fanout greater than 1.

Workaround: None

Devices affected: ispXPLD 5000MX

Preference Editor

Issue: Pin locate attributes defined in the HDL are not visible in the post-map

Preference Editor. These preferences are between SCHEMATIC

START/SCHEMATIC END statements in the post-mapped preference file

(.prf). Place and route will honor pin locates from HDL, and using Preference

Editor to set pin locates (including overriding those from HDL) will also be

honored. Similarly, frequency attributes defined in the HDL are not visible in

the Preference Editor.

Workaround: To make HDL preferences visible in the Preference Editor post-map, use Edit

Constraints (ASCII) or any text editor to move these preferences to after the

SCHEMATIC END statement. They will then be visible in the Preference

Editor.



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Project Navigator

Issue: Source files opened, and then saved, in Text Editor could fail to generate

database if blank spaces are left in the file name.

Workaround: Don’t leave blank spaces in file names of source files saved in the Text Editor.

Devices Affected: All Devices

Issue: When trying to view the JEDEC file by selecting the JEDEC File process in

the Processes for Current Source pane of the Project Navigator, and right-

clicking on the view option, the JEDEC (.jed) file will not be displayed. This

option is not supported for the MACH4A, or MACH5 devices.

Workaround: None. The view JEDEC option is not supported. View the JEDEC file with atext editor.

Device Affected: MACH4, MACH5 and ispMACH4A

Issue: When a new project is created in the same directory as an existing project, the

revision control for the old project appears in the Revision Control window.

Workaround: None. Do not create multiple projects in the same directory when Revision

Control is enabled.

Devices Affected: ispXPGA, ORCA FPGA

Issue: CDR and FIFO are not supported in the Lattice Logic Simulator.

Workaround: Use ModelSim simulator.

Devices Affected: ispGDX2


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Issue: When a register signal drives a RAM/FIFO/CAM block and at the same time

outputs to a pin, it will cause a failure during timing analysis and Standard

Delay File (.sdf) file generation.

Workaround: The failure can be prevented by preserving the register signal in the design

source code. The following examples show a workaround for a VHDL design:Exemplar:

Attribute preserve_signal: boolean;

Attribute preserve_signal of reg_out: signal is true;

Attribute OPT : string;

Attribute OPT OF reg_out : SIGNAL IS "KEEP";

Synplicity:

Attribute syn_keep: boolean;

Attribute syn_keep of reg_out : signal is true;

Attribute OPT : string;

Attribute OPT OF reg_out: SIGNAL IS "KEEP";

Where signal reg_out is the Q output of the register that drives the memory

block.

Devices Affected: ispXPLD 5000MX

Issue: If you import a preference (.prf) file into Project Navigator, and the device

type is industrial, the PRF file must explicitly include the INDUSTRIAL

keyword. Otherwise, correct timing parameters will not be used.

Workaround: After a PRF file is imported, open it using the Edit Constraints (ASCII)

process, and add keyword INDUSTRIAL;


Issue: The ispLEVER software aborts if you import a Verilog Test File (.tf) and then

attempt to display any Verilog Simulation Properties dialog box.

Workaround: Before displaying any Verilog Simulation Properties dialog box, save the

project by choosing File > Save in the Project Navigator.

Device Affected: All


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Issue: If you to run the ISC-1532 File process in ispLEVER Project Navigator

without having the ispVM System software installed on your computer, you

will receive an error message.

Workaround: Ensure that you have the latest available version of the ispVM System software

installed on your computer before running the ISC-1532 File process inProject Navigator.

If you are using ispLEVER Starter software, you must download the ispVM

software from the www.latticesemi.com website, and install the ispVM

software in your \ispTOOLS directory

Devices Affected: All IEEE 1532 compliant devices.


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Revision History

This version of ispLEVER 3.1 Release Notes for PC contains updated information that is not contained

in the original printed version of the document that comes with the software.

Changes include:

Page 22 - A known issue was added describing warning messages that are generated in Constraint

Editor when backannotation is performed.

Page 23 - A known issue was added describing problems with Floorplanner Package View dialog box.

Page 23 - A known issue was added describing a problem with zoom feature of Floorplanner floorplan

view.

Page 23 - A known issue was added describing a problem with viewing the Synplicity License

Agreement during software installation.

Page 24 - A known issue was added describing a a possible problem with the “Lattice Semiconductor

Setup Program” icon during software installation.

Page 24 - A known issue was added describing a problem with the Product Options dialog box during

software installation on a client server.

Page 30 - A known issue was added describing a problem with synchronous FIFOs generated for

ORCA4 devices with Module/IP Manager when Synplicity v.7.3.3 is used as the synthesis tool.

Page 37- A known issue was added describing how an error message is generated in Project Navigatorif you run the ISC-1532 File process without having first installed the ispVM System software.

Documents

Is Ple Verv 31 Release Notes for Pc