IRT NaNoelec 2017...Accélérateur d’innovation pour les PME“ book 50 SMEs and 15 partners in countries other than France In 2017, 33 new affiliate partners, including 28 small

TECHNOLOGICAL RESEARCH INSTITUTE

IRT NaNoelec 2017Scientific & technical report

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IRT NANOELEC scientific & technical highlights 2017

France created its Technology Research Institutes (IRT) in 2012 as an instrument of the government’s economic stimulus package. The institutes’ mission is to develop

new technologies and the associated industrial manufacturing capabilities to boost the economic competitiveness of industrial companies in France and other European countries. Obtaining state-of-the-art scientific and technological research results is the first step toward achieving this goal.

Maintaining the highest standards of quality is particularly relevant to IRT Nanoelec, which operates in a field—integrated circuits—where competition and the creation of effective value chains are international. As in previous years’ reports, the 2017 report provides a review of our main scientific publications and technological advances, and it also benchmarks the results of two major IRT Nanoelec programs, 3D Integration and Silicon Photonics, against the international state of the art.

The year 2017 also saw the start of a new program at IRT Nanoelec. This program addresses the now crucial issue of energy management and, specifically, the development of gallium nitride power components on silicon. Inside you will find an explanation of the broader context of this new program, which is expected to produce results at the international state of the art in 2018. As in previous years, IRT Nanoelec achieved excellent scientific results in materials and process characterization, leveraging access to unrivalled resources like the Synchrotron and a neutron reactor.

In terms of transferring microelectronics technologies to industry, the Easytech program, which specifically targets SMBs, helping

Michel WolnyDirector, irt nanoelec

Director’S foreWorD

SuMMary

them to integrate digital technology into their products and services, continued to grow. At end-2017 more than 200 Easytech projects had been completed since the program’s inception in 2012. The PULSE program, which helps businesses take advantage of microelectronics to develop innovative products and services, entered the final stage of its shift toward digital trust, which began in 2016.

Finally, IRT Nanoelec continued its work to ensure that tomorrow’s businesses will have access to the know-how they will need for their future recruitments by implementing new training modules that respond to the needs expressed by IRT Nanoelec partner companies. The new training modules also align more closely with IRT Nanoelec’s current technology development programs to maximize synergies.

1 Director’s foreworD

5 3D integration program

19 silicon photonics program

31 powergan program

37 characterization on large-scale instruments program

51 pulse (uses of integrateD systems anD support for companies) program

61 easytech program

67 eDucation & training program

72 irt nanoelec technological platforms

74 irt nanoelec training platform


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2 KEy FIgURES

Partners in the consortium Effective integration of 1 new partner in 2017: Almae

20FTE (full-time equivalents)engaged in IRT Nanoelec projects

185

Companies created to develop and commercialize IRT Nanoelec R&D

3 Products highlighted in the “IRT Nanoelec Accélérateur d’innovation pour les PME“ book

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SMEs and 15 partners in countries other than France

In 2017, 33 new affiliate partners, including 28 small - to mid-sized Enterprises, kicked off joint projects with IRT Nanoelec

147

Patents filed and 13 software applications registered

In 2017 IRT Nanoelec filed 20 patents and registered 3 software applications

108

Scientific and technical articles and papers published

In 2017 IRT Nanoelec researchers published 62 scientific and technical articles and papers, more than 96% of which were in international journals/at international conferences

272

Affiliate partners engaged in or having completed joint projects with IRT Nanoelec (these partners include)

191

Million annual mean operating budget

50

Key figureS eNd 2017

EU projects16Participation in


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The objective of 3D Integration program is to develop a platform gathering major aspects of the manufacturing chain, as most generic as possible but meantime developed

to be compatible with some specific applications. It requires experience in technology, circuit architecture, EDA tools, packaging and test. Another objective is to facilitate the access to 3D Integration technology. For that reason, the platform is widely open to new partners and to external partners. The innovation is the key to position IRT 3D Integration program at the top of the international state-of-the-art. Innovative technologies and architectures are developed, in accordance with the industrial specifications. These technological modules are validated on pioneer technical demonstrators, this realization being an important objective of the partners to validate and highlight all the generic developments done in the program.Development are focused around 3D technologies for Imager and for High Performances Computing.CEA-Leti, STMicroelectronics, Mentor graphics, EVg, and SET are the partners of the 3D integration program.

Séverine cheraMy 3D integration prograM Director

3D integrationprograM


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WorlDWiDeBenchMarK

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3D for image sensor

Since 2012 and the release

of the very first 2-dies product

by Sony (Exmor RS 3D-imager,

8M 1.5µm large pixels, integrated in

the Sony Xperia Z and in the Apple

IPhone 5S smartphones), all major

players, from fabless to foundry

and IDM, have published some

work or even some products on 3D

integration for image sensor.

Sony’s state-of-art (as pioneer in

such integration) offers a good

overview of worldwide benchmark.

After the release of the Exmor RS

3D-imager, Sony then released

a non-TSV 3D imager, using direct

hybrid bonding (chip-to-chip

interconnect pitch reduction

to 6µm) which is in production

in Samsung galaxy 7. Recently,

Sony also released in 2017 the very

first prototype of a 3-layers imagers,

by stacking a layer of memory

(DRAM) in between the imager

and the logic dies, and using

a TSV-based interconnect

technology.

Additionally, if the first concept

of 3D stack imagers was a TSV

connection outside the pixel array,

it seems that latest developments

are oriented toward an image

parallel processing.

Techinsight released in 2017

the following table, showing

that large players have already

developed and industrialized

stacked imagers. Public reverse

engineering studies prove

that almost all products are using

wafer-to-wafer direct hybrid

bonding technology except Sony

2013 product (Exmor 3D imager,

TSV interconnect) and Sony 3-layers

2017 prototype (TSV interconnect).

Since the start of IRT Nanoelec program, STMicroelectronics and CEA-Leti

developed a cost-effective solution based on direct hybrid bonding

for ultra-fine pitch wafer-to-wafer (< 5µm). EVg also joined the consortium

to support and speed this strategy.

A major part of the 3D integration Nanoelec program is focused

on technology development for 3D-stacked imager, included a pioneer

technology demonstrator called “Harmony”.

Sony exmor RS 3d stacked cMoS imager

cross-section of the cu TSV array

Sony, ISScc 2017 - First 3-layers imagers (BSI/dRaM/logic) - TSV based interconnect

Sony (chipworks analysis, March 2016)

3D INTEgRATION PROgRAM

chip Vendor year stacked cis foundry/gen.

stacked isp foundry/gen.

Sony 2013 Sony 90 nm Sony 65 nm

Sony 2014 Sony 90 nm TSMC 40 nm

Sony 2016 Sony 90 nm TSMC 28 nm

OmniVision 2015 XMC 65 nm XMC 65 nm

OmniVision 2016 TSMC 65 nm TSMC 65 nm

Samsung 2015 Samsung 65 nm Samsung 65 nm

Samsung 2016 Samsung 65 nm Samsung 28 nm HKMG

Sony ISSCC 2017 90 nm CIS* 30 nm DRAM* 40nm ISP*

* announced Feb 2017. Table 2. Noteworthy Stacked chip cIS/ISP configurations


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3D for computing and Data center

Top challenges for High Performance Computing applications are:

1 - Reaching exascale computing as soon as possible;

2 - Increasing data traffic (x2 every 2 years is expected); and

3 - Lower energy per operation (÷ 4 every two years).

Till now, designers used to develop their components in advanced

node to meet those HPC requirements. Nevertheless, considering

chips daRPa Program 2016 (development of interface in active interposer for modular stacking)

aMd: exascale Heterogeneous Processor (chiplet on active interposer)

aSTaR (2016) PeTRa (2013)

Traditionally, the main driver

for HPC application is Intel,

and the transition towards

3D advanced packaging solutions

is depicted as follow:

Other players also believe

in photonic interposer to speed

data transfer, reduce total power

and ease chip floorplan design and

global packaging (Hewlett Packard

Enterprise), but the work is in

the early phase of development.

Some proofs of concept have

already been published by labs

(PETRA in 2013 with a Si-Photonics

interposer, ASTAR in 2016 with

a Si-Photonics die with TSVs

stacked on a digital interposer).

Major players have already

mentioned the Si-Photonics

interposer as a new game changer

in their roadmap (CISCO, IBM,

Ericsson, Xilinx, Luxtera).

Furthermore, as far as data center application is concerned, the constant

increase of telecommunication flow all over the world put a critical

emphasis on the most critical nodes of the global network: the bandwidth

and energy efficiency performances of data centers. To meet data center

performance requirements (currently 40 to 100 gb/s, next 400 gb/s

then 1 Tb/s), the optical data flow from fibers has to come closer and

closer to the digital chip. By introducing optical transceiver functions

in the package, as close as possible to the digital IC I/Os, System-in-Package

and 3D integration bricks are seen as key enablers.

all challenges adding the fact

that cost design is dramatically

unfordable for majority of HPC

players, going to modular stacking

by using chiplet on a performant

silicon interposer is now of high

interest. As passive interposer

also reaches some limits in terms

of performance, active interposer

has recently gained more interest,

as per figures below:

Trend towards usage of silicon

interposer for High Performance

Application is clear; this trend

reinforces the choice done in

the IRT 3D program. Indeed, we

considered that silicon interposer

has the advantage to achieve

challenging dimensions and

the possibility to integrate more

functions than only routing passive

tracks to keep a strong advantage

over organic substrates.

It is why we are investigating

a platform interposer architecture

and generic technologies that

can address challenges of a silicon

interposer. This platform will gather

some of the technologies that could

address any silicon based interposer,

whatever it is passive, active or

photonic.



10 11


2017 hIghLIghTs


as far as imaging application is concerned, “Harmony” technical demonstrator aims,

starting by an existing architecture, to push the limit of the interconnect pitch

to 1µm using wafer-to-wafer hybrid bonding (industrial state of the art is the range

of 4 to 6 µm). This demonstrator is a 2-stacked dies (Back-Side Illumination Sensor

stacked on logic die) at a very aggressive pitch.

In 2017, development of the wafer-to-wafer hybrid bonding has been pursued,

reaching a capability of 1µm pitch on metallic wafers (world-wild first).

The functional batch is ongoing and have been bonded at the end of 2017 by eVG.

Packaging and functional test are scheduled by mid-2018.

Finally, the new machine from SeT,

targeting very accurate die-to-wafer

direct hybrid bonding with a 500 to

1000 dies per hour, has been qualified

and installed at cea-leti. early tests

are very encouraging, as shown

in publications released end of 2017.

a new opportunity raised in 2017 about photonic interposer, leading to the definition

and the design of a new test vehicle, “Thetis”. The technological development already

achieved for Intact (TSV, interconnect, TSV to Beol compatibility) will be largely

reused (after tuning) for the photonic interposer. “Thetis” embeds many electrical

& optical test structures to characterize 3d interconnects on a photonic silicon

interposer.

Schematic view of Intact interposer

Schematic view of Harmony demonstrator characterization of the alignment after bonding

SeT Fc1 prototype machine in cea-leti clean room

The focus of the program is put on the most challenging 3d technologies that are for energy efficient high performance

applications and the 3d vertical scaling. all those applications require high interconnect density, large chip size with mechanical and thermal aware solutions. applications considered are High Performance computing (HPc) and data center from one hand, and on the other hand imaging solutions and low power 3d devices.

“Intact” is a technical demonstrator of the program targeting HPc applications.

The demonstrator Intact embeds a manycore architecture, some computing

clusters with a hierarchical memory l1, l2 and l3, and manufactures in FdSoI 28nm

technology. 6 chiplets are stacked on the interposer.

In 2017, some path-finders full functional wafers have successfully passed the Feol,

TSV and Beol integration while back-up batches are in the TSV-Middle root.

In parallel, some metallic wafers have successfully followed the copper pillar pitch

20µm root, followed by packaging development. Some early characterizations of

the 3d interconnects have been published (electrical dc and RF, as well as reliability).

as far as the chiplet is concerned, the design have been completed (FdSoI 28nm)

and embedded in a ST MPW and then, some first wafers are completed, with the

copper-pillar pitch 20µm (reduced by 2 compared to state-of-the-art) integration

for a high density chiplet to interposer interconnect. early functional tests have been

done with the stand-alone chiplet which prove the performance of the architecture

as well as its scalability.

an applicative demonstration was prepared in parallel, corresponding to a Pc facility,

including 2 FPGa circuits, all necessary interfaces and several periphery outputs.

The full functional demo with the Intact circuits is scheduled end of 2018.

optical view of TSV in Intact interposeur


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Key publications in 2017

K. Morot, a. farcy, th. lacrevaz,

c. Bermond, h. Jacquinot,

p. Scheiblin, ph. artillan, B. flechet

“3D interconnect optimization for

Single channel 100-gBps transmission

in a photonic interposer”-

21st Workshop on Signal and power

integrity (ieee - Spi), May 7-10, 2017

lake Maggiore (Baveno) italy

High speed 3d interconnects are a key

element in 2.5d interposer technology

that is widely investigated for high

performance applications. a wide-band

electrical modeling and optimization

method of the photonic interposer

interconnect chains is presented using

scalable models developed based

on electromagnetic simulations.

Highly scalable 3d-chain models

have been developed and validated

up to 100 GHz. Models application

in optimization procedure leads

to significant improvement of electrical

network performances in photonic

interposer. 100 Gbps digital signal

provided by optical outputs can be

efficiently transmitted through electrical

chains. Transverse length for die-to-

substrate communication has been

increased by 100% through technology

and design optimization of TSV-Rdl

link and 25% through line design

optimization of Beol-TSV-Rdl chain.

J-h. choy, a. Kteyan, v. Sukharev, S. charterjee, f.n najm and S. Moreau

“finite-difference Methodology for electromigration analysis applied to 3D

ic test Structure: Simulation vs. experiment” - 22nd international conference

on Simulation of Semiconductor processes and Devices (ieee-SiSpaD 2017),

September 7-9, 2017 Kamakura (Japan)

This paper presents a novel electromigration (eM) assessment method based

on a finite-difference (Fd) approach witch has been implemented to study eM

degradation in 3d integrated circuits. The flow has been successfully employed

for predicting eM failures on a 3d Ic test-structure with redundancy: failure sites

and lifetimes predictions are in good agreement with experimental results.

Stress evolution based eM assessment is the only approach that can be used

for the predictive analysis of eM-induced degradation in complex interconnect

and packaging power delivering structures.

The results demonstrate that the eM induced MTF in 3d Ic structures can be

correctly predicted with Fd simulations, by representing them as combinations

of 1d interconnect branches with suitable boundary conditions (Bc) for the

branch junctions.

D. gitlin, M. vinet, S. cheramy, h. Metras, o. faynot, th. Signamarcheix,

J.r lequepeys “generalized cost Model for 3D Systems”- Soi-3D-Subthreshold

Microelectronics technology unified conference (ieee- S3S), october 16-19,

2017 San francisco (uSa).

This paper present a generalized cost model for 3d systems that is applicable

to both sequential and parallel 3d system integration. It takes into account yield

multiplication effects in the case of sequential integration, and also reflects

the additive nature of the cost for parallel integration.

For large dies, chip-on-wafer solution is preferable. For small dies, 3d economical

equation is very challenging. Wafer to wafer is preferable, compared to chip

to Wafers.


S. cheramy “3D Stack roadmap and technology” - coolcubetM / 3DvlSi open

Workshop october - 17, 2017 San francisco (uSa)

This presentation highlight the possibility from leti and IRT Nanoelec platforms

to offer a complete 3d process integration covering TSV and hybrid bonding

developments. For 3d stack, the 3d integration program in now moving to the next

stage of technology development (wafer to wafer and chip to wafer including

self-assembly technique).

o. faynot “towards high Density 3D interconnections” - european 3D tSv Summit,

January 23-25, 2017 grenoble france

This paper presents the use of 3d high density integration for a Beol-like approach

based on possibilities offered by ultrafine pitch hybrid bonding (1µm and less

is reachable) and a Feol-like approach based on coolcube™ and possibility

of reaching few dizains of nanometers of pitch.

Mains applications of these development are for image sensor and computing.

S. lhostis “hybrid Bonding toolbox for 3D image Sensor”-

european 3D tSv Summit – January 23-25, 2017 grenoble france

The paper demonstrates the advantage of 3d stacked process for Image sensor

future developments (Back Side imagers). The hybrid bonding processes are now

robust (processes under control) and the advantages of hybrid bonding have been

demonstrated (footprint, power, speed …).


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Q. Struss, p. coudrain, J. p colonna, a. Souifi, c. gontrand and l. frechette

“embedded vapor chamber in Microelectronic Devices”- 20th Journées nationales

du réseau doctoral en Micro-nanoélectronique (JnrDM 2017), november 6-8, 2017

Strasbourg (france)

The goal of this project is to propose a performant chip cooling and thermal

homogenization solution, more efficient than current passive heat spreaders

and compact enough to be compatible with an integration in mobile devices.

The presented solution consists in a so-called “vapor chamber”, a passive phase change

cooling system directly integrated in the backside of the silicon substrate of a chip.

J. Jourdon, S.Moreau, D. Bouchu, S. lhostis, n. Bresson, D. guiheux, r. Beneyton,

S. renard and h. fremont “effect of passivation annealing on the electromigration

properties of hybrid Bonding Stack” - international reliability physics Symposium

(ieee – irpS), May 2-6, 2017 Monterey (uSa)

This paper presents electromigration results on a hybrid bonding-based test vehicle

to study the impact of bonding and passivation annealing on back end of line

(Beol) robustness. Black’s parameters extraction leads to typical values of cu-based

interconnects. electromigration lifetime remains the same, whatever the bonding

annealing conditions but a significant influence of passivation annealing is observed.

chemical analyses evidence the effect annealing atmosphere. a discussion is lead

on the chemical species concentration at different locations of the stack and the

reduction of the Time to Failure with passivation final annealing. We show that there

is no specific failure mode is induced by hybrid bonding process step whatever

the bonding anneal temperature.

p. Metzger, n. raynaud, a. Jouve, n. Bresson, l. Sanchez, f. fournel, S. cheramy

“toward a flip-chip Bonder Dedicated to Direct Bonding for production

environment” - 14th international Wafer level packaging conference (iWlpc)

october 24-26, 2017 - San Jose (uSa)

The purpose of this paper is to demonstrate the performance of a fully automated

die-to-Wafer bonder, SeT Fc1, specifically designed for direct bonding. It will be

demonstrated that a throughput over 900 dph (dies per hour) with an accuracy

of +/-1µm can be reached today. If progresses still need to be done, the particle

contamination is low enough to enable the 1st demonstration of oxide/oxide

die-to-Wafer direct bonding. These first harvest of measures has been done at SeT

facilities. They are very encouraging as precision is in the range of ± 1 µm and

throughput is close to 500 dph. cleanliness seems to be at an acceptable level

to permit to achieve direct bonding with good adhesion of chips onto wafer.

l.M collin, J.p colonna, p. coudrain, M.S. Shirazy, S. cheramy, a. Souifi, l.g fréchette

“hotspot aware Microchannel cooling add-on for Microelectronic chips in Mobile

Devices”- the intersociety conference on thermal and thermomechanical

phenomena in electronic Systems (ieee- itherM), May 30, June 2, 2017

orlando (uSa)

This work proposes an experimental microchannel solution to cool microelectronic

chips with hot spots, using a non-intrusive technique. an experimental add-on

cooling approach with direct fluidic contact at the back side of the chip has been

investigated. It showed that the different tested microchannel or fin layouts only

had a secondary role compared to the stacking configurations in the global thermal

performance. only the cavity without microchannel showed significantly higher

thermal resistance for the cold plate configuration. The proposed solution is also

adapted as a post-fabrication solution. So, even in the case where a highly thinned

chip needs cooling in a specific application, the backside approach can provide

a solution without modifying the process flow map.

a. Jouve, v. Balan, n. Bresson, c. euvrard-colnat, f. fournel, y. exbryat, g. Mauguen,

M. abdel Sater, c. Beitia, l. arnaud, S. cheramy, S. lhostis, a. farcy, S. guillaumet,

S. Mermoz, h. Jacquinot, t. lacrevaz, c. Bermond, a. farcy and B. flechet “1µm

pitch Direct hybrid Bonding with < 300nm Wafer-to-Wafer overlay accuracy ”-

Soi-3D-Subthreshold Microelectronics technology unified conference (ieee- S3S),

october 16-19, 2017 San francisco (uSa)

The goal of this article is to present a complete hybrid bonding process optimization

achieved on 300mm wafers to enable down to 1µm pitch dimension copper

pad connections.

This paper shows for the 1st time successful bonding results of 300mm wafer-to-wafer

hybrid bonding with copper pads as small as 500nm. Investigation on copper density

tolerance as well an application on electrical wafers is currently in progress.

i. Jani, D. lattard, p. vivet, e. Beigné “innovative Structures to test Bonding

alignment and characterize high-Density interconnects in 3D-ic” - 15th new

circuits and Systems (ieee- neWcaS), June 25-28, 2017 Strasbourg (france)

This paper focuses on test and characterization of cu-cu interconnects and propose

a novel technique to measure several information after bonding: perfect alignment,

misalignment (direction, value) and contact resistance. These test structures are

implemented without active part for process development and also in an application

circuit to assess performance of 3d-Ic thanks to the dFT infrastructure.


FIB-SeM X-section of 1µm pitch copper pads after 400°c-2h annealing.

SeT Bonding equipment in cleanroom

High-density 3d-Ic architecture


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S. cheramy, M. vinet and o. faynot

“3D integration technology for

high-Density / high-performance

ics” chip Scale review Magazine

april 2017

This paper describes the process

flows for very high 3d integration:

3d stacking, (wafer-to-wafer

and chip-to-wafer), as well as

3d monolithic coolcubeTM

technologies are considered

as complementary approaches

to produce high-performance

devices. Both coolcubeTM and

3d stacking are considered for

performance, cost and form factor

reduction. The promising results

reached for both integrations

give high confidence for their

use in fabricating products in

the near future for a wide range

of applications.

S. cheramy “advanced 3D

technologies for Smart image

Sensors” 14th 3D architectures

for high Density integration

and packaging (3DaSip)

December 5 - 7, 2017

San francisco (uSa)

This presentation highlighted

the 3dVlSI IRT Nanoelec offer

with a complete range

of technologies including design.

This include a demonstration

of test vehicle on various

cMoS node, a demonstration

of fine pitch (< 1µm) hybrid

bonding, an exploration and

demonstration of 3-level-wafer

stacking of heterogeneous chips

and an architecture partitioning

of complex computing chips.

h.Jacquinot, l. arnaud, a. garnier, f. Bana, J.c Barbe, S. cheramy

“rf characterization and Modeling of 10 µm fine-pitch cu-pillar on a high Density

Silicon interposer” - 67th electronic components and technology conference

(ectc), May 30- June 2, 2017 orlando (uSa)

This work aims at providing a RlcG extracted model of the 10 µm fine-pitch

microbump type interconnects in the 100 MHz-10 GHz frequency band based on

characterization from dc to 40 GHz. RF measurements are performed on two-port

test structures within a short-loop with chip to wafer assembly using 10 µm fine

pitch cu-pillar on a 10 ohm.cm substrate resistivity silicon interposer. accuracy

is obtained thanks to a coplanar transmission line using up to 44 cu-pillar based

transitions. To the author knowledge, it is the first time that a RlcG model of fine-

pitch cu-pillar is extracted from experimental results. another goal of this work is to

get a better understanding of the main physical effects over a wide frequency range,

especially concerning the key parameter of fine pitch cu-pillar 3d interconnects, i.e.

the resistance. Finally, analysis based on the proposed RlcG extracted model are

performed to optimize over frequency the resistive interposer-to-chip link thanks to

process modifications mitigating high frequency parasitic effects.

a. garnier, l. arnaud, r. franiatte, a. toffoli, S. Moreau, f. Bana and S. cheramy

“electrical performance of high Density 10µm pitch cu-pillar with chip-to-Wafer

assembly” - 67th electronic components and technology conference (ectc), May

30- June 2, 2017 orlando (uSa)

Micro bump-based interconnects with 20 µm pitch have been fabricated on 300

mm wafers using industrial tools. Good processes control enables to get narrow

standard deviations for the micro bumps height (0.2 µm) and diameter (0.4 µm).

electrical yield measured on daisy chains is very good (close to or higher than

90%) for MR or Tc, even on more than 20,000 interconnects. For Tc NcP, electrical

yield remains to be improved, particularly on large daisy chains. Finally, an original

electrical test has been designed and successfully implemented to characterize top

to bottom misalignment. These results are promising for future high performance

computing products that would require 20 µm pitch micro bumps.

o. Jerhaoui, S. Moreau, D. Bouchu,

g. romero, D. Marseilhan, t. Mourier

and a. garnier “Quality and reliability

assessment of cu pillar Bumps for fine

pitch applications” 67th electronic

components and technology

conference (ectc), May 30 - June 2,

2017 orlando (uSa)

This paper presents the relations

between processing, microstructure

and mechanical reliability of copper

pillar bumps (cuPi). Two sets of samples

were manufactured: cu/Snag and cu/

Ni/Snag with diameters between 15 and

20 µm. From the microstructure point

of view: at these dimensions and for

simulated reflows, up to 5, intermetallic

compounds (IMc) follow a classical

power law with a time exponent

value between 1/3 and 1/2 indicating

the interfacial IMc growth is grain

boundary/volume diffusion-controlled.

adding a Ni layer limits micro-voids and

IMc growth (~2-3 µm w/o. Ni vs. ~1 µm

w. Ni). From the mechanical/reliability

point of view: the more reflow, the

tougher the cu pillar bumps. With 5

reflows, the pillar bump

is a minima 74 % tougher for a cu/Snag

one and 19 % for a cu/Ni/Snag one.

at the investigated shear heights, the

fracture is always in the solder without

any apparent impact of IMc growth.


S. cheramy, a. Jouve, l. arnaud, c. fenouillet-Beranger, p. Batude and M. vinet

“towards high Density 3D interconnections” - ieee - 3Dic conference,

november 09 - 11, 2017 San francisco (uSa)

This paper presents two 3d-high density (with 3d interconnects pitch around

or below the µm range) schemes using on one side hybrid bonding

and on the other one monolithic integration.

S. cheramy, a. Jouve, l. arnaud, c. fenouillet-Beranger, p. Batude and M. vinet

“3D high Density: technology, roadmap and applications” 50th international

Devices packaging conference (iMapS), october 09 - 12, 2017

raleigh - north carolina (uSa)

This paper presents two 3d-high density (with 3d interconnects pitch around

or below the µm range) schemes using on one side hybrid bonding and on the other

one monolithic integration. Both integrations are described and current status are

given. a technology/application roadmap is proposed positioning both integrations

and showing that they offer complementary approaches to tackle most of today

challenges in terms of cost, area, power and performance. The promising results

reached for both integrations give high confidence for products in near future

and with a wide range of applications.

J-h. choy, v. Sukharev, S. chatterjee, f. n. najm and S. Moreau “physics-based

electromigration assessment for analysis of eM Degradation in 3D ic test

Structures” ieee- 54th Design automation conference (ieee-Dac),

June 18 - 22, 2017 raleigh - austin (uSa)

In this study, two novel approaches to eM assessment, which are based on the

analysis of stress evolution under the eM load, were implemented for the first time

for analysis of eM degradation in 3d Ic components. The fast compact model

approach employs hypothetical steady-state stress at all times, while a more accurate

finite-difference approach resolves time evolution of stress in each interconnect tree.

D. Dutoit “emerging architecture for computing with 3D Silicon integration”

Design for 3D Workshop (D43D Workshop), June 26- 27, 2017 raleigh -

grenoble (france)

This presentation discussed on how 3d will contribute to scale features for higher

performances. First application is for computing applications (more parallelism,

more cores, more memory per core and more data bandwidth, less data latency).

For future developments, new architectures are emerging from co-design process

and advanced packaging enables system architecture specialization (SIP for

server on a chip, silicon interposer for new Noc and high density 3d monolithic 3d

for disruptive architectures).

S. cheramy “advanced 3D technologies for innovative 3D architecture” Design

for 3D Workshop (D43D Workshop) June 26- 27, 2017 raleigh – grenoble (france)

3d can help for extending Network-on-chip to the third dimension and offer more

latitude to designers. concerning technological aspects, IRT Nanoelec is working

towards several disruptive 3d stack options devoted to fine alignment and pitches.


19


The photonics program of the IRT Nanoelec works towards the design and integration of photonics components on silicon for high speed short reach data communications

targeting High Performance Computing (HPC) and Data Center market segments. This program groups five complementary partners:

Mentor graphics, bringing to the consortium its expertise on automated design and layout verification

SAMTEC, specializing in module integration and packaging, who has joined the program in 2015 and who has provided a since a strong leadership in our efforts to target the transceiver market, making our demonstrator proposals more effective;

Finally, a group of technology partners composed by ST Microelectronics, CEA-Leti and CNRS who are working together to define innovative components and the associated fabrication processes on the two CMOS technology lines that coexist in the program (STM’s 300 mm and CEA-Leti’s 200 mm lines).

Benoit charBonnier Silicon photonicS prograM Director

Silicon photonicS prograM


21


WorlDWiDeBenchMarK

20SILICON PHOTONICS PROgRAM

The tables (see below) show that we

address most of the relevant topics

considered by other industrial

or research institutions and that

we have a comprehensive approach

including basic technology

to packaging and integration.

Our III-V on silicon integration

platform is extremely

well-positioned and is definitively

a key differentiator compared

to the other players in the field.

Another important player, as far as

laser hybrid integration is concerned,

in INTEL, but extremely little

information on their results

and performance is available.

The tables below shows a short form comparison of the results achieved

by the photonics program with the current state of the art worldwide.

We have tried, when possible, to compare our results with the ones

obtained (and communicated) by other research programs or even

industrial players. The main competitors are:

· PETRA consortium focussing on the development of transceiver

modules with flip-chipped lasers and specific packaging techniques

for high volume and low cost assemblies.

· IMEC, focussing on Silicon Photonics technologies, fabrication

and integration.

· AIM Photonics, a large public-private US based consortium,

developing Silicon photonics technologies and associated packaging.

· STMicroelectronics associated with Luxtera and considered

here as a “competitor” although STMicroelectronics is part

of the IRT photonics program (focussing on separate/independent

technological developments).

passive Devices library

Devices irt results imec results petra results st-luxtera others band O-band mainly C-band mainly O-Band mainly O-Band -

Rib WG loss 1.5dB/cm 1.5dB/cm 1.5dB/cm 1.9dB/cm AIM: <2.2dB/cm

1D Grating Coupler 2dB 5dB (2dB with modified process) - 2.3dB (full flow) Luxtera/TSMC: 1.2dB (O-band)AIM: <3dB

2D grating coupler 4dB 6dB - 3.5 dB (full flow) Luxtera/TSMC: 3.2dB (O-band)

Silicon Mux IL 3dB (echelle, MZI), 4 IL<3dB (MZI)XTalk <14dB, 4 - -

IME (8 ), XTalk<15dB with heater control

IBM: IL<2dB, XTalk<15dB (MZI)

Athermal Mux.

SiN Echelle CWDMIL < 3 dB / XTK > 25 dB

BW -1dB = 10nmAthermal Mux (Si) O-Band, 17pm/K, XTK>15dB, IL<4dB

Polymer assistedAWG IL<2.5dB

XTK>15dB- -

ST : AWGMZI cascadés/SiN

(IL<1dB)

Edge Coupler - SiON edge coupler 2dB IL (3μm MFD) - - AIM: <2.5dB/facet

Broadband 1D grating coupler

Si/SiN devicesBW@(1-dB): 60nm

IL<4dB- - - -

Low loss WG <1dB/cm (H2 annealing) - - - AIM: <1dB/cm for SiN

50g active devices library

Devices irt results imec results petra results st-luxtera others

MZM52 Gbps / 30GHz BW

1.9V/cm0.8dB/cm (Deep rib)

56Gbps / 27GHz1.65V.cm16dB/cm

25Gbps / 17GHz0.31V.cm

56Gbit/s 40GHz BW2.5V.cm

0.55dB/cm

IME : 40Gbps, 20GHz, 2.2V.cmAIM : BW>15GHz, <5dB loss,

25Gbps operation

High Speed photodetector

SiGeSi PIN diode>1A/W, 35GHz, Idark<1nA

Ge PIN diode>0.85A/W, 50GHz, Idark<10nA

Ge PD>0.8A/W, 20GHz

Ge SH PD / 60GHz0.9A/W

Idark <20nA

IME: >6A/W, Idark<100nASiFotonics: 28Gbps product

AIM: BW>45GHz, Idark<20nA

eic and pic integration


µ pillar based flip chip Pitch 40µm and 50µmDemonstrated 25Gbps Flip chip (pitch?) Flip chip (pitch?)

3D assemblyBiCMOS 55 EIC

40µpicth Cu-pillar 56Gbit/s

Finisar demonstrated 56Gbps modulation with flip-chipped

electronics

TSV Under Development - - - IME: TSV availableAIM Photonics

Modules/ technical demonstrators


100G PSM 4x25G Chip on board RX - 4x25G MMF O-band (5mW/Gbps)

4x25G PSM4 product available

Commercial products from Luxtera, Mellanox, Intel, MACOM

100G WDM 4x25G Chip on board RX 4x25Gbps TX based on ring modulators - - Mellanox, Intel (CWDM)

200G/400G Ongoing - 12x25Gbps MMF (5mW/Gbps) - -

800G - 16x56Gbps C-band WDM module - - -

laser integration


Direct Oxyde Bonding DFB, DBR demonstrated Integrated circuits (MZM) - - - Commercial product from

INTEL and AurrionFlip Chip - - Laser array (multimode) - MACOM: single laser flip chip

Direct Epi Ongoing Directly grown but not yet electrically pumped - - IBM

Quantum Dot lasers Direct Oxyde bonding - -

QDLaserOperation up to 75°C,

25Gbps- HP


22 23


2017 hIghLIghTs laser integration

The laser integration process has produced a large number of key results and prototypes to demonstrate the successful

inclusion of lasers on Silicon by molecular bonding of III-V wafers and/or dies. all the required processing steps, which had been

demonstrated on 100m wafers and non-cMoS compatible environment, have now been demonstrated on 200mm wafers and

are cMoS compatible. The realization of a backside laser has been demonstrated, ensuring compatibility with all industrial grade

ST Back end of line (Beol) processes and easing considerably the potential future integration of a laser source in an industrial

platform. In addition to the maturation of different process steps (III-V bonding – wafers and dies, substrate removal and III-V

patterning), one major result has been the identification of Nickel-Silicon (NiSi) as a potential good material to create an electrical

contact on III-V material and remain cMoS compatible (Gold was previously used, which is not cMoS friendly). NiSi contacts have

been processed, showing less that 10Ω resistance (including the laser diode resistance) and allowing a laser with less than 60ma

of threshold current and maximum

output power of 4mW to be

demonstrated (Figure 1 and Figure 2).

This is a real first world and, because

the different building blocks have been

engineered with 300mm compatibility

in mind, the way to a backside full

300mm integrated laser is now clear.

We are now working on the fabrication

of tungsten plugs to obtain a planar

laser back-end and be able to have

3d integration of electronic chips

with lasers.

full flow devices library (pDK)

Several Photonic design Kits (PdK) have been coded and now include in a full library

of active and passive components with a high level of maturity. These different PdKs

relate to different technology platforms both in the 300mm ST Microelectronics

manufacturing line (in crolles) and 200mm leti clean room.

one important aspect to underline is the fact that leti 200mm PdK has been

improved and matured so as to be offered in Multi-Project Wafer (MPW) runs

with our cMP partner. First contributions from external customers have been

received and we will continue to offer public access to leti’s technology to promote

it and gain access to potential future partners.

fiber packaging: micro-lenses

auto-alignment by solder reflow

excellent results have been obtained

demonstrating the auto-alignment

of a coupling structure with optical

grating couplers on a Silicon Photonic

chip by flip-chipping the coupling

structure on the PIc using copper-pillars

and then reflowing the solder to use

capillarity forces to realign the chips

precisely. an accuracy better than

0.5µm has been obtained with an initial

misalignment tolerance of up to 6µm.

This is entirely compatible with high

throughput pick and place tools

(>1000 pieces/hour) and would lead

to an entirely passive optical coupling

mechanism.

high speed circuit technical demonstrators

50Gbps Mach-Zehnder Modulator

52Gbps ooK modulation (limited by our test equipment) was achieved

on a 3mm long MZM from leti’s platform. The MZM exhibited an impressive 2V.cm

of modulation efficiency combined with record low loss of 0.8dB/cm and around

30GHz of bandwidth.

25GBaud PaM4 Mach-Zehnder Modulator

25GBaud PaM4 operation was demonstrated on a MZM integrated into a full circuit

demonstrator (with photodetectors).

4x25Gbps receiver for 100G applications

a four channel receiver comprising a wavelength demultiplexer and four high

speed photodetectors with a quad channel trans-impedance amplifier fabricated

by STMicroelectronics flip-chipped onto the PIc was operated successfully. all four

channels were operational and exhibited clear opened eyes at 25Gbps. The footprint

of the circuit was compatible with 100G ethernet products.

25Gbps MZ Modulator with integrated laser

a functional circuit integrating for the first time a tunable laser processed on Silicon

along with a Mach-Zehnder modulator has been fabricated and tested. operation

of the MZM at 25Gbps ooK and the laser was tuned over more than 10nm.

four channel Multiplexers

Several versions for wavelength multiplexers have been designed, fabricated

and demonstrated in the frame of the project. The best results have been obtained

by using cascaded Mach-Zehnder interferometers that have been designed to be

at the same time fabrication fluctuation tolerant and thermally stable.

New multiplexers have also been fabricated in the Silicon Nitride (SiN) layer

to improve thermal stability and to give an additional flexibility to circuit designers.

Results have shown echelle gratings bases multiplexers with less than 10pm/°c of drift.

high Speed photodetectors

In order to reduce the number of processing steps when making photodetectors,

a double heterojunction PIN diode has been designed in replacement of bulk

germanium. Indeed, bulk germanium photodiodes need the doping of Germanium

(both P and N side) whereas, the new SiGeSi diode, because only the Si parts are

doped, reuse the implantation steps of phase shifters (used in MZM for instance).

Similarly, the electrical contacts are implanted on the silicon regions and thus

contacting Germanium is not needed anymore. This leads to a significant reduction

of the number of lithographic steps in a full flow fabrication. We have demonstrated

that such photodetectors have state of the art performance with responsivities

greater than 1a/W, bandwidth in excess of 35GHz and dark current lower than 1na.

low loss waveguides

By thermally annealing under H2

pressure, it has been shown that the

lateral roughness of silicon waveguides

can be reduced. Sidewall roughness

is mainly responsible for propagation

losses in highly confined waveguides

(waveguides whose width < 800nm).

a loss lower than 0.6dB/cm has been

obtained for waveguides wider than

300nm after optimization of the

annealing process. This is a record

for low loss waveguides.

Figure 1: Photographs of a dFB laser during test

Figure 2: emission spectrum at 160ma bias current of a dFB laser. Inlet: Transmission spectrum of the output grating coupler showing 10dB of optical loss at the lasing wavelength the waveguide coupled output laser power is thus 4mW.

SILICON PHOTONICS PROgRAM

In 2017, the main results achieved by the photonic program are:


25


24


S. Zhiou, ph. rodriguez, f. nemouchi, c. perrin-pellegrino, p. gergaud

and K. hoummada “composition and phase sequence of ni-ingaas

intermetallics: an in situ XrD and atom probe tomography study” 26th

Materials for advanced Metallization conference (MaM 2017), March 26-29,

2017- Dresden (germany)

The improvement of MoSFeT transistors performances at advanced sub 10 nm

technological node pushes the Si to its limits as a channel material. In order to

continue the enhancement of such performances, one solution among others,

is to replace silicon with a material that yields better mobility of charge carriers.

III-V compounds and especially InGaas alloys can achieve such performances

compared to Si. among several steps that are ought to be studied, the formation

of suitable, thin, stable, ohmic and with low resistivity contacts is crucial. Such

contacts can be achieved through a solid-state reaction between Ni and InGaas.

In this paper we report on the phase sequence of the resulting compound

Ni4InGaas2.

r. famulok, ph. rodriguez, y. le friec, J. ph. reynard, K. Dabertrand,

B.n. Bozon, S. favier, y. Mazel, e. nolot, B. previtali, p. gergaud, f. nemouchi,

“characterizations of fluorine-free tungsten liner and its application

for pcraM”- 26th Materials for advanced Metallization conference

(MaM 2017), March 26-29, 2017- Dresden, (germany)

Using a metal-organic tungsten based precursor, a fluorine-free tungsten

thin film has been obtained. The process deposition recipe includes

a plasma-enhanced cVd step and ald cycles. This tungsten thin film

can be used as low resistance liner and barrier to fluorine diffusion

for several applications in replacement of the classical TiN liner.

r. famulok, ph. rodriguez, y. le friec, J. ph. reynard, K. Dabertrand,

B. n. Bozon, S. favier, y. Mazel, e. nolot, B. previtali, p. gergaud, f. nemouchi,

“properties of fluorine-free tungsten thin film and its application as low

resistance liner”- european Materials research Society (e-MrS Spring

Meeting), May 22-26, 2017 Strasbourg (france)

a set of physicochemical characterizations including XRR, in-plane XRd, WdXRF,

plasma profiling time of flight mass spectrometry (PPToFMS) and SeM/TeM

observations has been realized in order to study a F-free W thin film structure

and properties. This tungsten thin film can be used as low resistance liner

and barrier to fluorine diffusion for several applications in replacement

of the classical TiN liner. The film is perfectly conformal and exhibits

extremely low electrical resistivity.

c. Bellegarde, e. pargon, c. Sciancalepore and c. petit-etienne, “improvement

of sidewall roughness of sub-micron silicon-on-insulator waveguides for low-loss

on-chip links” Spie photonic West - Silicon photonics Xii conference 10108,

Jan. 30 – feb. 1, 2017 San francisco (uSa)

We report the successful fabrication of low-loss sub-micrometric Silicon-on-Insulator

strip waveguides for on-chips links. Several strategies including post-lithography

treatment, and post-silicon smoothening techniques such as thermal oxidation and

hydrogen annealing have been investigated to smoothen the waveguide sidewalls,

as roughness is the major source of transmission losses. an extremely low silicon line

edge roughness of 0.75nm is obtained with the optimized process flow combining

resist mask Si patterning and hydrogen annealing at 850°c. as a result, record

low optical losses of less than 0.5dB/cm are measured at 1310nm for waveguide

dimensions superior to 500nm. They range from 2dB/cm to 0.8dB/cm

for 300-400nm wide waveguides. Those results are to our knowledge

the best ever published for a 1310nm wavelength.

c. Bellegarde, e. pargon, c. Sciancalepore, c. petit-etienne, v. hughes,

D. robin-Brosse, J. M hartmann and p. lyan “optimization of optical performances

in sub-micron silicon-on-insulator rib and strip waveguides by thermal annealing

under h2”- 10th plasma etch and Strip in Microelectronics Workshop (peSM),

louvain (Belgium)

Silicon-on-Insulator is a strong and efficient approach for the fabrication of optical

communication systems: it is compatible with cMoS fabrication processes

and transparent at telecom wavelengths. The contrast of refractive index between

Si and Sio2 is large enough (around 2) such that Si/Sio2 waveguides show a great

confinement of light, it is thus possible to make small footprint optical chips via the

use of sub-micron wires notably. However, the decrease of waveguide dimensions

is synonym with the increase of scattering losses as there are stronger interactions

between light and the rough sidewalls

of waveguides. as a consequence, one

efficient way to decrease optical losses

in sub-micron waveguides is to smooth

the waveguide’s sidewalls. In this work,

we study the optimization of the

waveguide patterning process flow to

significantly reduce sidewalls roughness

in order to obtain low-loss on-chip links.


S. Zhiou, ph. rodriguez, K. hoummada,

n. Blanc, n. Boudet, f. nemouchi and

p. gergaud, “in situ investigation

of ni-ingaas contacts for advanced

cMoS”, advanced Metallization

conference (aMc), September 13-14,

2017 austin (uSa)

The texture and phase sequence

of intermetallic compounds formed

upon solid-state reaction between

thin Ni films and InGaas was studied

through X-ray diffraction 3d-Reciprocal

Space Mapping. Ni-InGaas proved

to yield a sequential formation scheme.

Moreover, starting from the same

as-deposited samples, the material

investigation revealed significant texture

difference whether slow annealing or

Rapid Thermal annealing were performed.

S. Bensalem, e. ghegin, ph. rodriguez,

f. nemouchi, S. favier, M. pasquali,

c. Jany and p. gergaud “ti nanoalloyed

ohmic contacts to p-in0.53ga0.47as for

iii-v photonics applications” - advanced

Metallization conference (aMc),

September 13-14, 2017 austin (uSa)

In this work, we report silicon fab-

compatible non-gold ohmic contacts to

p-In0,53Ga0,47as using a Ti metallization.

In order to identify the auspicious

process conditions allowing the best

specific contact resistance value,

samples with a metallization sequence

of TiN /Ti /InGaas were analysed after

different temperature annealing. First

X-ray diffraction (XRd) results show no

reaction between the Ti film and InGaas

below 300°c. From that temperature,

we were able to identify, for the first


27


26

y. D. Zonou et al. “Self-alignment

with copper pillars Micro-Bumps

for positioning optical Devices

at Submicronic accuracy” -

67th electronic components

and technology conference (ectc),

May 30 - June 2, 2017 orlando (uSa)

This paper studies the self-alignment

properties between two chips

that are stacked on top of each

other with copper pillars micro-bumps.

The chips feature alignment marks

used for measuring the resulting

offset after assembly.

The accuracy of the alignment is found

to be better than 0.5 µm in X and Y

directions, depending on the process.

The chips also feature waveguides

and vertical grating couplers (VGc)

fabricated in the front-end-of-line

(Feol) and organized in order to realize

an optical interconnection between

the chips. The coupling of light between

the chips is measured and compared

to numerical simulation. This high

accuracy self-alignment was obtained

after studying the impact of flux and

flux less treatments on the wetting

of the pads and the successful

assembly yield. The composition

of the bump surface was analyzed

with Time-of-Flight Secondary Ions

Mass Spectroscopy (ToF-SIMS) in order

to understand the impact of each

treatment. This study confirms that

copper pillars microbumps can be used

to self-align photonic integrated circuits

(PIc) with another die (for example

a micro lens array) in order to achieve

high through put alignment of optical

fiber to the PIc.

time, the formation of the Ti5Ga4 compound. While electrical measurements

performed on the samples show that the Ti contacts may exhibit a Schottky

behaviour at low temperature, best ohmic results were obtained on samples

annealed at 350°c for a specific contact resistance as low as 1.2 .10-6 Ω.cm2

belonging to Ti5Ga4 phase. at higher temperatures a degradation of the

specific contact resistance was observed.

M. casale, S. Kerdiles, p. Brianceau, v.hugues, h. el Dirani and c. Sciancalepore

“low-temperature crack-free Si3n4 nonlinear photonic circuits for cMoS-

compatible optoelectronic co-integration” Spie photonic West - Silicon

photonics Xii, conference 10108 Jan. 30 – feb. 1, 2017 San francisco (uSa)

In this communication, authors report for the first time on the fabrication and

testing of Si3N4 non-linear photonic circuits for cMoS-compatible monolithic

co-integration with silicon-based optoelectronics. In particular, a novel process

has been developed to fabricate low-loss crack-free Si3N4 750-nm-thick films for

Kerr-based nonlinear functions featuring full thermal budget compatibility with

existing Silicon photonics and front-end Si optoelectronics. Briefly, differently

from previous and state-of-the-art works, our nonlinear nitride-based platform

has been realized without resorting to commonly-used high-temperature

annealing (~1200°c) of the film and its silica upper cladding used to break N-H

bonds otherwise causing absorption in the c-band and destroying its nonlinear

functionality. Furthermore, no complex and fabrication-intolerant damascene

process - as recently reported earlier this year - aimed at controlling cracks

generated in thick tensile-strained Si3N4 films has been used as well. Instead,

a tailored Si3N4 multiple-step film deposition in 200-mm lPcVd-based reactor

and subsequent low-temperature (400°c) PecVd oxide encapsulation have been

used to fabricate the nonlinear micro-resonant circuits aiming at generating

optical frequency combs via optical parametric oscillators (oPos), thus allowing

the monolithic co-integration of such nonlinear functions on existing cMoS-

compatible optoelectronics, for both active and passive components such as,

for instance, silicon modulators and wavelength (de-)multiplexers. experimental

evidence based on wafer-level statistics show nitride-based 112-µm-radius ring

resonators using such low-temperature crack-free nitride film exhibiting quality

factors exceeding Q >3 x 105, thus paving the way to low-threshold power-efficient

Kerr-based comb sources and dissipative temporal solitons in the c-band

featuring full thermal processing compatibility with Si photonic integrated

circuits (Si-PIcs).

ph. rodriguez, r. famulok, f. Boyer, y.

le friec, J.-ph. reynard, B.-n. Bozon,

K. Dabertrand, c. Jahan, S. favier, y.

Mazel, B. previtali, p. gergaud and f.

nemouchi, “fluorine-free tungsten

film: properties, Modeling and

application as low resistance liner

for pcraM” advanced Metallization

conference (aMc), September 13-14,

2017 austin (uSa).

Using a metal-organic tungsten based

precursor, a fluorine-free tungsten

ultrathin film has been developed,

integrated and electrically evaluated. a

set of physicochemical characterizations

has been realized in order to study the W

thin film crystallographic structure and

morphology. The F-free W film exhibits

the lowest electrical resistivity phase

( -W) but is not pure. Indeed, in addition

to a top surface oxidation, a layer located

at the W film / substrate interface is

present. This interface layer (Il) contains

impurities, including carbon and oxygen,

due to ligand decomposition. after the

demonstration of its perfect conformality

in various features, the W liner has been

implemented on PcRaM structures in

order to evaluate its impact on contact

plug resistivity. at the aspect ratio studied,

the gain in terms of contact plug

resistivity is about 20% compared to the

process of reference using a TiN liner.

Modeling showed that this benefit

is mainly due to the reduction of

interface resistances.


J. Durel, B. Ben Bakir, c. Jany, S. cremer, K.hassan, B. Szelag, t.Bria, v. larrey,

l. Sanchez, p. Brianceau, J.a Dallery, r. guiavarch, t. card, r .thibon,

J.e Broquin and f. Bœuf “Back-side integration of hybrid iii–v

on Silicon DBr lasers”, international Symposium on vlSi technology,

Systems and application (vlSi-tSa), april 24-27, 2017 hsinchu (taiwan)

In this paper we demonstrate the monolithic integration of a fully cMoS

compatible hybrid dBR laser on the backside of a SoI wafer. This innovative

approach allowed implementing cMoS compatible electric interconnects

andoptical sources on a same chip. The optical characterizations confirm

the single wavelength behavior of the realized devices which present a SMSR

higher than 35 dB and can be tuned over 4 nm, opening the route to a fully

integrated optical transceiver on a Si platform.

M. epitaux “Silicon photonics for Mid-Board optical Modules”,

technical presentation SeMi Stc Semicon europa, november 14 – 17, 2017

Munich (germany)

after reviewing the challenges faced by transceiver in the data center market

and the requirements for on-Board optical Modules, the design of Silicon

Photonics based 200G capable modules is detailed including validation

for signal integrity, optical coupling and thermal management.


29


28

ph. rodriguez, r. famulok, y. le friec, J.ph. reynard, B.n. Bozon, f. Boyer,

K. Dabertrand, c. Jahan, S. favier, y. Mazel, B. previtali, p. gergaud, f. nemouchi,

“advanced characterizations of fluorine-free tungsten film and its application

as low resistance liner for pcraM” Mater. Sci. Semicond. process. 71 (2017) 433-440.

Using a metal-organic tungsten based precursor,

a fluorine-free tungsten thin film has been

obtained. The process deposition recipe includes

a plasma-enhanced cVd (PecVd) step and

atomic layer deposition (ald) cycles. a set of

physicochemical characterizations including

X-ray reflectivity (XRR), in-plane X-ray diffraction

(XRd), wavelength dispersive X-ray fluorescence

(WdXRF), plasma profiling time of flight mass

spectrometry (PPToFMS) and microscope

observations has been realized in order to study

the W thin film structure and properties. The film

is perfectly conformal whatever the structure

size investigated (from tens of nanometers to micrometers wide). It was also

highlighted that the F-free W film exhibits the lowest electrical resistivity phase

( -W) but is not pure. Indeed, in addition to a top surface oxidation, a layer located

at the W film / substrate interface is present. This interface layer (Il) contains

impurities, including carbon and oxygen, due to ligand decomposition. This Il

might be deposited during the soak step or during the PecVd step. The W liner

with thicknesses ranging from 3 to 4 nm has been implemented on PcRaM

structures in order to evaluate its impact on contact plug resistivity. First electrical

results are promising and demonstrate the interest of using a F-free low resistance

W liner. at the aspect ratio studied, the gain in terms of contact plug resistivity

is about 20% compared to the process of reference using a TiN liner. Modeling

shows that this benefit is mainly due to the reduction of interface resistances.

K. hassan, c. Durantin, v. hugues, B. Szelag, a. glière, “robust silicon-on-

insulator adiabatic splitter optimized by metamodeling”, applied optics

56 (8), 2047-2052

a robust integrated power splitter based on a silicon-on-insulator adiabatic

coupler configuration is demonstrated. The power separation is achieved

by a slow and simultaneous change of phase and coupling constants.

The geometrical parameters of the device are determined thanks to a

metamodel-based iterative optimization strategy. Solving the multiple

parameter problem together with a realistic bandwidth constraint provides

a clear improvement of the power splitting stability. The robustness

is confirmed experimentally on a single device and at the wafer scale.

e. ghegin, ph. rodriguez, M. pasquali, i. Sagnes, J. l. labar, v. Delaye, t.

card, J. Da fonseca, c. Jany, f. nemouchi, “cMoS-compatible contacts to

n-in” ieee trans. electron Devices 64 (2017) 4408-4414

In the context of the development of silicon photonics, various Ti and

Ni-based alloyed metallization have been investigated for the purpose

of forming low resistivity and Si cMoS-compatible contacts to n-InP.

The innovative Ni2P metallization combined with an in situ ar+ preclean

represents the most suitable available solution for the formation of ohmic

contacts with a specific contact resistivity as low as 4.3 x 10−6 Ω.cm2 on such

a semiconductor. The latter additionally presents the advantage of being

stable at least up to 350°c and could therefore withstand additional

integration processes conducted at this temperature.

c. Bellegarde , e.pargon, c. Sciancalepore, c. petit-etienne, v. hughes,

D. robin-Brosse, J.M hartmann, p. lyan “improvement of Sidewall roughness

of Sub-Micron Soi Waveguides by hydrogen plasma and annealing” ieee

photonics technology letters, early access, Dec. 2017

We report the successful fabrication of low-loss sub-micrometric silicon-on-

insulator strip waveguides for on-chip links. Post-lithography treatment and

post-etching hydrogen annealing have been used to smoothen the waveguide

sidewalls, as roughness is the major source of transmission losses. an extremely

low silicon line-edge roughness of 0.75 nm is obtained with the optimized

process flow. as a result, record-low optical losses of less than 0.5 dB/cm

are measured at 1310 nm for strip waveguide dimensions exceeding 500 nm.

They range from 1.2 dB/cm to 0.8 dB/cm for 300 - 400 nm wide waveguides.

Those results are to our knowledge the best ever published for a 1310 nm

wavelength. These results are compared to modeling based on Payne

and lacey equations.

GeNeRalIST TecHNIcal ReVIeW

S. Bernabé, o. castany, B. Szelag,

B. charbonnier, and M. epitaux

“photonic modules for data centers

require cutting-edge technologies”,

chip Scale review, 21, 5, 2017

Review of the requirements and

challenges for Silicon Photonics circuits

technology and module packaging

to serve the market for high speed

short reach optical interconnects

for data center Networks.

c. Kopp, S. olivier, S. Bernabé

“light is the ultimate Medium

for high-Speed communications”,

europhotonics, Mars 2017.

Review of the Silicon photonics

technology and its combination

with heterogeneous materials and 3d

photonic integration to respond to the

upcoming challenges of very high speed

data communications.

e. ghegin, ph. rodriguez, J. l. labar, M. Menyhard, S. favier, i. Sagnes,

f. nemouchi, “phase formation sequence in the ti / inp system during

thin film solid-state reactions” J. appl. phys. 121 (2017) 245311.

The metallurgical properties of the Ti/InP system meet a great interest for its

use as a contact in the scope of various applications such as the Si Photonics.

The investigations conducted on this system highlight the initiation of a

reaction between the Ti and the InP substrate during the deposition process

conducted at 100°c. The simultaneous formation of two binary phases,

namely, Ti2In5 and TiP, is attributed to the compositional gradient induced

in the InP by the wet surface preparation and enhanced by the subsequent

in situ ar+ preclean. once formed, the TiP layer acts as a diffusion barrier

inhibiting further reaction up to 450°c in spite of the presence of an

important Ti reservoir. at higher temperature, however, i.e. from 550°c,

the reaction is enabled either by the enhancement of the species diffusion

through the TiP layer or by its agglomeration. This reaction gives rise to the

total consumption of the Ti2In5 and Ti while the TiP and In phases are promoted.

articleS IN 2017


B. Szelag, K. hassan, l. adelmini,

e. ghegin, ph. rodriguez, S. Bensalem,

f. nemouchi, t. Bria, M. Brihoum,

p. Brianceau, e. vermande, o. pesenti,

a. Schembri, r. crochemore,

S. Dominguez, M.c. roure,

B. Montmayeul, l. Sanchez, c. Jany,

hybrid iii-v/Si DfB laser integration

on a 200 mm fully cMoS-compatible

silicon photonics platform” ieee

international Devices Meeting (ieDM)

December 2-6, 2017 San francisco (uSa)

In this paper we demonstrate the first

integration of a hybrid III-V/Si laser

in a fully cMoS compatible 200 mm

technology. device with SMSR up to

50 dB and a maximum output power

of 4mW coupled in the waveguide have

been measured. The fabrication flow is

fully planar and compatible with large

scale integration silicon photonics circuit.


31


POWERgAN goal is to develop a new competitive gaN on Silicon power technology that will allow major breakthroughs in terms of power converter energy

efficiency and power density. Its specific objectives are to:

Demonstrate industrial transfer readiness of a gaN/Si 200 mm technology of high performance and high robustness gaN/Si power components ( transistors, diodes )

Explore new advanced architecture of power devices and their related technological building blocks

Adapt gaN/Si power technology to standard packaging and explore advanced packaging techniques

Study and evaluate innovative gaN/Si enabled power converters topologies.

poWerganprograM

philippe pantigny poWergan prograM Director


33


WorlDWiDeBenchMarK

32POWERgAN PROgRAM

Wide band gap technologies, i.e Silicon Carbide (SiC) and gallium Nitride

(gaN), are indeed new entrants with respect to the mainstream Silicon

enabled power electronics that addresses all the voltages with a large

product portfolio of components. SiC and gaN overcome the intrinsic

limitations of Si in terms of operating temperature and switching frequency.

SiC is positioned on applications requiring discrete devices operating

between 900 Volts and 3.3 KVolts whereas gaN/Si rather addresses

applications typically between 200 V and a maximum of 1.2 KVolts.

The two main advantages of gaN/Si on SiC are:

· Manufacturing cost : gaN/Si power components can be manufactured

on CMOS technological platforms on 200 mm substrate wafers;

· Component portfolio: the gaN/Si component portfolio spans from discrete

power transistor/diode to multifunctional monolithic components and,

ultimately to gaN Integrated Circuit.

POWERgAN is a multidisciplinary project where STMicroelectronics,

Schneider Electric and CEA-Leti tackle in an holistic approach gaN/Si

following challenges : power device TCAD; material (gaN/Si device specific

200mm epitaxy); 200mm device technology development (Transistor,

Diode), characterizationand modelling; power device reliability; packaging;

power converter design and test. POWERgAN first prototypes target are

normally off 30 amps – 650V monolithic discrete power transistors and

6 amps – 650V power diodes.

gaN/Si is an emerging technology in the field of power electronics

as shown by yole following product vs. voltage range schematic.

Power electronics is a pervasive technology enabling electricity distribution,

electrical mobility, manufacturing, home appliances and digital devices

powering. The power semiconductor market will reach $36B in 2022

(source: yole 2017) and is at the crossroads of many societal challenges

(efficient energy, green transport, resource efficiency).

The adjacent table (source: yole 2017)

gives the list of the top 18 power

discrete and module players and

their position on the Si, SiC and

gaN power technologies. gaN/Si

is today at an early commercial

stage with a thriving competition

between many different type of

switching devices (enhanced,

depleted, cascade transistor),

device architectures (P-gaN vs.

MIS gate recessed) and wafer size

manufacturing (mainly 150 mm,

as TSMC that produces P-gaN

transistors for fabless companies).

Numerous gaN/Si enabled power

converter prototypes have already

demonstrated the added value of

gaN/Si technology and pinpointed

the gaN/Si technology required

improvements towards high

performance, highly reliable

and competitive large volume

manufacturing.

35

IRT NANOELEC scientific & technical highlights 2017 IRT NANOELEC scientific & technical highlights 2017

34

2017 highlights

o publications in 2017 due to the youth of the program.Setting up a new gan/Si 200 mm process flow

Starting in June 2017, ST and cea-leti teams have combined their respective know-

hows in 150 mm and 200 mm GaN on Silicon discrete power devices into a new

innovative 200 mm GaN on Silicon process flow, generic of the manufacturing of 650

V Noff power transistor and Schottky power diodes. The required test vehicles have

been designed and their manufacturing (epitaxy of GaN on Silicon substrate; Front

end of the line device steps; Back end of the line interconnects steps) launched on

the 200 mm technological platforms of cea-leti and STMicroelectronics.

Key puBlicationS IN 2017

POWERgAN PROgRAM

first promising results

on gan/Si 650v power diodes

Promising results have already been

demonstrated on Schottky power

diodes at 150°c operating temperature.

The 650V – 6 amps power diode

prototypes comply with the targeted dc

performances (forward voltage, reverse

current). Moreover, their transient

response measurements confirms

that the switching characteristics of

GaN/Si “lateral” (High electron Mobility

Transistor architecture) compare very

well to the more conventional “vertical”

Sic power diodes. Schneider electric

characterization of the first prototypes

in conditions representative of its

industrial applications showed similar

performance to the Sic diodes in terms

of recovery current.


37


The characterization program of the IRT Nanoelec includes 4 academic partners (the European Synchrotron Radiation Facility - ESRF, the Institut Laue Langevin - ILL, the Laboratoire

de Physique Subatomique et Cosmologie - LPSC and the PlateForme de NanoCaractérisation (PFNC) of the Commissariat à l’Energie Atomique et aux Energies Alternatives) with 3 industrial partners (STMicroelectronics, Soitec and Schneider Electric). Its objective is to open grenoble Large Research facilities to industrials from the micro and nano-electronic world for their R&D needs by means of dedicated characterization equipment, specific knowledge and quick and easy access to them.

The required infrastructure and links between the academic and industrial partners have been set during the first years of the Characterization Program. The latter is now focusing on last equipment’s development, short term feasibility studies, long term technological characterizations and the development of R&D services to industry. The three first actions constitute the heart of the collaborative research undertaken for the technological programs of the IRT Nanoelec and accessible to the industry. The last ones gave birth to the Platform for Advanced Characterisation – gRENOBLE (PAC-g), the operational structure dedicated for servicing industry.

JéroMe BeaucourcharacteriZation on large-Scale inStruMentS prograM Director

characteriZation on large-Scale

inStruMentS prograM

39

IRT NANOELEC scientific & technical highlights 2017 IRT NANOELEC scientific & technical highlights 2017

WorlDWiDeBenchMarK

38CHARACTERIZATION ON LARgE-SCALE

INSTRUMENTS PROgRAM

création de l’offre de service (platform for advanced characterization-grenoBle):The valorisation structure created by the program to service Industry. a special attention has been put by the characterization

Program into the best value to generate from the PIa investment to the benefit of the microelectronic industry in France.

Besides the value jointly generated in the frame of the IRT technical program, the program initiated a specific development

model based on the commercialization of innovative characterization services accessible to industry valuing the feasibility studies

and long term research achieved

in the frame of the IRT Nanoelec.

a dedicated structure has been set

promotes for this purpose: the Platform

for advanced characterization-

GReNoBle (Pac-G). Pac-G. This initiative

has been strengthen thanks to a

dedicated collaboration with Serma

technology, a French technology

consulting and engineering company

specialized in analysis, control, expertise

and consulting service of electronic

components, boards and systems.

The year 2017 took IRT Nanoelec’s innovative service lineup to new levels with the advent of the Platform for advanced characterization-

Grenoble, or Pac-G, initiative. Previous years’ work validating new services for the microelectronics industry played a crucial role, as did collaborative research between the large instruments and the industrial companies taking advantage of the Pac-G initiative.

our lineup of services for industrial

companies continues to expand

according to the targets set

To support the growth of our services

for industrial companies and

consolidate the business model

used by the characterization

program, a partnership with SeRMa

Technologies, a national leader in

electronic component failure and

reliability analysis, is currently in the final

negotiation stages. The year 2018 looks

very promising in terms of the expansion

of our innovative services lineup.

new resources to solidly anchor our

position of international leadership

The year 2017 also saw the GeNePI2

station reopen with substantially

improved performance thanks to

funding program from the French

government’s « Investments for

the future » (PIa). GeNePI2 is now

one of the most competitive 14 MeV

neutron sources in europe. GeNePI2’s

main competitors are in Great Britain

(chipir, STFc-ISIS), at ceRN (charm),

and in the United States (los alamos).

However, these facilities have much

more elaborate infrastructures and the

associated (higher) costs. Therefore,

our services business is seeing remarkable growth. Pac-G services were more

popular than ever in 2017,

with 50 days’ paid use for the irradiation of electronic circuits.

at Ill, a tomography machine that is unlike any other in the world—it combines

neutron-beam and high-resolution X-ray imaging—was built in 2016 and 2017 at

d50 in partnership with Grenoble-alpes University, Total, and edF. This cutting edge

non-destructive imaging technique can now be used for microelectronics research

and innovation projects. This new service rounds out the very-high-resolution

(sub-micron) imaging services already available at the Synchrotron and, in terms

of technical performance, is comparable to what is offered at the Paul Scherrer

Institute in Switzerland.

continued advanced characterization work

to support the microelectronics industry

Research on advanced interconnects for IRT Nanoelec’s 3d program moved

forward according to schedule, and a thesis was defended on december 12, 2017.

The research resulted in images of several dozen copper interconnect bumps,

paving the way toward a statistical approach that had previously been impossible.

The characterization work on the micro/nanoelectronics interfaces using neutron

techniques also produced some major findings for enhancing the reliability and

performance. one last achievement worth noting is the ongoing collaboration

between our characterization program and the eU Innovative Training Network

RadSaGa on testing the sensitivity of electronics to neutron background noise—tests

that are crucial for developing high-reliability systems for the space and aeronautics

industries, as well as for the automotive and healthcare industries in some cases.

Finally, congratulations to alexandra Fraczkiewicz, who won the Best Paper award

at the International Symposium for Testing and Failure analysis (ISTFa)

for her research on the copper pillars used for 3d integration.

The characterization program provides a unique environment that breaks down

the traditional silos that separate academic research on large scientific instruments,

technological research, and services for industrial companies.

2017 highlightS


41


40


J. Segura-ruiz, p. gutfreund, r. cubitt, a. ponard,

g. imbert, f. roze, o. gourhant, f. Bertin, M. tedjini,

f. fournel “combined neutron and X-ray

reflectivity characterization of key interfaces

for the microelectronics industry” international

conference on neutron Scattering (icnS), July 9-13,

2017 Daejeon (Korea)

The poster shows the three main subjects on the

characterization of interfaces for the microelectronics

industry developed at the Ill in the framework of

the IRT Nanoelec: i) low-k and UlK Beol (Back-end

of line) interfaces; ii) water at the interfaces Si/Si and

Sio2/Sio2 direct bonded; iii) SiGe interfaces and

layers. This poster aimed the publication of one paper

on the Journal Physics World (http://live.iop- pp01.

agh.sleek.net/physicsworld/reader/#!edition/editions_

neutron_2017/article/page - 22568).

J. Segura-ruiz, D. atkins, B. giroud, a. tengattini, e. andò, g. viggiani, r. cubitt

and J. Beaucour “D50: the industrial instrument at the ill” international

conference on neutron Scattering (icnS), July 9-13, 2017 Daejeon (Korea)

d50, the industrial instrument constructed at the Ill thanks to the help of the IRT

Nanoelec was described in detail in this poster. The main characteristics of the three

techniques available on d50 were provided and some images of the instrument,

as well as some results obtained were showed. The objective of this poster was

to present the possibilities offered by d50 to the industrial visitors present in the

IcNS2017 conference.

CHARACTERIZATION ON LARgE-SCALE INSTRUMENTS PROgRAM


43


42

cécile Weulersse “contribution of thermal neutrons to Soft error rate” conference

on radiation effects on components and Systems (raDecS) 2017, october 02-06, 2017

geneva (Switzerland)

RadecS is a reference conference in the field of tests and study of the radiation effects

(including neutrons) on components microelectronic components and systems.

The oral presentation given by cécile Weulersse from the airbus Group, reported on the results

obtained on the study of microelectronic technologies with different integration levels.

The most integrated technologies showed a higher contribution to the total error rate

from thermal neutrons. This study was done by airbus using the Pac-G facilities GeNePI2

at the lPSc and d50 at the Ill.

J. Segura-ruiz, J. Beaucour, n. gambacorti, f. villa, M. Baylac, e. capria,

e. Mitchel “platform for advanced characterization of grenoble (pac-g)”

28th european Symposium on reliability of electron Devices, failure physics

and analysis (eSref) 2017, September 25-29, 2017 Bordeaux (france)

This presentation was done for

the participants to the eSReF

2018 conference. The Pac-G was

presented to an enthusiastic audience,

interested in knowing more about the

characterization services offered by the

Pac-G in Grenoble. Some examples

using Synchrotron and Neutron

techniques were presented to

illustrate the possibilities opened by

the advanced techniques in terms

of sensitivity, resolution, speed and

complementary information.

Furthermore, the complementary

characterization and sample

preparation services offered by the

PFNc were presented.

J. Segura-ruiz, f. fournel and g. imbert “a Stronger interface”- article in the physics World on neutron Science.

There are multiple ways to explain the weak interaction

between the microelectronics industry and the neutron

source, but the main reasons are a lack of awareness

about neutron techniques and the difficulties industrial

users have in getting rapid access to the available facilities.

The Ill and the eSRF are among the institutes that have

partnered with IRT Nanoelec in an effort to open their

characterization facilities to the microelectronics industry,

and to adapt their techniques and services to the industry’s

needs. among the techniques available at the Ill, neutron

reflectometry seemed particularly well-adapted for

the needs of the microelectronics industry. The interplay

between the properties of the different layers that make up

microelectronics devices (such as Sio2, SiocH or SicN, among

others) and the robustness of the interfaces between layers

are both critical for the devices’ reliability and performance.

For instance, slight changes in the composition of the layers

or the presence of water at their interfaces can strongly affect

the fabrication process and the performance of the final

devices. Hence, characterizing layers and interfaces used

in the fabrication of microelectronics devices is paramount

in both the development of new microelectronic devices

and the improvement of existing ones. These techniques

are now beginning to be exploited and integrated

in the R&d process of the microelectronics industry,

and similarly in other areas of applied industrial research.



45


44

J. a clemente, g. hubert, J. fraire,

f.J. franco, f. villa, S. rey, M. Baylac,

h. puchner, h. Mecha, and r. velazco

“Seu characterization of three

Successive generations of cotS SraMs

at ultralow Bias voltage to 14.2 Mev

neutrons” in ieee transactions

on nuclear Science (tnS), vol. 99,

pp. 1 - 8, 2018 http://ieeexplore.ieee.

org/document/8278278/

This paper presents a SeU sensitivity

characterization at ultra-low bias

voltage of three generations of coTS

SRaMs manufactured in 130 nm, 90 nm

and 65 nm cMoS processes. For this

purpose, radiation tests with 14.2 MeV

neutrons were performed for SRaM

power supplies ranging from 0.5 V

to 3.15 V. The experimental results have

been cross-checked with predictions

issued from the modeling tool

MUlti-Scales Single event Phenomena

Predictive Platform (MUSca-SeP3).

large-scale Sels and SeFIs, observed

in the 90-nm and 130-nm SRaMs

respectively, are also presented

and discussed.

p. ramos, v. vargas, M. Baylac, f. villa,

S.rey, n. e. Zergainoh and r. velazco “

error-rate prediction for applications

implemented in Multi-core and

Many-core processors” - this work

is part of the vanessa vargas’s phD

thesis defended in april 2017

This paper proposes a methodology

for predicting the error rate

of applications implemented

in commercial off the shelf (coTS)

multi/many-core processors.

For validating the approach,

predicted error-rates of three devices

are compared to results issued from

14 MeV neutron tests. Three case studies

were implemented.

n. gambacorti “presentation of the nanocharacterization platform (pfnc)”

carac2017 Workshop, november 23, 2017 grenoble (france)

The PFNc has been created in 2006 in the Minatec campus and it is a federation

of the Nano characterization resources from three cea institute (leti, liten and

INac) based at cea/Grenoble. Today in the PFNc there are about 100 FTe

(between researchers and technicians), it has about 50 principal state-of-the-art

tools and its lab are over an area of about 3500m2. To maximize the use of

the equipment a partnership with SeRMa Technologies is in place. The PFNc

is composed of eight different centers of competence for physical and chemical

characterization: ion beam analysis (SIMS, ToF-SIMS, atom Probe, MeIS,…), X-ray

analysis (XRd, XRF, XRR, HRXRd,…), electron microscopy (SeM, HR-SeM, TeM,

HR-TeM, UHR-TeM, STeM, electron holography, electron tomography, eelS,

X-edS,…) scanning probe microscopy (aFM, UHV-aFM, electrical aFM,…), surface

analysis (XPS, UPS, PeeM, k-PeeM, leed, RHeed, Nano aUGeR,…), optical

characterization (RaMaN, micro- RaMaN, FTIR, ellipsometry (VUV, VIS, NIR),

Spectrophotometry,…), Nuclear Magnetic Resonance (NMR, dNP) and sample

preparation (dB-FIB, Tripod,…).

after the description of the PFNc, some examples of results obtained on

the PFNc has shown: defect analysis in GaN films, the use of TeM to obtain

multiple information from the same sample (morphology, composition, strain…),

combining aPT and TeM to locate B doping in cMoS devices, combining XcT

and FIB-ToF-SIMS to increase the knowledge on the material composition.

To conclude the presentation the collaboration model of the PFNc

and its worldwide collaboration network has been presented.

MoSFeT characterization using TeM and electron holography analysis

J. Segura-ruiz “how neutrons

can help your r&D process”

carac2017 Workshop, november

23, 2017 grenoble (france)

The caRac event, organized by

the Pac-G in association with other

characterization centers based

in Grenoble, aims to promote

the characterization services

provided by the partners among

the participants, coming mainly

from the industry. This talk showed

some examples using of neutron

techniques well adapted to solve

characterization problems of

the microelectronics and other

industries were presented.

J. Beaucour “platform for advanced characterization of grenoble: pac-g”

carac2017 Workshop, november 23, 2017 grenoble (france)

The caRac event, organized by the Pac-G in association with other

characterization centers based in Grenoble, aims to promote the characterization

services provided by

the partners among the

participants, coming mainly

from the industry. This talk

showed the structure,

partners and main

characteristics of the Pac-G.



47


46

ennio capria “platform for advanced characterization – grenoble” -

17th conference on Defects recognition, imaging and physics

in Semiconductors (Drip Xvii), october 8 - 12, 2017 valladolid (Spain)

The Platform for advanced characterization – Grenoble (Pac-G), has been

created as a pathfinder project, with the objective to enhance the effectiveness

and attractiveness of the large scale research infrastructures located in the

Grenoble european Photons and Neutrons (ePN) campus: a) the eSRF, one of

the most brilliant synchrotron light sources in the world, b) the Ill the most

intense neutron source worldwide.

a. fraczkiewicz, S. Moreau, t. Mourier, p. Bleuet, p.-o. autran, e. capria,

p. cloetens, J. Da Silva, S. lhostis, f. lorut

presented by alexandra fraczkiewicz, best student paper,

“Making synchrotron tomography a routine tool for 3D integration failure

analysis through a limited number of projections, an adapted sample

preparation scheme, and a fully-automated post- processing” -

43th international Symposium for testing and failure analysis (iStfa 2017),

november 5 - 9, 2017, pasadena (uSa)

3d integration, which aims at reducing the footprint of microelectronics devices,

takes more and more importance in the microelectronics industry. In order

to image the three- dimensional objects created for the wafer or die bonding

processes, new tools must be developed. In fact, those objects can be up to

several microns large, while the defects they feature can be as small as a few

nanometers. Here, we focus on two types of objects, which are copper pillars

(typically 20 µm of diameter) and copper pads used in hybrid bonding,

which measure 5 µm in width.

Tomography is a technique based on the successive acquisition of the sample

projections, at different angles. an algorithm then allows for the reconstruction

of a 3d volume representing the original sample. lab x-ray tomographs provide

a solution for the 3d imaging of large samples. They however lack the spatial

resolution, as they are limited to resolutions close to 1 micron. Synchrotron-based

tomography performed on recent beamlines can offer resolutions down

to several tens of nanometers. However, as the experimental setup is still quite

heavy, strategies must be found to increase the throughput of samples, in order

for the technique to require little human intervention and to provide high

resolution statistical information. In this study, three strategies that allow for

such features are presented. a first one has been presented in a former work and

relies on improving the sample preparation scheme. Moreover, the reduction

of the number of projections, together with a fully automated post- processing,

reduce dramatically the whole process time and the human intervention needs.

a. fraczkiewicz, f. lorut, g. audoit, e. Boller, e. capria, p. cloetens, J. Da Silva,

a. farcy, t. Mourier, f. ponthenier, and p. Bleuet “3D high resolution imaging

for microelectronics: a multitechnique survey on copper pillars” Submitted

in ultramicroscopy (2017)

In microelectronics, recently developed 3d integration offers the possibility to

stack the dice or wafers vertically instead of putting their different parts next to

one another, in order to save space. as this method becomes of greater interest,

the need for 3d imaging techniques becomes higher. This paper proposes

a study about different 3d characterization techniques applied to copper pillars,

which are used to stack different dice together. destructive techniques such

as FIB/SeM, FIB/FIB, and PFIB/PFIB slice and view protocols have been assessed,

as well as non- destructive ones, such as laboratory-based and synchrotron-based

computed tomography. a comparison of those techniques in the specific

case of copper pillars is given, taking into account the constraints linked to the

microelectronics industry, mainly concerning resolution and sample throughput.

a. even, c. richter, M.-i. richard, y.M.

vaillant, p. ferret, o. ledoux, D. Sotta,

e. guiot, t. Schulli, and a. Dussaigne

“Synchrotron X-ray study of ingan

layer grown on relaxed ingan

substrate” iSS leD 2017, 8-12 oct 2017,

Banff, canada

To achieve long wavelength emission

with InGaN-based leds, large indium

contents are needed in the active layer.

Yet, a limitation to the incorporation

of indium exists because of the strain

induced by the lattice mismatch

between InGaN active layer and the GaN

substrate, a phenomenon known as the

compositional pulling effect. We recently

proposed to tackle this issue by growing

a full InGaN structure on a relaxed InGaN

substrate. an easier In incorporation is

expected owing to a reduction of strain.

The InGaN substrate called InGaNoS

is manufactured by Soitec using their

Smart cut™ technology. Three nuances

of InGaNoS with lattice parameters of

3.190, 3.200 and 3.205 Å are available.

InGaN/InGaN quantum wells grown

on InGaN buffer on InGaNoS showed

strong redshift with increased InGaNoS

lattice parameter allowing emission

from green to amber range. Still, more

characterizations of the structure, and

especially the evaluation of strain in the

InGaN buffer layer, are needed. To deeper

understand the relation between the

substrate and grown InGaN layer, an X-ray

diffraction study was lead at european

Synchrotron. Sample consisted of a

200 nm thick InGaN layer grown on

InGaNoS with a lattice parameter of

3.190 Å was measured. a mapping of real

(2d) and reciprocal (3d) space on

symmetric and asymmetrical Bragg

reflections was performed at a resolution

of 270 nm. a detailed data analysis reveals

the full strain/tilt pattern in the buffer

layer that is imposed by the substrate.


Results of tomography on electromigration samples. a) automatically reconstructed volume. b) Segmented volume. The red part

represented the volume of copper depleted by electromigration

Slices of copper pillar reconstructions from a) Id16a at 17.05 ke V (cu P 4) b) Id16a at 33.6 keV (cu P 4) c) lab tomography (cu P 3) d) Id19 (cuP 5). every figure contains an XZ view of the pillar (with a plain red frame),

an XY view of the interface containing voids (in black) and intermetallic alloys (with a dashed blue frame), and a zoom-in view of the latter (with a plain green frame).

e) Profiles across voids on reconstructions obtained from Id16a (33.6keV), Id19, and lab tomography.


49


48

t. nhi tran, v.a. oliveira, D. camel, D. caliste, J. härtwig and J. Baruchel

“combining qualitative and quantitative X-ray Bragg diffraction imaging

at the eSrf to study defects in semiconductors: the example of pv

silicon” - 17th conference on Defects recognition, imaging and physics

in Semiconductors (Drip Xvii), october 8 - 12, 2017 valladolid (Spain)

The need for high quality diamonds, for electronics, detectors and X-ray optics

purposes, and for “inexpensive, reduced- defects” silicon for photovoltaic (PV)

purposes, has strongly promoted the use of X-ray Bragg diffraction imaging

(“X-ray topography”) techniques to study their defects. This led us to develop,

at the eSRF, enhanced capabilities in the portfolio of Bragg imaging techniques

we now propose. This includes some automation, and a new diffractometer

on the BM05 beamline. Within this portfolio, projection and section white beam

topography and monochromatic Rocking curve Imaging (RcI) [1] are mostly

used to qualitatively and quantitatively characterise the crystalline quality,

in deposited layers, deep bulk structures and the interface between them, with

an angular precision in the µrad range and a spatial resolution in the µm range.

t. nhi tran “combining qualitative and

quantitative diffraction topography

at the eSrf to characterise pv silicon

crystals” - 8th photovoltaic technical

conference 2017 (pvtc 2017)

april 26-28, 2017, Marseille (france)

Silicon is today the most widely-used

material for PV applications.

Both the quality of PV-Si substrates and

the preparation of the device, strongly

influence the PV efficiency and price of

the solar-cell. We have therefore studied

both the growth of “mono-like” Si

(less expensive than czochralski Si, but

sufficient quality for PV applications)

and aspects of the cell processing

(al back electrical contacts).

t. Schülli “the Bright future

of nanoscience and Synchrotron

radiation” - nanoinnovation 2017,

September 26 - 29, 2017, rome (italy)

The success of nanoscience

and technology is mainly based on

a comprehension, control and design

of nanostructures and nanomaterials.

These penetrate all fields of functional

materials from biocompatible implants

to new electronic devices. The rapid

development of the availability of

synchrotron radiation (SR) throughout

europe and in interaction with the very

active user community, SR has become

a key tool in material science, chemistry

and biology over the last decade.

With the natural evolution that

nanoscience and technology have

brought to those fields the synchrotron

beamlines and techniques have evolved

in particular with adapted instruments

put into operation during the first phase

of the eSRF upgrade (2009-2015).

The further improvement of X-ray

technologies and in particular the

boost in brilliance that the european

Synchrotron will experience during

its conversion to the extremely Bright

Source (eBS) will dramatically enhance

the importance of this tool for the

characterization and imaging

of the nanoworld.

a. fraczkiewicz, p-o autran, e. capria, p. cloetens, J. Da Silva, S. lhostis,

f. lorut, S. Moreau, th. Mourier and Dr. pierre Bleuet “Making Synchrotron

tomography a routine tool for 3D integration failure analysis through

a number of projections, an adapted Sample preparation Scheme,

and a fully-automated post-processing” 43th international Symposium for

testing and failure analysis (iStfa 2017), november 5 - 9, 2017, pasadena (uSa)

Here we present and illustrate the possibilities given by the newly-built Id16a

nanotomography beamline at eSRF (european Synchrotron Radiation Facility)

for the field of microelectronics. We focus more specifically on the assets

of a synchrotron source regarding highly-resolved and quick tomographies,

as well as strategies aiming at even faster acquisitions and processing

of the tomographic data, when applied to 3d devices.

during this study, we addressed the different steps of the tomography

procedure, and improvements presented here enabled us to get results faster,

but also in an automated way, involving as little human intervention as possible.

The study presents an assessment of synchrotron-based tomography as can be

performed on the Id16a beamline, in the specific case of, but not limited to,

3d integration devices, while keeping in mind the performances of conventional

analysis methods such as TeM and SeM. Given the industrial context of

microelectronics failure analysis, we will focus on three major parameters:

the time needed to get a reconstructed volume from a piece of wafer,

the volume resolution, and the statistical relevance of the final result relatively

to the fabrication process. This work has been funded by the IRT Nanoelec

program. The authors acknowledge access to the Nano characterization

platform (PFNc) at the Minatec campus in Grenoble. The experiments were

performed on the Id16a beamline at the eSRF (european Synchrotron Radiation

Facility, Grenoble, France), in the frame of the long term project ma2240.

t. nhi tran “new aspects of diffraction topography at the eSrf: application

to the characterisation of diamond crystals” 5th french Japanese workshop

on Diamond for electronics devices, okinawa (Japon)

We have used Grazing Incidence X-ray diffraction (at the Id01 beamline, eSRF)

to study lattice parameters and damage (strain, mosaic spread) both in diamond

substrate surfaces and in thick (10~50um) overgrown boron doped diamond

layers. Micro and nano section topography has been carried out (at BM05

and Id06, eSRF) using rocking curve imaging techniques to study defects

propagating from the substrate to the overgrown layer and its influence to the

final electronic performance of Shotky diodes. The studies are involving of

many commercially sourced diamond substrates from different manufacturers,

with the MWcVd overgrowth being performed at the IaF-Germany.



51


The PULSE (Programme Usages des technologies de Liaison et Soutien aux Entreprises) program, launched in 2012, helps IRT Nanoelec’s industrial partners leverage nanoelectronics

for innovative products and services targeting emerging markets like new mobility, the Silver Economy, and Smart Cities. Each year, in-house projects involving academic research and industrial R&D professionals from IRT Nanoelec’s founding partners generate:

Specifications that take into account uses, market needs, and cybersecurity

Demonstrators and/or prototypes either at technology platforms on in realistic environments (a city, a vehicle, etc.)

Evaluations of technical performance and user-centered assessments.

Bruno charratpulSe prograM Director

pulSe (uSeS of integrateD

SySteMS anD Supportfor coMpanieS)

prograM


52 53


2017 hIghLIghTs

PULSE PROgRAM

an innovation club to round out the products and services offered by irt

nanoelec founding partners

The challenge is to ensure that the IRT Nanoelec Technologies Platform maintains

the highest possible level of excellence and remains attractive to companies so that

the platform’s tools and research results are effectively used by IRT Nanoelec’s

industrial partners to design innovative new products and services. In 2017,

eight projects were run to develop innovative solutions available for enhancing the

platform.

Silverlab, for example, supported by Schneider electric in developing and releasing

a new assisted living solution targeting the nursing facility market—a market that

grew by 1,300% from 2015 to 2017. The Perfect project to develop technologies for

driverless vehicles resulted in a prototype of a new scene-analysis solution—crucial

for self-driving vehicles. The results of this project were leveraged in partnerships

with Transdev, Renault, and Infineon, and spurred driverless shuttle manufacturer

easyMile to consider becoming a member with Founder status for 2018–2020.

The findings of other projects on self-powering buildings (Reli2) and digital trust

(Poc Blockchain) are currently being used in the HIKaRI project, an energy-plus city

block project being built by construction company Bouygues in lyon.

transferring results to associate partners

another one of our goals is to ensure that our new associate partners have access

to the assets and tools available at IRT Nanoelec and to conduct contract R&d

projects for these partners. In 2017 several such partnership agreements were signed

with major industrial companies like Transdev, Philips, and Schneider electric.

The program also engineered and managed several eU-backed collaborative

research projects (including FeSTIVal, oRGaNIcITY, WISe IoT, and BIGcloUT),

which co-financed actions beneficial to the IRT Nanoelec Technologies Platform. In

early 2016 IRT Nanoelec was selected to be part of a consortium of Silver economy

stakeholders for the eU call for projects “IoT-01-2016: large Scale Pilots,” to speed up

the market release and adoption of IoT solutions. The 42-month project has a total

budget of €20 million and work began in 2017.

a sharper focus on digital

trust to enhance our support

to businesses

The PUlSe program’s focus had been

to implement new tools and methods

to more effectively transfer research

results to new associate partners.

Since 2016, the program has sharpened

its focus on digital trust, a need that

had been expressed by the program

partners. as a result, in-house efforts

in certain areas were scaled back and

the current plan is to potentially work

with the cea open Innovation center

rather than develop dedicated resources

in-house at IRT Nanoelec.

French society is seeking solutions

to several major challenges. an aging

population and more efficient use

of energy resources (transportation,

buildings) are at the top of the list.

Judicious use of micro and

nanotechnology can enable devices

to communicate with each other,

producing data crucial to the efficient

allocation of resources (human, financial,

etc.). as the Internet of Things gains

traction, new services leveraging data

management are cropping up

everywhere. However, high-profile

cyberattacks (whether intentionally

produced for academic research

purposes or real-world attacks by

hackers) have raised the average

citizen’s awareness of the risks of

making the digital transition too quickly

and without the necessary safeguards.

The PUlSe program set up a platform focusing on integration and experimentation: the IRT Nanoelec Technologies Platform.

The program’s R&d strategy is built on three pillars:as medical systems, cars, and industrial and urban equipment become more

connected and autonomous, new vulnerabilities are identified and covered by the

media, revealing them to the general public. For industrial companies that have

not sufficiently protected their products, these incidents can damage their brand

image, cost them money, and even land them in court. The United States Federal

Trade commission brought charges against a manufacturer of connected devices in

2017 on the basis that the manufacturer’s IP cameras and routers were not secure

enough, potentially putting thousands of customers at risk.

The public’s perception of cybersecurity and its role in the widespread adoption of

digital technology spurred the partners of the PUlSe program to focus on the topic

of digital trust in the third phase of the program. The goal is to determine how

nanoelectronics can help develop new services for:

Greater operating safety when a context (such as in a building or around

a moving vehicle) is entered automatically

More robust cybersecurity to protect the confidentiality and anonymity

of data generated in IoT systems (energy production, building monitoring,

etc.) and reassure users that their privacy is protected and that digital systems

are robust (in terms of both failures and malicious acts)

Improved ergonomics to simplify the implementation of security strategies

(commissioning) through new tools for the personnel in charge of these

generally complex and sophisticated implementation projects

digital trust can only be created by getting all stakeholders to work together, from

technology experts and professionals from industry who know their customers and

business risks inside-out to experts in the social sciences and humanities with

knowledge of the legal and regulatory frameworks for digital technology. The PUlSe

program is fairly unusual (there is nothing quite the same, either in France or anywhere

else in the world) in that it gets all stakeholders working together on such strategic issues.


54 55


2017 hIghLIghTsfaster lifi wireless communications

luciom was founded in october 2012 to design, manufacture, and commercialize

liFi (light Fidelity) communications solutions. liFi is a wireless communications

technology that uses visible light to transmit data. Specifically, liFi harnesses leds’

capacity to switch on and off very rapidly (faster than what the human eye can see)

to send signals.

luciom became an associate partner of IRT Nanoelec to develop specific technology

bricks. Three research contracts were completed successfully. luciom confirmed its

interest in using the technologies when it signed, on august 1, 2016, an agreement

outlining some of the conditions for a future IP license based on the principles in the

three previous research contracts.

technologies for driverless cars on display

automation technologies are advancing rapidly, spurred by new demands from the

automotive industry—in other words, driverless cars. capturing context in complex,

dynamic environments regardless of lighting, precipitation, and other changing

conditions remains a major hurdle to ensuring the safety and security of these

technologies—and the economic viability of an entire emerging industry. The Perfect

project was set up to integrate, develop, and promote context-capture technologies

to enhance the safety of driverless cars.

a demonstrator of a technology called SigmaFusion™, which operates with

a STMicroelectronics microcontroller, was presented at leti’s exhibit booth

at the 2017 consumer electronics Show in las Vegas. one of the goals for 2017 was

to investigate porting the technology to a certified platform (aSIl-d) in the sense

of the ISo 26262 standard.

SigmaFusion™ was integrated onto a commercially-available aSIl-d-certified

platform. The integration provided an opportunity to demonstrate the data-fusion

technology’s capabilities with the ultimate goal of integrating it into a product

certified for use in driverless cars. The figure below shows how SigmaFusion™

performed compared to other studies at the current state of the art.

BmwF. Homm [IV’10]

continentalm. schreier

[ITSc’15]

mercedesd. Nuss [IV’15]

cea (2015)[IcRa’16]

cea (2016)[dac’16]

cea (2017)[IT’S17]

Performance 1 x0,47 x0,39 x5,06 X1 X1 (<50%CPU)Power 204 W 95 W 80 W 1 W 0,5 W 1,5 W

HW Nvidia GeForce 268GTX Intel’Core [email protected] GHz Desktop Single Cortex A9 @900 MHz

µC Cortex M7@200 MHz

µC Aurix TriCore@300 MHz

ISO26262 ASIL-D Non Non Non Non Non Possible[IV’10] F. Homm, N. Kaempchen, J. ota and d. Burschka. efficient occupancy grid computation on the GPU with lidar and radar for road boundary detection. In Ieee IV, pages 1006-1013, June 2010. [STSc’15] M. Schreier, V. Willert and J. adamy. compact Representation of dynamic driving environments for adaS by Parametric Free Space and dynamic object Maps. Ieee ITSc 2015. [IcRa’16] T. Rakotovao, J. Mottin, d. Puschini, c. laugier. Multi-sensor fusion of occupancy grids based on integer arithmetic. In IcRa 2016. [dac’16] T. Rakotovao, J. Mottin, d. Puschini, c. laugier. Integration of multi-sensor occupancy grids into automotive. ecUs. In dac 2016.

a demo was given at the 12th ITS european congress in Strasbourg, France, held

on June 19–22, 2017. a report (d3 – démonstration de SigmaFusion™ sur plateforme

certifiée aSIl-d) describes the development work completed and the demo given

at the congress.

activage project underway

In 2016, the european commission issued a call for projects (IoT-01-2016: large Scale

Pilots) under the Horizon 2020 research and innovation framework. The activage

project, which IRT Nanoelec is coordinating in France, was selected by the european

commission for the “aging Well” segment of the initiative and granted a budget

of €20 million for the 42-month duration of the project.

activage will evaluate digital solutions to help the elderly live at home longer

and better and investigate potential business models for these solutions. a total

of 50 partners in nine european countries are participating. The French node of

the project, with ten partners, is using the Isère district as a testing ground for the

solutions. Two types of homes were selected for the tests in France: independent

housing for the elderly, and nursing and rehabilitation centers. a total of 75 homes

and ten nursing and rehab rooms will be equipped with the solutions being tested.

The solutions will first be developed and tested at the IRT Nanoelec Technology

Platform. In 2017 a life-sized testbed representing a nursing and rehab center patient

room with bathroom was set up at the platform.

The testbed will be used to install, test,

and complete functional validation

of the solution selected in realistic

conditions, thereby reducing the

risks of problems occurring when the

solution is implemented in the field.

The technological solution selected has

already been installed on the testbed

and is currently being evaluated.

The first algorithms were developed and

are undergoing functional validation

testing. a room at an actual nursing and

rehabilitation facility (les Granges de

Korian) has also been equipped with

the solution and will be fully installed

and operational by the beginning

of 2018, pending the initial results

of experiments on the testbed.

once the first actual patient room is up

and running, feedback will be used to

inform future installations (in 2018) for

each of the panels. The initial security

initiatives are also expected to begin,

with a focus on IoT security certification-

related issues.

PULSE PROgRAM


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56


l. h. J. Kikkert, n. vuillerme, J.p. van

campen, B. a appels, t. hortobagyi

and c. J. lamoth “gait characteristics

and their discriminative power

in geriatric patients with and without

cognitive impairment”- Journal of

neuroengineering and rehabilitation

a detailed gait analysis (e.g., measures

related to speed, self-affinity, stability,

and variability) can help to unravel the

underlying causes of gait dysfunction,

and identify cognitive impairment.

However, because geriatric patients

present with multiple conditions that

also affect gait, results from healthy old

adults cannot easily be extrapolated

to geriatric patients.

For the present cross-sectional study,

25 healthy old adults recruited from

community (65 ± 5.5 years), and 70

geriatric patients with (n = 39) and

without (n = 31) cognitive impairment

from the geriatric day-clinic of the Mc

Slotervaart hospital in amsterdam (80

± 6.6 years) were included. Participants

walked for 3 min during single and dual-

tasking at self-selected speed while 3d

trunk accelerations. In conclusion, gait

outcomes related to speed, regularity,

predictability, and stability of trunk

accelerations were most important in

the characterization of patient groups

and revealed with a large discriminative

power. While geriatric patients vs.

healthy old adults walked slower, and

less regular, predictable, and stable, we

found no differences in gait between

geriatric patients with and without

cognitive impairment.

ch. villemazet, M. passot, i. chartier, f. coulon-lauture, and n. vuillerme.

“ghanDileo: developing an indoor guidance system for visually impaired people

using a user-centered design” - 16th international Mobility conference,

June 26 -30, 2017 Dublin, (irlande)

The aim of the Ghandileo project is to design, implement, assess and deploy an

innovative indoor guidance system specifically designed to enhance the safety

and independence of people with any kind of disabilities navigating within their

workplace. The paper presents what we have done to support people who are blind

or visually impaired who travels indoors with the best precision.

We have implemented a user-centered design to support the entire development of

an indoor guidance system for blind and visually impaired people. This smartphone-

based system has demonstrated to be useful and easy to use, and hence, seems of

added value to the intended users.

l. h. J. Kikkert, M. h. De groot, J.p. van campen, J. h. Beijnen, t. hortobagyi,

n. vuillerme, and c. J. lamoth “gaith Dynamics to optimize fall risk assessment

in geriatric patients admitted to an outpatient Diagnostic clinic”, ploS one,

on line scientific review (public library of Science)

Fall prediction in geriatric patients remains challenging because the increased fall

risk involves multiple, interrelated factors caused by natural aging and/or pathology.

The specificity of the model using patient characteristics was 60% but reached

80% when cognitive and gait outcomes were added. The inclusion of cognition and

gait dynamics in fall classification models reduced misclassification. We therefore

recommend assessing geriatric patients’ fall risk using a multi-factorial approach

that incorporates patient characteristics, cognition, and gait dynamics. In conclusion,

geriatric patients represent a vulnerable population with an increased risk for falling.

Fall risk assessment including modifiable fall risk factors revealed high classification

accuracy (aUc = 0.93). although patient characteristics can accurately identify fallers,

the evaluation of executive function and gait dynamics reduced misclassification

with an increase in specificity from 60% to 80%. Therefore, we underscore the need

for a multifactorial approach in fall risk assessment in geriatric patients, including

a comprehensive evaluation of patient characteristics, cognitive function, and gait

performance. These fall risk factors should ultimately be targeted by individualized

interventions to reduce fall risk.

r. Balaguier, p. Madeleine, K. rose-Dulcina and n. vuillerme “trunk kinematics

and low back pain during pruning among vineyard workers—a field study

at the chateau larose-trintaudon” - ploS one, on line scientific review

(public library of Science)

The prevalence of low back disorders is dramatically high in viticulture. Field

measurements that objectively quantify work exposure can provide information

on the relationship between the adopted trunk postures and low back pain. The

purposes of the present study were three-fold to carry out a kinematics analysis

of vineyard-workers’ pruning activity by extracting the duration of bending

and rotation of the trunk, to question separately the relationship between the

duration of forward bending or trunk rotation with low back pain intensity

and pressure pain sensitivity and (3) to question the relationship between the

combined duration of forward bending and trunk rotation on low back pain

intensity and pressure pain sensitivity. This study reinforces the necessity of

further field measurements with longer time of observation and larger sample

size to confirm our findings and to investigate other variables specifically the

effects of potential lBP confounders such as gender, age or job seniority to

accurately quantify the risk exposure.

PULSE PROgRAM


59


58

l. rummelhard, J. lussereau,

J.a. David, c. laugier, S. Dominguez,

g. garcia and p. Martinet “perception

and automation for intelligent

mobility in dynamic environments” –

Workshop on robotics and vehicular

technologies for Self-driving cars

(icra 2017), June 2017, (Singapour)

In this paper we present the design

and integration of a perception and

automation system on an experimental

vehicle, and first experimentations on

real data. The vehicle has been modified

in order to be able to control the

steering, throttle, brake and gearshift

by computer in a simple manner. a

modular hardware architecture that

minimizes the length of the wires

reducing the risk of electrical noise by

installing the signal modules close to

the corresponding actuators has been

used in our approach. a car interface

module allows controlling the individual

modules by computer at a high rate (up

to 1 KHz). To close the low level control

loop, the status of the car is obtained by

reading directly the caN bus of the car.

The system showed promising results,

opening the opportunity of further

experiments (automatic trajectory

diversion for risk avoidance).

l. rummelhard, a. paigwar,a. nègre and c. laugier “ground estimation

and point cloud segmentation using spatiotemporal conditional field” -

28th intelligent vehicule Symposium (ieee- iv2017, June 11 - 14, 2017 redondo

Beach (uSa)

In this paper was presented a 3d point cloud ground segmentation system,

based on a dynamic estimation of local ground elevation and slope. The system

models the ground as a spatio-Temporal conditional Random Field (STcRF),

dividing the surrounding into interconnected elevation cells, affected by local

observations and spatio-temporal dependencies. Ground elevation parameters

are estimated in parallel in each cell, using an interconnected expectation

Maximization algorithm variant. The approach, designed to target high-speed

vehicle constraints and performs efficiently with highly-dense (Velodyne-64)

and sparser (Ibeo- lux) 3d point clouds, has been implemented and deployed

on experimental vehicle and platforms, and are currently tested on embedded

systems (NVIdIa Jetson TX1, TK1). The experiments on real road data, in various

situations (city, countryside, mountain roads), show promising results.

S. Mandigout, J. lacroix, B. ferry,

n. vuillerme, M. compagnat and

J.c Daviet “can energy expenditure

be accurately assessed using

accelerometry-based wearable

motion detectors for physical activity

monitoring in post-stroke patients

in the subacute phase?” european

Journal of preventive cardiology

In the subacute stroke phase, the

monitoring of ambulatory activity and

activities of daily life with wearable

sensors may have relevant clinical

applications. Twenty-four patients (age

68.2_13.9; post-stroke delay 34_25 days)

voluntarily participated in this study.

each patient underwent a scenario of

various everyday tasks (transfer, walking,

etc.). during the implementation,

patients wore 14 wearable sensors

(armband, actigraph GT3X, actical,

and pedometer) to obtain an estimate

of the energy expenditure. The actual

energy expenditure was concurrently

determined by indirect calorimetry.

except for the armband worn on the

non-plegic side, the results of our

study show a significant difference

between the energy expenditure values

estimated by the various sensors and

the actual energy expenditure when

the scenario is considered as a whole.

The present results suggest that, for a

series of everyday tasks, the wearable

sensors underestimate the actual

energy expenditure values in post-

stroke patients in the subacute phase

and are therefore not accurate. Several

factors are likely to confound the results:

types of activity, prediction equations,

the position of the sensor and the

hemiplegia side.

PULSE PROgRAM

c. villemazet, c. guyon-gardeux, i. chartier,

n. vuillerme. “actiSenS : une technologie

de l’interaction numérique dédiée à la rééducation

à domicile de personnes atteintes de troubles

cognitifs” – poster

a study of participative design was driven with end-

users. This study allowed to define the functional

and technical specifications of new electronic tool

of recognition of the gesture designed to equip

the objects of current life. Thanks to its real time

multimodal, actisens project allowed to develop and

to validate useful algorithms of recognition of the

movement for the reeducation.

l. h. J. Kikkert, n. vuillerme, J.p. van campen, B. a appels, t. hortobagyi, and

c. J. lamoth “the relationship between gait dynamics and future cognitive

decline: a prospective pilot study in geriatric patients” international

psychogeriatrics

Medical developments have substantially extended human lifespan. an increase

in age, however, comes hand-in-hand with co-morbidities, such as cognitive

decline, muscle weakness, frailty, polypharmacy, and falling. 19 geriatric patients

(age 80.0±5.8) were followed for 14.4±6.6 months. an iPod collected three-

dimensional (3d) trunk accelerations while patients walked for 3 minutes. The

increase in gait regularity and predictability possibly reflects a loc due to

age- and cognition-related (neuro) physiological decline. Because dynamic

versus traditional gait outcomes (i.e. gait speed and - variability of - stride

time) were more strongly correlated with future cognitive decline, the use of

wearable sensors in predicting and monitoring cognitive and physical health in

vulnerable geriatric patients can be considered promising. However, our results

are preliminary and do require replication in larger cohorts. In conclusion, the

present pilot study revealed that a more regular and predictable gait pattern

was correlated with future cognitive decline in geriatric patients admitted to an

outpatient diagnostic clinic. Those results could reflect a loc of the aging NMSS.

In addition to traditional outcomes, such as gait speed, trunk outcomes derived

from wearable sensors are promising indicators of cognitive as well as physical

decline. Hence, we recommend the incorporation of a non-invasive detailed gait

analysis in predicting, diagnosing, and monitoring health status in vulnerable

geriatric patients. However, our results and interpretations are preliminary and

need replication in larger cohorts, as for now, our conclusions are based on a

small sample size and a relatively short follow-up period.

Illustration of 3d Point cloud segmentation following the road slope. Ground points are green, obstacles are pink.


61


In France, small and mid-sized businesses have a more difficult time accessing innovation than large

corporations. They find it hard to adopt the most recent technologies—the very same technologies likely to provide them with a long-term competitive advantage. These challenges are due mainly to a lack of information about what technologies are available and how they can be used, the need for rapid return on investment (developing new technologies from scratch—a process that takes at least five years—is simply not possible for smaller companies), an inability to finance R&D projects, and little to no in-house knowledge of electronics or innovation marketing.

The Easytech program was created specifically to respond to these challenges and bring the best in micro and nanoelectronics and digital technology R&D to small and mid-sized businesses. The goal is to get a large number of technology bricks in electronics and embedded systems to these companies. The technologies available are developed by the labs and technology platforms of two IRT Nanoelec partners, the CEA and grenoble Institute of Technology. The Minalogic cluster and Jessica France, a non-profit group (both IRT Nanoelec members), are also involved in the Easytech program. They intervene before and after R&D programs to:

Identify businesses that could participate in the program, and, as necessary, familiarize them with the potential digital technologies can bring to their businesses; introduce them to the appropriate contacts

DaMien coheneaSytech prograM Director

eaSytech prograM


63


2Measure the impact of the projects on the growth of the participating businesses

Businesses participating in the Easytech program can receive advice and audits and take part in creativity sessions and R&D projects.The program targets companies from all industries. Of course, those in the electronics and IT industries,

but also—and very broadly—those in more traditional industries like steel, mechanical engineering, farming and food manufacturing, automotive components, lighting, and more. Access to advanced technology bricks can give these more traditional companies opportunities to diversify, improve their current products, and make their manufacturing processes more efficient. Digital technology is now an undisputed and crucial enabler for SMBs in all industries that wish to stay competitive and grow over the long term.

Easytech, which was first made available to businesses in the Auvergne-Rhône-Alpes region, is gradually expanding to cover all of France. Projects involving companies from 37 districts across France have received Easytech support to date.

EASyTECH PROgRAM


64 65


2017 hIghLIghTs

EASyTECH PROgRAM

easytech, a collaborative r&D program designed specifically for SMes

The easytech program involves a large number of stakeholders: research labs,

partners, and local governments, as well as innovation and financing organizations

like Bpifrance, technology-transfer specialists, and angel investors, plus other support

programs like eNe (espace Numérique entreprise).

These stakeholders are represented on the committee that approves easytech

projects—providing another way for partners to stay in touch with the companies

they are supporting and learn about new innovation projects.

easytech focuses on R&d, providing support and partial funding for the completion

of a demonstrator system or prototype in conjunction with an IRT Nanoelec partner

lab. Bpifrance, angel investor club Réseau entreprendre, and/or government partners

can also get involved at crucial stages of the project (prototyping, recruitment, export

sales, etc.).

all stakeholders are there for the same reason: to help transform each SMe’s project

into a marketable product that will create jobs and additional revenue.

For the past six years Bpifrance, Réseau entreprendre, and technology-transfer

organization linksium have been members of the easytech project selection

committee. To date, more than 130 demonstrator systems and prototypes have been

approved by the project partners.

Secteur d’activitéthe objective for the coming years is to ramp up the program to 50 projects

per year with SMes based in france resulting in marketable products and

services based on the r&D completed.

The year 2017 was an important one for the easytech program. Following the

auvergne-Rhône-alpes regional government’s call for projects at the end of 2016,

we signed an agreement with the Regional council to continue to facilitate SMes’

access to the technologies developed by IRT Nanoelec partner labs. We also built

strong relationships with local governments in Grenoble, Valence-Romans, Thonon,

annemasse, and St. etienne to boost our impact on local companies. These local

governments have placed their trust in easytech by contributing 10% financing to

projects involving businesses from their local communities in addition to the 20%

provided by the region.

The following local governments have partnered with easytech:

In 2017, 38 easytech projects were completed, bringing the total number of projects involving IRT Nanoelec and industrial companies

to 205 since the program started. These projects involved 151 companies (142 of which were SMes). and, in line with the program’s founding objectives, the companies that have participated represent all sectors of the economy, including traditional manufacturing industries. The support of local government is crucial to promoting this program, which is why IRT Nanoelec signs agreements with local authorities, which provide 10% of the financing for projects completed by companies from these local communities. and the positive results of the regional “RdI Booster” call for projects will mean additional project financing from the region for 2017–2018 and 2019.

2017 highlightS

1 % automobile, équipement automobile

19 % Maintenance, mécanique, machines

3 % PlV, bois, papier, carton

10 % Santé

2 % Services, ingénierie, bureau d’étude

14 % Sport

9 % Transport

6 % Bâtiment, construction, mobilier urbain

24 % electronique, informatique

8 % loisir

2 % environnement, développement durable

2 % energie


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titre SectionDroite

Style § « Edito lettrine »Style § « Edito »

titre éDito Style § cyan Style carctère

eDucation & training prograM

The IRT Nanoelec Education & Training program is built on three pillars:

Initiatives that cross the frontiers between technology development, user-centered innovation, and the markets they create to effectively factor in the capacity of nanoelectronics to drive the widespread adoption of new technologies across all industries

Constant feedback from companies on their needs and expectations to ensure that our education and training programs target these needs: - The Strategy Committee represents the ecosystem’s partners and business community, helping to determine priorities and approve decisions - A survey of nanoelectronics-industry companies to determine their future recruitment needs and what competencies these positions will require

The development of new experiential learning approaches to promote the acquisition of new skills and help bring learners and businesses closer (through project-based learning or learning in real-world situations, for example)

IRT Nanoelec provides funding solely for the development of new courses.

paScal lefort, naDine guilleMot eDucation & training prograM co-DirectorS


68 69


2017 hIghLIghTs

EDUCATION & TRAININg PROgRAM

Main conclusions:

over the next decade, jobs in the

micro and nanoelectronics industry

will change significantly. This will result

in difficulties filling certain positions

(production line and maintenance

technicians, for example), certain

jobs disappearing (operators), others

growing (design, artificial intelligence,

network architectures, etc.), and, finally,

other jobs changing (R&d engineer,

project manager, etc.).

results of the micro and nanoelectronics-industry survey of future

recruitment needs and the associated competencies

a second round of the recruitment and competency survey kicked off in 2016 to

round out and update the first survey in 2014. The methodology was overhauled to

compensate for the challenges of obtaining an accurate vision of the future solely

through interviews with ceos. Therefore, the interviews were conducted following a

strategic analysis of the challenges micro and nanoelectronics companies are facing.

The second survey, which was completed in July 2017, took place in several stages:

The findings of consulting firm Katalyse

Meetings with major industry federations and other stakeholders (acSIel,

UIMM, STMicroelectronics) to compare the results presented by consulting firm

Katalyse with their own visions and strategies (June 2017)

Workshops on the results attended by industry stakeholders (July 5, 2017)

a Strategy committee meeting following the workshop to set the program’s

priorities for 2018-2019

a day-long meeting at ceReQ, a center for research on employment and

qualifications (September 2017)

consulting firm Katalyse investigated the economic and industrial challenges facing

the industry to paint a picture of how the industry could change between now and

2024. Interviews were conducted with 50 business decision makers (plant directors,

HR managers, production managers, etc.). Katalyse’s main missions were to:

Get a picture of the current situation of businesses in these industries

and the ecosystem’s strategies

Identify their needs in terms of recruitment and the associated competencies

create a directory of the training programs available in the region and elsewhere

Make recommendations

The findings and recommendations were presented at the workshop on July 5,

2017 for discussion by the industry stakeholders in attendance.

an attentive audience at the workshop held on July 5, 2017

irt nanotech Master’s program: “Management of technological and

innovative projects” module offered by grenoble ecole de Management

and grenoble institute of technology’s phelma engineering school

“Giving microtech product experts the know-how they need to manage

technological and innovative projects”

Microtechnology is found in virtually all of the products we use in our everyday

lives. and these products are expected to get even smaller, thanks to advances

in micro and nanotechnology. IRT Nanotech’s Master’s in Micro and Nanotechnology

for Integrated Systems offered as a continuing and executive education program

at Grenoble Institute of Technology’s Phelma engineering school, ePFl in lausanne,

and Politecnico in Turin, aims to give engineers a broad micro and nanotech culture.

each year, a cohort of 60 students from the three partner schools will be admitted;

students from other european universities are also invited to apply.

The program’s “Management of Technological and Innovative Projects” module

developed in 2016 by Grenoble ecole de Management and Grenoble Institute

of Technology’s Phelma engineering school in cooperation with businesses

and industry professionals and tested for the first time in 2017 teaches

the fundamentals of managing technical and innovative projects.

The purpose of the module is to give engineers (specializing in and who will likely

enter careers in the micro and nanoelectronics industries) the knowledge and skills

they need to manage R&d and high-tech innovation marketing projects. This dual

background in technology and business/marketing meets specific needs identified

Students in the international Nanotech Master’s program at Grenoble Institute of Technology’s Phelma engineering school

in the recruitment and competencies

survey of companies in the micro and

nanotechnology industries. employees

with skills in both areas will help

businesses to transform more effectively

the results of their R&d projects into

marketable innovative projects and help

get research from the lab to industry.

compared to traditional development

projects, this module approaches

development from a broader

perspective, widening the scope

to cover competitors and customers,

and factors the impact on final product

cost into R&d planning decisions.

These are just two ways in which

students must integrate a more

business-oriented point of view into

their project management practices,

analyses, and deliverables. Three

speakers with high-level positions at IRT

Nanoelec partner companies (experts

in BtoB marketing, development

project management, and strategic

and innovation marketing at Schneider

electric and STMicroelectronics) provide

both theoretical content and practical

support for group work to ensure

that students are learning the tools

of the trade and using them on actual

projects.


70 71


2017 hIghLIghTs1. cyBerWeeK: an introDuctory

courSe in cyBerSecurity

« Un cycle intensif de sensibilisation

à la cybersécurité pour

des étudiants-ingénieurs »

dans le cadre du renforcement

des compétences et de la

professionnalisation des métiers liés

à la sureté et sécurité, un des point-

clés pointé dans l’étude emplois

compétences de 2017, l’école

d’ingénieurs Grenoble INP-esisar a mis

en place pour l’ensemble des étudiants

en 1ère année de cycle ingénieur,

un cycle intensif d’une semaine

d’introduction à la cybersécurité.

la « cyberweek » a été construite sur

la base du référentiel aNSSI pour

permettre aux étudiants d’avoir leur

diplôme labellisé cyberedu.

les 82 étudiants qui ont ainsi participé

à cette semaine de sensibilisation,

ont pu assister à plusieurs cycles de

conférences, d’ateliers et de Moocs

sur des thématiques aussi bien

liées aux aspects technologiques

(sécurité des systèmes) qu’aux aspects

comportementaux et sociétaux

(« l’importance des comportements

humains ») ainsi que règlementaires

(droit et règlementation liées à la

sécurité). la cyberweek était également

ouverte aux entreprises partenaires de

la chaire industrielle TRUST (Ingénico,

GrdF, Innovista Sensor). Pour les années

à venir, cette semaine sera élargie à

d’autres entreprises, en particulier celles

partenaires de l’IRT Nanoelec.

2. Digital MarKeting factory

The purpose of the digital Marketing Factory program is to train leaders capable

of creating new businesses based on digital and connected technologies. The

goal is to understand and develop connected environments—the digital home,

digital retail, digital gaming, the connected person, the digital warehouse,

etc.—faster. The program opened in 2017 with a cohort of eighteen students

(engineers, designers, and managers) who complete 150 hours of classes and six

business-creation projects.

The program is built on five modules (see figure below) designed to give

students a set of skills that are crucial to business creation. The modules deliver

methods and business cases tailored to digital and connected solutions and

the use of data to create value. approaches to innovation and entrepreneurship

used by the GaFas and NaTUs (Netflix, airbnb, Tesla and Uber) are also covered.

The program give students the skills they need to respond to the industrial

challenges of the micro and nanotechnology industries right up to smart

solutions—from enhanced creativity and faster, more responsive development

to trial-and-error experimentation, working in “maker mode”, and high-growth

business development.

contributions to the program by IRT Nanoelec partners—identifying,

understanding, using, and experimenting with emerging digital solutions—based

on their own development experience and knowledge will help learners acquire

a “tech culture” and encourage them to look at their companies and markets

in new ways. Finally, students choose the module for the following five reasons:

to develop an “emerging technology” culture; to work with other people with

diverse profiles in hybrid mode; to work as a team within a broad innovation

ecosystem; to help discover tomorrow’s occupations and behaviors; and work in

start-up and “data value” modes.

3. 2017 eDucation & training prograM Key figureS

EDUCATION & TRAININg PROgRAM

J.B Quelène “contributions à l’optimisation d’une interconnexion optique sur

silicium constituée d’anneaux résonants et multiplexée en longueur d’onde”

– thèse de Doctorat de la communauté université grenoble – alpes, spécialité

nanoélectronique et nanotechnologies, soutenue le 10 juillet 2017

J.B Quelène, J.F carpentier, Y. le Guennec, P. le Maytre “optimization of Power

coupling coefficient of a carrier depletion Silicon Ring Modulator for WdM optical

Transmissions” optical Interconnects conference (Ieee- oI), June 5-7, 2017 Santa Fe (USa).

Key puBlicationS IN 2017


73


irt nanoelectechnological platforMS

Si proceSSing platforM

(200 anD 300MM)

IRT Nanoelec invests in new-generation

equipment for 200mm & 300mm

Si wafers processing. The equipment

are used for IRT Nanoelec’s 3d

integration, silicon photonics and

PoWeRGaN programs, and rounds

out our R&d partners’ (such as cea-

leti and STMicroelectronics) 200mm

and 300mm standard integration

equipment. The new equipment is

similar to industrial-grade equipment,

which enables the rapid transfer of

new technologies and short-loop

proof-of-concept testing. Short-loop

testing capabilities make it possible

to transfer wafers to and from IRT’s

technology platform to R&d and / or

manufacturing partners’ facilities so

that each step in the fabrication process

can be completed on the most suitable

equipment.

New equipment purchased in 2017:

cVd Plug filling tool: W filling

aMaT Tool

Photonic characterization tool

(prober from Keysight Technologies

FIB tool from FeI

Wafer Prober for Power GaN devices

from accretech

X-Ray high energy tool

MIMo tool (Multiple-Input

and output tool from Keysight

Technologies.

characteriZation on large Scale inStruMent platforM

To carry out its characterization on large Scale Instrument Program, IRT

Nanoelec benefits from two large facilities available in eSRF and Ill both

partners of IRT Nanoelec. The eSRF is an international research institute for

cutting-edge science with photons. as the world’s most productive light source,

the eSRF operates 40 state-of-the-art X-ray beamlines for almost 7,000 users

from academia and industry per year.

The Institute laue-langevin is an international research center at the leading

edge of neutron science and technology. as the world’s leader center for neutron

science, the Ill provides scientists with a very high flux of neutrons feeding

some 40 state-of-the-art instruments, which are constantly being developed

and upgraded. The Grenoble large-scale instruments potentially offer unrivalled

performance to achieve advanced

micro-Nanoelectronics

characterization.

IRT Nanoelec also benefits

of Nano characterization Platform.

It concerns analysis by X-ray and

ion beams, surface analysis, electron

microscopy and near-field optical

characterization and analysis of

mechanical properties and sample

preparation, a key step for nanoscale

experiments.

The equipment purchased

by IRT Nanoelec is selected to meet

the specific needs of its R&d programs,

as well as the needs of industrial

R&d partners.

BM05 diffractometer

connected transportation

outdoor Platform

d50 neutron-based measurement capabilities

connecteD oBJectS platforM

IRT Nanoelec developed an attractive lineup of services for

product and service designers and developers.

a lab for interconnected technologies development and testing.

a lab where experiments can be carried out in conditions replicating

actual use environments in fields like home healthcare, home automation,

and connected transportation. The lab is flexible, modular, and upgradeable

to adapt to a wide range of innovation-development needs.

72


75


ciMe nanotech

cIMe Nanotech (the Inter-University center for Microelectronics and

Nanotechnology) is europe’s largest Nanoelectronics training center. New cleanroom

training modules and cad tools have been implemented for the formal verification

of integrated circuits and the design of standard cells, for example. Second-year

Grenoble Institute of Technology - Phelma engineering students can now learn

hands-on about formal verification methods using atrenta’s SpyGlass-lint tool.

The advanced formal verification lab course uses oneSpin 360 and resulted

in a joint project with oneSpin following the evaluation of the software.

800 students in irt nanoelec-backed courses each year

eSynov

The esynov platform, which opened in 2014, delivers testing know-how and

resources for the analysis and characterization of embedded and RF electronic

systems. The platform features demonstrators representing communicating systems,

cyberphysical systems, telecommunications systems, radio-software, hardware

and software security, and sensor networks. Students use the platform for innovation

projects focusing on communicating objects. The esynov platform was expanded

in 2016 with a cybersecurity unit with cyberattack simulation capabilities.


irt nanoelectraining platforM

faBMStic

FabMSTIc is a fast-prototyping workshop that is designed to facilitate creativity and

interdisciplinary work by providing access to digital prototyping equipment. New

training modules on smart homes, connected objects, and robotics have been set

up. For example, eNSIMaG engineering students received training as part of the

Smartcampus project, which focuses on how students interact with their campuses.


pleXuS

course design began on the Plexus learning suite, which focuses on the key

managerial competencies (innovation marketing and management) associated with

the market applications for nanoelectronics, and the associated learning platform

was rolled out. The first Plexus course modules are expected to be offered in 2017.

a mock-up of the Plexus suite was presented to partners on october 19, 2016.

The partners provided valuable feedback that will be used to improve course content

and link the courses to collaborative R&d projects conducted with IRT Nanoelec.

The Plexus platform is financed by Grenoble ecole de Management and its corporate

partners.

preDiS-Mhi SMart hoMe anD Monitoring platforM

Predis-MHI is used for both research and teaching. The facility brings the issues

inherent to managing energy in smart buildings to life and shows how smart homes

and smart grids interact. New training modules on smart buildings, building energy

management, and energy and the home have been developed. as an example, an

engineering project on “the connected hive” was developed for ense3 engineering

students so that they could observe swarm health in real time.


http://www.nanoelec-formations.fr/les-ressources-entreprises

74

executive Director

Michel Wolny

editor-in-chief

didier louis

Design

laure diasparra

english translation

SFM Traduction

This work was funded thanks

to the French national program

"programme d’Investissements d’avenir",

IRT Nanoelec’ aNR-10-aIRT-05.

photo credits

© P. Jayet; © P. Ginter; © V. Guilly;

© P. avavian; © cea; © eSRF;

Fotolia: © Rido; © S. Nivens.

Thank you to all program directors, staff,

and partners for their contributions

to this report.

irt nanoelec

cea Grenoble, 17 rue des Martyrs, 38054 GReNoBle cedex 9, France

State-controlled entity of an industrial or commercial nature (ePIc) established in France

and registered with the Paris Business Registry under the number B 775 685 019

www.irtnanoelec.fr

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