I/O Cell LibraryDevelopment

Agenda

1. What are IO cells and why they are needed?2. Comparison with standard cells3. Basic components of an IO cell4. Types of IO cells5. Input buffer6. Output buffer7. Pull up and pull down circuits8. Bidirectional buffer9. Design considerations for IO buffers.10.References

What are IO cells and why they are needed?

An Integrated Chip needs to interact with external devicesLogic levels differ from device to deviceSame logic levels should be maintained for external interactionExternal logic levels are called IO level signalsLogic levels internal to the chip are called CORE level signalsIO buffers convert IO level to CORE level and vice versaIO buffers do not implement any logic (like NAND NOR etc) Operation of IO buffers is controlled by CONTROL signals

Comparison with standard cells

Standard cells perform logic functionality where as IO cells do not

Physical size of IO cells will be much more than that of standard cells

IO cells are associated with ESD structure where as standard cells do not

IO cells will have both CORE and IO level supplies where as standard cells

will have only CORE level supply

Number of standard cells may vary anywhere between 300 to 800 where as number of IO cells is limited by no of external pins

Basic components of an IO cell

An IO cell consists ofA bonding pad – An area to which the bond wire is soldered, the wire goes to a chip pin ESD Protection circuitry Driving and internal logic circuitryPAD pitch is as shown below

CORE

Driving and logic cktBond pad

ESDPAD pitch

Types of IO cells

IO buffers are classified as

Input buffer- Converts IO level signal to CORE level

Output buffer- Converts CORE level signal to IO level

Pull up/down circuit- Forces PAD to logic zero or one

Bidirectional buffer- Combination of Input and output buffer and

Optionally Pull-up/down circuit can be combined with any of the above mentioned buffers

Another type of classification based on PAD architecture/shape would be- Short Fat (SF), Tall Skinny (TS) Ultra Short Fat (USF)

Input stage

HysterisisControl

Level Shifter

OutputStage

Pull-upOr

Pull-down

BondPad

ESDCircuit

ControlSignal

ToCore(L)

External to chip(H)

Input buffer

Block Diagram

Input buffer

Converts IO level signal to CORE level signalBasic blocks are Input stage, ESD circuit, Hysterisis control, level shifterand output stagePull-up or Pull-down circuit is optionalInput stage improves the input slew and generally, consists of inverters ESD circuit is for protectionHysterisis control is for noise immunity and generally, consists of 2 Inverters connected back to backLevel shifter shifts IO level voltages to CORE level generally, consists of InvertersOutput stage also consists of series of inverters to improve the drive

Input buffer

What is ESD?ESD is instantaneous discharge of huge amount of Static charges. Q=CV, generally Capacitor value will be very small resulting into huge Potential build-up which may damage the transistorESD can happen in three ways in nature based on that three ESD models Exist viz Human Body Model (HBM), Machine Model (MM) and Charge Device Model (CDM)Each Model is characterized by its own Peak voltage and currentsWhen one touches the pins of a chip HBM effect is consideredWhen one touches the pins of a chip using machine MM effect is consideredCharges accumulated during fabrication might discharge through a pin which touches the ground first-MM is considered

Hysterisis= VIH-VIL

output (volts)

Input buffer

What is HYSTERISIS?Referring to figure, a minimum input voltage is required for output to start rising. This is VIH and generally measured when output reaches 50% of supply voltage Maximum voltage required for output to start falling is VIL and generally measured when output reaches 50% of supply voltageIdeally VIH=Supply and VIL=0

Input (volts)VIHVIL

Voltage

Time

Input buffer

How HYSTERISIS is related to Noise?Input for an Input buffer is an external signal and a noise can always superimpose this input and might change the logic levels resulting into glitchBut if HYSTERISIS (VIH-VIL) is greater than noise, glitch can be avoided

VIH Level

VIL Level

VIH Level

VIL Level

Input

Output

Time

Voltage

Input

Output

Input buffer

What is Level shifter?Level shifter converts CORE level signal to IO level and vice-versaFor input buffer conversion from IO to core level is requiredA simple level shifter (IO to CORE) is shown below

VDD VDD

VSS VSS

IO Level

InputCore level output

VDDS – IO Level

VDD – CORE Level

Output buffer

Outputstage

PredriverStage

LevelShifters

Pull-upOr

Pull-down

BondPad

ESDCircuit

ControlSignal

From Core(L)

To other devices (H)

Block Diagram

Output enable

Output buffer

Converts CORE level signal to IO level

Basic blocks are level shifters, pre-drivers, output stage and ESD circuit

Level shifters convert CORE level to IO level where as pre-drivers and output stages are needed to control Drive current and other parameters

Operation of output buffer is controlled by output enable signal

No hysteresis circuit is needed as signal is coming from CORE

Output current and load will be huge compared to input buffers

Output buffer/Level shifter

VSS

VDDS

AA

VDDS

VSS

FIG-1 FIG2-2

Note that a simple inverter in FIG-1 can not be used for converting CORE level signal to IO level

This is because A is VDD level and if VDDS-VDD>=VTH, PMOS may not be off completely

In Fig-2 always a VDDS level is used to put-off the PMOS.

AHVAHVB

Output buffer/Switching NoiseCaused by voltage build up across the unavoidable parasitic inductances that connect IC die to external pins

When current changes suddenly, unwanted voltage L (di/dt) builds up across the inductor.

Major problem in output buffers as currents are highEffect is more during transition when both N and P transistors are ONResults in “Ground bounce” and “Power dip”

VDDS

Parasitic L

L

C

VSS

Vin

Power dip

Ground bounce

VDDS

I

Output buffer/Switching NoiseSolution?As driving current is fixed for an o/p buffer, distribute the current through

transistors Switch on the transistors at different intervalsThis gives the same driving current as a sum of smaller currents,

I=i1 + i2 +…..Disadvantage is that, above circuit requires extra switching control

mechanism

P2

N2

VSS

VDDD

I

VDDD

VSS

N1

P1

Output buffer/Switching Noise

Control Mechanism:When output current is raising, first P1 should be switched low then p2There is definite delay between p1 switching low and p2 switching low

which limits the max frequency of the cellMore delay results in controlled current and less switching noise but

reduces the frequencySame conditions apply for N1 and N2 when output current is decreasingSignals N1, N2 ,P1 and P2 are referred to as Pre-driver signals

Output buffer/Pre-Drivers

VSS

VDDD

I C

C

I

P2

VSS

VDDD

I C

C

I

P1

More Widths

Less Widths

Output buffer/Pre-Drivers

I I

t t

P1

P2N1

N2