Invited Tutorial: Analog & Mixed Invited Tutorial: Analog & Mixed Signal Verification Signal Verification

Kevin D Jones

kdj@acm.org

An ApologyAn Apology

I owe you (collectively) an apology!

Paper accompanying this talk is not in proceedings

Kevin D. Jones

Rambus Inc.

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OverviewOverview

• Audience Calibration

• Digital and Analog

• The Analog Design (& Verification) Process

• Mixed mode Design (& Verification) Process

• Formal Verification of A(MS) Systems

• An Analog Example

• The State of the Art

• A Mixed Mode Example

• Open Problems - A Challenge

• Summary and Conclusions

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Audience CalibrationAudience Calibration

• Think about what you see in the following picture

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If you saw this:

Digital world view

- An approximation of a 0 to 1 transition

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If you saw this:

Analog world view

- An approximation of a linear transfer function

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If you saw this:

OUT = tanh(IN)

Theory world view

- A representation of the hyperbolic tangent function

High class analog world view

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Digital and AnalogDigital and Analog

• Different worlds• Think differently

• Different mindset, tools, approaches• Occasionally forced to coexist in mixed

signal designs• My assumptions for this audience:

• People understand digital design and verification

• Analog is the novel part• Main focus on the “front end”

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Digital CircuitsDigital Circuits

Verify this two-input AND gate

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Digital AbstractionDigital Abstraction

• States are discrete and countable

• Must verify the properties at all states

00

0

1

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Digital VerificationDigital Verification• Practice today: (Exhaustive) Simulation

• Directed pseudo-random simulation• Coverage based

• Formal methods• BDD based exhaustive state analysis• Symbolic simulation

• Tools: Specman, SystemVerilog, Equivalence Checkers, Model Checkers, Theorem Provers, …

• Quite tractable for Formal Methods and lots of research has been done

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Analog CircuitsAnalog Circuits

Verify this op-amp

B A

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Aside: AMS Verification is becoming Aside: AMS Verification is becoming a Significant Problema Significant Problem

• More and more systems have analog components• In recent DAC Keynote,

Justin Ratner pointed out the world is fundamentally analog

• Fast becoming a leading cause of SoC failure

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Analog Design (& Verification) Analog Design (& Verification) ProcessProcess

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Analog DesignAnalog Design

• Fundamentally schematic based• Draw the circuit• Very little abstraction• Not too many equations in

practice• Theory and equations in

school• Simulation in practice

• Draw it, Spice it, Repeat

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Analog Design ProcessAnalog Design Process

• Identify circuit class• Pick a topology• Initial sizing• Simulation• Observe results• Repeat until acceptable• “Verify”

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TopologyTopology

• For the desired class of circuit• current mirror, amplifier,

oscillator, PLL, ...

• Go to the text book and pick the topology that you believe has the best possibility of meeting the critical specs

• Topology means arrangement of fundamental components• transistors, capacitors, resistors

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SizingSizing• The fundamental parameters for

transistors are Width and Length• Physical dimensions effecting

speed (delay), strength, power and load of the circuits

• Initial sizing involves an “educated guess” as to the lengths and widths that will deliver the desired critical specification elements

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SimulationSimulation• Unlike the digital

world, simulation is a fundamental part of the design process• many parameters are

unknown until after simulation

• SPICE• DC-analysis• AC-analysis• Transient

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Design LoopDesign Loop

• Simulate• Eyeball (or measure)

result• Tweak parameters• Repeat until results

are acceptable for critical parameters• measure remaining

parameters

• Write spec

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Aside: Fancier ToolsAside: Fancier Tools

• Cadence Neocircuit• Automates the

sizing loop• Reduces the

human effort• Very expensive in

terms of machine effort

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End of Design LoopEnd of Design Loop

• A completed schematic

• Essential parameters are shown to be in spec (for process parameters used for simulation)

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Verification of Analog CircuitsVerification of Analog Circuits• Transistor level models• Circuit simulator (Spice)

• DC simulation • AC simulation • Parameter sweeping• Statistical variation (Monte Carlo)

• Tools: SPICE (HSPICE, PSPICE, Spectre, eldo, …)• Transient (time based) simulation is very

expensive• Simulation inputs based on designers’

understanding/experience/intuition• i.e. verification is the same as design simulation

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VerificationVerification

• No real notion of verification as a separate process using different tools and approaches

• Design is exercised not verified• Everything is based on simulation• Analog Verification today is roughly

equivalent to Digital Verification in 1990

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Statistical VerificationStatistical Verification

• Monte Carlo simulation• simulators support statistical variation of

certain input parameters

• Hits some variant spaces• classical “corners”, random variation

• Very expensive• Each simulation may take a long time• Overall result is as strong as the number of

simulations

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Mixed ModeMixed Mode

• Real systems are always “Mixed Mode” or “Mixed Signal”• Some digital

components• Some analog

components• Communicating across

boundary

• One tool • AMS Simulator

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Verification (should) != SimulationVerification (should) != Simulation

• 25+ Years of research in verification of digital systems has shown that simulation is not a sufficient tool for verification

• For analog systems, this is even more true since (transient/time based) simulation is very expensive

• Look for an abstraction that allows analysis

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Linear AbstractionLinear Abstraction

• If - it’s an op-amp with gain ||

• Choose an Operating Point

• Apply small-signal perturbations to the OP (A, B)

• Derive the relationY = ·A + ·B

• “Linearizing the system at the OP”

Operating Point (OP)

AB

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AC Analysis is a Formal Method for AnalogAC Analysis is a Formal Method for Analog

• AC analysis in SPICE provides the transfer function (TF)

• TF: a complete description of the linear system in frequency domain

• No further need to simulate circuits in transient simulation as long as the input signals remain small

• The circuit is formally verified

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Non-linear DomainsNon-linear Domains

• The “formal” techniques for analog circuits work very well in linear domains

• Many (most) circuits are not linear in the voltage or current domains • PLLs are obviously very non-linear in V

• All the simulator AC analysis tools work in V or I

• This seems to imply they are not useful for most circuits!

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Variable Domain TransformationVariable Domain Transformation

• Most circuits are not linear in voltage or current

•but are linear in some domain: •phase, frequency, delay, duty-cycle, …

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Domain TranslatorsDomain Translators• V ≈ Phase Detector and

V ≈ Phase Mixer• Must propagate perturbations correctly

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Domain Transformation gives “FV”Domain Transformation gives “FV”

• Use domain translators to map the linear domain to V or I• Verilog-A is a good vehicle for developing

translators

• Perform analysis in this domain using AC analysis tools

• Use inverse translator to map back to original linear domain for results

• All the benefits of linearity together with all the benefits of V/I AC simulation techniques

• A “classic” analog approach to Formal Verification

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Limitation of Linear AnalysisLimitation of Linear Analysis

• Linear methods verify only LOCAL properties

• Most circuits are nonlinear

Don’t forget these!

AB

• Must make sure that the circuit does operate at the assumed OP

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Bugs in Analog/MS SystemsBugs in Analog/MS Systems

• Parametric bugs• E.g. Jitter too high• The usual focus of designers effort

• Requires better models and simulation techniques for improvement

• Functional bugs• E.g. PLL doesn’t lock!• Very difficult to find due to long simulation

times and large spaces

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An Example from the “Real world”An Example from the “Real world”

• The example is extracted from an actual design failure• Some issues were only found in

measurement of fabricated test chips• The design was validated as well as any

analog designs are in practice today

• The scale of the example is reduced to make it approachable from an academic perspective but all of the issues are still present

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An Even Stage Ring OscillatorAn Even Stage Ring Oscillator

• Ring oscillators are a common component used in a variety of analog applications

• The obvious design uses an odd number of inverter stages to produce oscillating “0” and “1” signals at a frequency dependent on the inverter delay

• Even (2 or 4) stage oscillators are used when quadrature clocks are useful

XCell1 XCell2

A2

B2

“bridge”

Figure 1: “XChainOfCells2”

“bridge”

“bridge”

Figure 2: An alternative view

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The Complete DescriptionThe Complete Description• * sring - a ring oscillator with bridges• *-----------------------------------------------------------• * Libraries, parameters and models• *-----------------------------------------------------------• .protect• *.lib

'/user/cad/process/tsmc65/model/spice/g+/v1.0/local/fets.lib' TT

• .lib ./cln90g_lk.l TT • .unprotect• .model pch pmos • .model nch nmos • *-----------------------------------------------------------• * Operating point• *-----------------------------------------------------------• .temp 30• .param supplyVoltage=1.5V • *-----------------------------------------------------------• * Initial conditions and stimuli• *-----------------------------------------------------------• .IC V(A2)='supplyVoltage*1.'• *.IC V(B2)='supplyVoltage/2.'• Vdd vdd gnd supplyVoltage DC • *-----------------------------------------------------------• * Simulation controls• *-----------------------------------------------------------• .tran 25ps 5000ps UIC• .option post • .plot v(A2))

• *-----------------------------------------------------------• * Simulation netlist• *-----------------------------------------------------------• .• .param lp=1.0u ln=1.0u • .param wnbridge= 2u wpbridge=4u • * Circuit ceases to oscillate above this ratio• *.param ratioChainToBridge = 1.972• *• *Circuit ceases to oscillate below this ratio• *.param ratioChainToBridge = 0.31• *• .param wnchain = 'wnbridge*ratioChainToBridge'• .param wpchain = 'wpbridge*ratioChainToBridge'• .global vdd gnd• .subckt INV in out psource nsource• Mpullup out in psource vdd pch l=lp w=wp• Mpulldown out in nsource gnd nch l=ln w=wn• .ends INV• .subckt CELL inp inm outp outm• Xinv1 inp outm vdd gnd INV wp='wpchain' wn='wnchain'• Xinv2 inm outp vdd gnd INV wp='wpchain' wn='wnchain'• Xinv3 outp outm vdd gnd INV wp='wpbridge' wn='wnbridge'• Xinv4 outm outp vdd gnd INV wp='wpbridge' wn='wnbridge'• .ends CELL• .subckt CHAINOFCELLS2 ina inb outa outb • XCell1 ina inb oa1 ob1 CELL • XCell2 oa1 ob1 outa outb CELL • .ends CHAINOFCELLS2 • XChainOfCells2 A2 B2 B2 A2 CHAINOFCELLS2• .end sring

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Challenge for Formal MethodsChallenge for Formal Methods• The “obvious” digital abstraction doesn’t

hold• It has interesting failure modes

• It is very sensitive to the exact sizing of the ring and bridge transistors

• It has sensitivities to initial conditions for some sizes

• The challenge: Show that this circuit oscillates for all initial conditions for some sizing

• Extra credit: Show the sizing ratios regions for the ring and bridge transistors

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GoodGood

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BadBad

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Ugly Ugly

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Some Formal ApproachesSome Formal Approaches

• The ESRO example has been tackled by a number of different groups

• Methods used differ dramatically• Recent publication in FAC 08 and

surrounding conferences• Following section gives an overview of a

variety of approaches to this problem and some other noteworthy approaches on a similar scale

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Stability analysis Stability analysis • UBC

• “Pencil and paper” approach

• Use monotonicity of fundamental components to find DC equilibria, VT derivative to analyse stability

• Unstable => no DC steady state => no lock up

• GLSVLSI 2008

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iSpiceiSpice

• CBL

• Formulate example as an SMT problem using arithmetic intervals as underlying theory

• Proves properties based on DC, Transient and PSS simulations

• Shows regions of stability

• FAC 2008

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Discrete AbstractionDiscrete Abstraction

• University of Frankfurt

• Divide continuous space into discrete regions for model checking

• Analog specification language

• DATE 08

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Petri Net ModelsPetri Net Models

• University of Utah• Translating AMS

circuits into LHPN• Using this model as a

basis for both BDD and SMT model checking

• FAC 08

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Hybrid AutomataHybrid Automata

• Verimag• Using dense time

automata to model behaviors of analog circuits

• Analog assertions and monitors

• FMCAD 04, FAC 08

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Reachability AnalysisReachability Analysis

• CMU• Forward and

backward reachability analysis on over-approximated partitions

• DATE 06

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Bond Graph AbstractionBond Graph Abstraction

• Concordia• Abstract the

properties of analog circuits into a representation based on Bond Graphs

• Constraint solving to reason about safety and reachability properties

• FAC 08

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Example 2: Moving up the AMS food chainExample 2: Moving up the AMS food chain

• Phase Locked Loops are critical components of most high speed PHYs• They are made up of subcomponents

• Phase detector• Charge pump• Linear filter• Voltage Controlled Oscillator • Divider

• There are many possible failure modes• Simulating the locking behavior of a PLL at

the transistor level in the time domain is very expensive

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PLL locking bugsPLL locking bugs

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PLL Locking Bugs (II)PLL Locking Bugs (II)

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PLL Locking Bugs (IV)PLL Locking Bugs (IV)

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PLL Locking Bugs (V)PLL Locking Bugs (V)

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A Verification NightmareA Verification Nightmare• Individual components can be wrong• Individual components can be fine but assumptions

between components can be wrong• Most of these issues are not visible if we assume

“correct initialization” i.e. we start simulation from a locked state, as we do for most parametric simulation

• It takes a very (very, very, …) long time to simulate, using sufficiently accurate models, from any arbitrary initial state to reach lock

• Bugs like these make it through to production

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Open Analog Problems (A Challenge)Open Analog Problems (A Challenge)

• Avoiding transient simulation

• Establishing that operating point assumptions are valid

• Establishing that all initial conditions result in correct behavior

• Dealing with non-linearity

• Good candidates for FM approaches

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Conclusions and Future WorkConclusions and Future Work• Analog and digital are different

• Different mindsets, different tools, different problems

• There are problems in the analog space that are really looking for solutions• Different points of view yield valuable approaches

• The FV community is just beginning to come to grips with this problem =>Lots of interesting opportunities

• We can provide “realistic” examples to interested parties• Some are small, representative and tractable• If any one really wants it, we have a software → digital →

analog → physics problem (ms → ns → ps → fs) in a 20GB SERDES system

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Some Further ReadingSome Further Reading• General Analog Design

• Gray & Meyer: Analysis and Design of Analog integrated Circuits, Wiley.

• B. Razavi: Design of Analog CMOS Integrated Circuits, McGrawHill

• Verification issues for Analog/MS• Thomas Sheffler, Kathryn Mossawir, Kevin Jones: PHY

Verification - What's Missing?, DVCon 2007

• More information on Domain Transformation• Jaeha Kim, Kevin D. Jones, Mark A. Horowitz: Variable

domain transformation for linear PAC analysis of mixed-signal systems. ICCAD 2007: 887-894

• The State of the Art for Formal Verification of Analog Circuits

• Proceedings of FAC 08