Extended Abstracts of the 1994 International Conference on Solid State Devices and Materials, Yokohama, 1994, pp. 406-409

Invited

lntroduction

Research on Silicon-on-insulator (SOl) has beensteadily increasing over the last few years, and theadvantages of fabricating CMOS circuits on SOIsubstrates is being seriously addressed by severaldevelopment labs worldwide. The reader is referred tothe excellent monograph on the subject by J,-P.Collingel and references containedinerein and alsothe proceedings of the IEEE SOI (or SOS/SOI)conferencesz, the ECS SOI conferencesu and WaferBonding Symposia4 as well as the SOI sessions inthis meeting for a more extensive discussion. Therehave been several reports of dramatic performanceimprovemerts resulting from the use of SOIsubstratesr. SOI substrates have establishedthemselves in the field of analog and mixed signalapplications6 as well as certain smart powerapplications/. As SOI establishes itself in thesespecialized markets, its use is being investigated formainstream digital CMOS applications both for logicand memory. The digital lC applications are projectedto drive the SOI wafer market to over Y 20 billion overthe next few years followed by further rapid growth.

Device Considerations

There are basically two structural options available forCMOS device implementation in SOl. ln the firstoption (a) - called fully depleted - the thickness of theSOI layer is less than the depletion width in thechannel region of the device. Such a structure, hasseveral features: a nearly ideal sub threshold inverseslope of -60mV/decade; a reduction of all parasiticcapacitances to the substrate by about ZS% or more;reduced short channel effects due to the film

A-0-4

thickness defined shallow junction depth. Otheradvantages are a potential increase in channelmobility (because of a smaller vertical surface field),and increased transconductance (because of areduction in Cp - the depletion capacitance and alsoincreased mobility). As a result the fully depleted FEThas a higher drive capability. Fully depleted devicesdo not exhibit the so-called "kink" effect. Fullydepleted devices may be operated either in theinversion mode or the accumulation mode withconvenient V1 for CMOS obtainable with a single gatematerialu. The biggest disadvantage of the fullydepleted devices is a stringent requirement on thethickness of the SOI layer and its uniformity. Thethreshold voltage for a given channel doping isextremely sensitive to the SOI film thickness. This isperhaps the biggest drawback of fully depleteddevices, though a constant channel implant dose willreduce this sensitivity. The extremely thin SOI layerswill need more sophisticated processing capability.

Nonlully depleted (sometimes called partiallydepleted) structures resemble more conventionalscaled MOS transistors. they do not exhibit theextreme sensitivity of the threshold voltage to SOIthickness. They are more'bulk-like" in that there is aneutral body. Unlike the bulk case this body isfloating, (though it may be tied through the use of aspecial body contact). The depletion capacitance Cpis reduced, but not as much as in the fully depteted-case. To first approximation, at least structurally, thetechnology is a bulk technology but on an SOIsubstrate. However, the operation of the partiallydepleted SOI MOSFET is some what more subtie9.The parasitic lateral bipolar transistor and its floatingbase i.e., the so-called floating body, play a comptex

SOI Technology for VLSI

Subramanian S. lyerSiBond L.L.C., 1580 Route 52 Hopewell Junction, NY 12533. USA

Silicon-On-lnsulator (SOl) technofogy promises improved performance and functionality inboth digital and analog VLSI technology, in addition to that afforded by direct scaiing.Performance enhancement results from the reduction of parasitic capacitances to th;substrate and in a more subtle way from the presence of the floating body during theswitching transient. In addition to performance improvement, SOI allows for a simpler processflow and perhaps even a smaller die size with concomitant improvements in yields. Thus thecombined advantage of improved performance, lower integrated processing cost, and apotential transparency to bulk device and circuit design, make SOI a potential replacementfor bulk Si substrates in an existing Silicon line. For this to happen however, significantprogress in the development of a SOI materials' infrastructure is necessary. In this talk weexamine the principal device considerations and progress towards the development of amaterials' infrastructure especially for bonded SOl..

406

role leading to an anomalous increase in inverse subthreshold slope at high VOO. The net effect is an

effective increase in drive capability. lt appears thatfor a given process and design technology theseeffects can be well controlledru,. A concern is snap-back or the inability to turn the device off, if the drainvottage is too high. This breakdown of the transistorcan be avoided (as in the bulk case) by ensuring a lowenough operating voltage. Tying the body to a fixedpotential has been suggested, but will reduce the

device packing density (by as much as 30-40%) andmay also detract from the beneficial effects of thefloating body. One possible concern is the possibilityof some as yet unknown circuit sensitivity to thefloating body potential fluctuations. A related effect is

the "kink" in the output characteristics. P-channeltransistors do not show the kink except at very high

voltages. While the appearance of this kink isunacceptable for devices where linearity is a key(analog applications) it is quite tolerable (and evenadvantageous) for digital applications.

Another general point that must be made concernsreliability and operating voltage. lt is clear that effectssuch as snapback and other reliability concerns are

minimized at lower operating voltages. Bulk CMOS is

also being driven to lower operating voltages by both

reliability and market requirements for lower power

operation. The performance improvement provided by

CMOC/SOI can be traded for lower power operation,and this is clearly an additional driving force for SOl.

As a result of the foregoing SOI/CMOS offers someimmediate advantages from a performance

standpoint. lt offers a way of effectively lowering thethreshold - a normally non-scalable property (unless

one lowers operating temperatures). The higher drivecurrent speeds up the switching transient andmanifests itself in improved performance. Additionallyit is possible to lower the operating voltage and

operate at a reasonably high performance level withrespect to bulk. This approach to attain low power

circuits is receiving widespread attention an will be an

effective technology driver. The reduction of parasitics

is also an important factor and alone may be able tocontribute as much as 30% in performanceimprovement. Other advantages of SOI circuits is theirincreased radiation immunity and the possibility ofeasy integration of bipolar circuits for BICMOS

applications. This last application does requireexcellent lifetime in the SOI material. Low junction

leakage (mainly because of reduced junction area) is

another advantage of thin SOI that can be exploited in

high temperature applications.

Besides performance, cost is another driving force forthe implementation of SOl. There have been detailedstudiesl 1 on the process simplification that amigration to SOI will bring aboul. Mainly, these stemfrom the simplification in isolation schemes. Theelimination of the well implantsand the ability to buttcertain devices not only reduce processingcomplexity, but can significantly reduce die size and

an increase in overall yield.

However, the biggest cost benefit derives lromeconomic reasons. The performance improvement in

SOI is available without further scaling. Traditionally,in CMOS technology, performance improvement has

derived from scaling. This is increasingly a more

expensive exercise and over time has necessitatedthe development of larger wafer diameters, morerobust and uniform processes, and new tools. Today itis estimated that a new state of the art facility may

cost upwards of Yl00 billion. The ability to extend the

life of this facility by changing the substrate from bulk

Si to SOI is an attractive proposition. lf the facility

depreciation has already been amortized over the life

cycle of a previous bulk product, only the operatingcosts for the SOI product are relevant. These, as we

have discussed promise to be lower for an SOIproduct, with the possible exception of the SOIsubstrate itself. The point to be made is that notwithstanding the higher price of an SOI substrate,migrating CMOS technology to SOI , especially if one

is able to utilize a partially depleted design, wherebulk designs can be ported to SOI with minimalchanges, will provide a lower overall cost for theproduct. Additionally, SOI may offer the most viablepath today; for the migration to lower power CMOS.Many of these points.llave been exemplified in recent*ork by Shahidi et all2 , where a512K SRAM withabout 1.5X performance improvement over bulk wasachieved using bulk like technology on SOl.Furthermore the relative performance improvementover bulk increased at lower voltages.

There have been a few suggestionq of novel memorystructures utilizing SOI substratesl3. Often, these arequasi three-dimensional structures where the storagenode is fabricated on one level and the addressingdevice is on another level. Once again, iunction areasare minimized so that leakage currents are less. SOI

for memory applications will more likely require thicker

device layers over 1pm. lt is possible that such novel

memory structures may provide our only approachDRAM structures at the l Gbit level. The use of SOI inSRAMs has been quite widespreadl4 especially forradiation hard applications rc

407

Materiaf s Considerations

si technology owes its pre-eminent position entirely tothe ready and cost effective availability of the bulkpolished Si substrate. Similarly, the success of SOItechnofogy is dependent on the availability of a similarquality SOI substrate. For the thickness range beingconsidered for digital CMOS applications, there aretwo main sol materials approaches that merit seriousconsideration: These are SlMOX (separation byimplantation of Oxygen)16 and the bonded waferapproach t I The bonded wafer approach offersalmost unlimited flexibility in that the thickness of thesilicon device layer and the buried oxide (Box) as wellas the electrical characteristics of the SOI layer andthe substrate, can be independently chosen.Throughout, it has been the material of choice andbonded SOI is extensively used in various analog andmixed signal products with great success. The mainreason for this widespread acceptance is the excellentquality of both the superficial silicon and the buriedoxide - unmatchable by any other technique - and itsavailability at reasonable cost. Several surveys,'including one conducted by the Japanese ElectronicIndustry Development Association (JEtDA) 1B haveindicated the preferabilty of the bonded waferapproach to SOI over other approaches by bothmerchant semiconductor houses as well as wafermanufacturers.

While Simox has been used extensively in thedemonstration of many of the advantages of thin filmSOl, the use of Bonded SOI has lagged. The biggestdrawback of the bonded wafer approach has been theperception that it would be impossible to extend intothe thin Si thickness regime of CMOS viz. 100-200nm, with uniformities better than a few percent.However, over the last two years, importantdevelopments in bonded wafer fabrication have madethe avaifability of thin and uniform bonded SOI atcompetitiye^ price a reafity. One approach is theAcuthinrMl e method. Here a conventional bonded pairthat has been thinned by grinding and polishing tobelow about 10 pm with ttv's of a few pm is accuratelymapped and locally polished using a plasma process.The wafer is scanned under the plasma head, and thedwell time dictated by the initial thickness and thetarget thickness. This method, combined with anefficient metrology system allows for the production ofhigh quality thin SOl. Such wafers are availablecommercially.

The bonded wafer approach to SOI using an etch stopcalled Bond and Etchbacl< SOt (BESOI) wasproposed by Lasky et al 20. In their approach, anundoped epitaxial film is grown on top of a highly p++

doped substrate. This layer is joined to an oxidizedhandle wafer (or oxidized and joined to a handlewafer). The p++ layer is then selectively etched off tostop at the i-layer. This original'approach worked inprinciple but had some practical limitations. since thenthere have been several new enabling technologiessuch as advanced epitaxial technology andsophisticated double etchstop technology that allowfor a far more robust and uniior* proce-ss21. Thereader is referred to an excellent review by Maszarafor a description22. BESOI wafers are also availablecommercially.

Today, surface morphology of all types of SOI wafersare inferior to that available in bulk Si wafers, thoughat long wavelengths, SOI surfaces are comparable. Atshorter wavelengths, the BESOI roughness is verysensitive to the final etch or polish step employed, andcan be made comparable to bulk Si after sacrificialoxidation. The epitaxial BESOI film afso important toobtain good gate dielectric quality and reliability andits good crystallinity and purity is evident from lifetimemeasurements. Effective lifetimes as high as 370psec, comparable to bulk have been obtained onBESOI. This is indicative of excellent quality of boththe SOI film and the oxide interfaces. Film uniformity -a key concern for bonded wafers - of better than +/-35% at thicknesses as low as 100nm are routinef yobtainable by BESOI on all diameter wafers with anedge exclusion of <6mm. The ability to "dial-in" SOIand BOX thickness has also been amplydemonstrated in BESOI.

Sheet resistance and spreading resistancemeasurements inlicate that the carrier concentrationis well below 1015 cm-3. Carbon and oxygenconcentrations are also below detectability limits.Transmission Electron Micrographs fail to showdislocations or any delineation of the bondedinterface. No Si inclusions - a common occurrence inSimox are observed. Independent measurements ofthe buried oxide integrity and charge show it to besimilar to thermally grown oxides. The BESOI filmssynthesized by the methods detailed above havebeen used in the fabrication of CMOS devices andcircuits. The details of^the process and the results aredescribed elsewherezi1. Delays as low as 20 psechave been reported for channel lengths of about 0.1pm at 1.7V. Sub 50 psec delays at 1 V bias for bulkand BESOI devices are also very impressive. Theseresults clearly demonstrate the applicability of BESOIto high performance and low power CMOStechnology, and coupled with the potential to lowercosts of CMOS by SOI fabrication processes and theinherent quality of an epi-based SOI materialstechnology promise widespread use of BESOI for

408

digital applications in the sub100nm to 2.5pm range.The ability to reduce the operating power supply andyet exhibit very high performance bodes well for theuse of SOI for low power and portable applications.

Gonclusions

In summary, a convincing argument for the applicationof SOI to CMOS can be made from both cost,performance, and low power considerations as well asadditional functionality. We expect the insertion of SOIat the 0,5 to 0.25pm lithography generation usingpartially depleted designs. The ready availability ofcost effective substrates on a manufacturing scale is

Relerences

I .1.-p. Collinge "Si licon-on -insu lator Tech nology :

Materials to VLSl", Kluwer Academic Publishers,Norwell, MA (1991)2see for example, Proc. of the IEEE SOIconferences Pub IEEE (NY)3see for example, the Proc. of the Sixth Intl.

Symp. on Silicon-on-lnsulator Technology andDevices, ECS Proc. 94-11 ed. S. CristofoveneanuPub. Electrochemical Soc., Pennington NJ (1994).4see for example, Proc. of the second Intl. Symp.on Semiconductor Wafer Bonding, ScienceTechnology and Applications, ECS Proc. 93-29ed. M.A. Schmidt et al Pub. Elecrrochemical Soc.Pennington NJ (1993).5Y. Omura and K. lzumi, Proc. 4th Intl. Symp. onSOI devices and Technol. p 509 Pub.Electrochemical Soc. ( 1 990)G.G. Shahidi et al Extended Abstracts of SSDM

p 1e3 (1eez)W.M. Huang et al, Tech. Digest of IEDM p +49

Pub. IEEE (1e93).6 K. Yallup, ECS Proc. 92-1 p 43 (1992)

C.J. McLachlan et al, ECSProc. 93-29 p 41

f ee3)/S. Merchant et al, Proc. IEEE SOI Conference, p150 (1ee1).

Y. Yasuhara et al Tech. Digest of IEDM, p 141

Pub. IEEE Press (1991)8p.X. Woerlee et al, Tech. Dig. of IEDM p 583(1990) Pub. IEEE New York.9For a good review see J.B. McKitterick, ECS

PIoc. 94-11 p 278 (1994)10C.e. Shahidi et al - Tech. Digest of IEDM p 813(19e3).

!1f.O.Stanley, ECS Proc.94-11 p441 (1994)12e .e . Shahidi et al, Tech. Dig. of the IEDM, p813 Pub. IEEE (1ges)

crucial before semiconductor manufacturers cancommit to SOI based product programs.Simox andBonded SOI are the main options. The bonded waferapproach, especially BESOI, offers the potential ofcost effective, high quality epitaxial film SOIsubstrates on a manufacturable scale. lt is the onlycunent SOI technology that uses readily availablecom mercial se micondu ctor processi ng equ ipmen t,

and shows reduced per cmz cost as the waferdiameter is scaled up. The entry of mainstream siliconsuppliers into the SOI business and a sustained pushby chip makers into manufacturing, promise to makeSOI a reality.

13t. Eimori et al, Tech. Dig. of the IEDM p 45Pub. IEEE (1993)14f.W. Houston et al, IEEE SOI/SOS ConferenceProc. p 137 , IEEE Press (1993)1Sru. Haddad and L.K. Wang, ECS Proc. 92-13 p

2e (1eez)16K. lzumi et al, Electron. Lett. 14 p 593 (1978)17.1.g. Lasky et al Tech. Dig. of IEDM p684, Pub.

IEEE Press (1985)M. Shimbo et al, J. Appl. Phys. 60 2987 (1987)T. Abe et al ECS Proc. 92-7 p 200 (1992)

18 SEMI-JEIDA report on 200mm wafers,published by SEMI (1993)l9Acuthin is the trademark of Hughes DanburyOptical Systems, See also: G.J. Gardopee et al,

Microelectronic Engg. 22 (14) pp-347-50 (1993).20,.1.g. Lasky et al IEDM Tech. Digest p 684(1e85)21S.S. lyer et al, Semiconductor Si/1994 ECS

Proc.94-10 ed. H. Huff et al p391 (1994)22W .p . Maszara,Microetectronic Engineertng, 22(1-4) p 2e9-306 (1e93)23o.c. Shahidi et al in vLSl technology Symp.Kyoto Japan (1993), P 27

409