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Introduction to Sequential Logic Design Finite State-Machine Analysis

Introduction to Sequential Logic Design Finite State-Machine Analysis

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3 Clocked Synchronous State-Machine State machine: generic name for sequential circuits; (Finite State Machine: FSM) Clocked: the storage elements (FFs) use a clock input; Synchronous: all of the FFs in a circuit use the same clock signal. Such a FSM changes states only when a triggering edge (rising or falling) on the clock signal.

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Page 1: Introduction to Sequential Logic Design Finite State-Machine Analysis

Introduction to Sequential Logic Design

Finite State-Machine Analysis

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Prev…

Flip FlopsD FFsT FFsJ-K FFs

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Clocked Synchronous State-Machine

State machine: generic name for sequential circuits; (Finite State Machine: FSM)

Clocked: the storage elements (FFs) use a clock input;

Synchronous: all of the FFs in a circuit use the same clock signal.

Such a FSM changes states only when a triggering edge (rising or falling) on the clock signal.

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State Machine Structure

State memory: n FFs to store current states. All FFs are connected to a common clock signal.

Next-state logic: determine the next state when state changes occur;

Output logic: determines the output as a function of current state and input

Mealy machine vs. Moore machine

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Mealy Machine

Next state= F (current state, input)Output= G (current state, input)

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Moore Machine

Next state= F (current state, input)Output= G (current state)

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Characteristic Equations

A Characteristic equation specifies the FF’s (or latch’s) next state as a function of its current state and inputs.

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Analysis of FSM with D FFs

Next state= F (current state, input)Output= G (current state, input)

Step 1: Determine the next-state and output functions F, G Step 2: Use F, G to construct a state/output table that completely specifies the next state and output of the circuit for every possible combination of current state and input.

Step 3: (optional) Draw a state diagram which is a graphical form of the state/output table.

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Example: clocked synchronous FSM using positive-edge triggered D FFs

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Transition, state, state/output tables

Excitation equationsTransition Equations (next-state equations)Output equations

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State Diagram

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Summary: how to analyze a clocked synchronous state machine?

1) Determine the excitation equations for the FF control inputs;2) Substitute the excitation equations into the FF characteristic

equations to obtain transition equations;3) Use the transition equations to construct a transition table;4) Determine the output equations;5) Add output values to the transition table for each state (Moore)

or state/input combination (Mealy) to create a transition/output table;

6) Name the states and substitute state names for state-variable combinations in the transition/output table to obtain state/output table;

7) Draw a sate diagram corresponding to the state/output table.

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Excitation EqTran. EqTran.TableOutput EqTran/out TableState/out TableState Dagram

Another Example

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