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Introduction to Mixed-Signal
Integrated Circuit Design
Comparator
Yongfu Li & Yong Lian
Dept. of Micro/Nano Electronics
Shanghai Jiao Tong University
Comparator Slide 1 Y. Li & Y. Lian
Course Website
Slide 2 Y. Li & Y. Lian Comparator
https://yongfu-li.github.io/module/mr317.html
Course Outline Week Lecture Homework Project Reading (Chpt)
1 Introduction Lab #1 2
2 Sample and Hold HW #1 (5%) Project #1 (15%) 1, 5.1-5.6
3 Comparator Lab #2 *
4 DAC Design HW #2 (5%) Lab #3 3
5 ADC Concept Project #2 (40%) 2, 4
6 Case Study Lab #4 4
7 ADC Testing HW #3 (5%) Presentation 9
8 Exam (25%)
Slide 3 Y. Li & Y. Lian Comparator
Homework + Class discussion: 15% + 5%
Project: 55% (Literature Review + Design Project)
Exam: 25%
*Chpt 2 in âComparator in Nanometer CMOS Technologyâ
Reading Materials
Analog Design for CMOS VLSI
Systems
Professor Franco Maloberti
⢠Chapter 6
Slide 4 Y. Li & Y. Lian Comparator
Additional Reading Materials
Comparators in Nanometer
CMOS Technology
Bernhard Goll &
Horst Zimmermann
⢠Chapter 2
Slide 5 Y. Li & Y. Lian Comparator
Summary
1. Concept
2. Design considerations & Non-idealities
3. Offset compensation Techniques
Slide 6 Y. Li & Y. Lian Comparator
Data converters (ADC & DAC)
Y. Li & Y. Lian Comparator
Continuous-amplitude, continuous-time
Discrete-amplitude, discrete-time ADC
ADC
Slide 7
đđđ = 1⯠đđ´đ ⼠đđ´đ
0⯠đđ´đ < đđ´đ
Classification of Comparators
â˘Digital Comparator
â˘Priority Encoder Digital
â˘Continuous Time (Static)
â˘Clocked Regenerative (Dynamic)
Analog
Slide 8 Y. Li & Y. Lian Comparator
Types
of
inputs
Digital Comparator with Encoder
Slide 9 Y. Li & Y. Lian Comparator
Continuous-time (Static)
OpAmp Comparator Current Switch Comparator
Slide 10 Y. Li & Y. Lian Comparator
Miller OpAmp
Clocked Regenerative (Dynamic)
Y. Li & Y. Lian Comparator Slide 11
⢠Two symmetric sub-circuits
⢠Increase Gain/Speed with Regenerative Feedback (cross-coupling)
⢠Clocks are often added to remove the restriction of regenerative-type structures not recovering when inputs change a little (Clocked regenerative, dynamic comparator)
E
E đđźđ đđźđ
đđ
+ đđ
â
E
E đđźđ đđźđ
đđ
+ đđ
â
đđâ đđ
+
đđđđ´+ đđđđ´
â
OpAmp Comparator Comparator w Regenerative Feedback
Clocked Regenerative (Dynamic)
Slide 12 Y. Li & Y. Lian Comparator
Clocked Regenerative (Dynamic)
Strong-Arm Comparator Lewis Gray Comparator
Slide 13 Y. Li & Y. Lian Comparator
Strong-Arm Comparator
Slide 14 Y. Li & Y. Lian Comparator
Dynamic Comparator Waveform
Slide 15 Y. Li & Y. Lian Comparator
Return to Zero signal We need a
D-FF!!!
Static Latch
Y. Li & Y. Lian Comparator Slide 16
Very fast!
Zero DC current after full regeneration
Ă Q+ and Q- are not well defined in reset mode (ÎŚ = 1)
Ă Large short-circuit current in reset mode
Ă Very noisy
M6M5
M7
Q+
Q-
ÎŚ
Vi+
Vi-
M1 M2
M3 M4
M6M5
M7
ÎŚ
ÎŚ
M8
Vi+
Vi-
M1 M2
M3 M4
Q+
Q-
Semi-Dynamic Latch
Y. Li & Y. Lian Comparator Slide 17
Very fast!
Zero DC current after full regeneration
Ă Q+ and Q- are not well defined in reset mode (ÎŚ = 1)
Ă Still very noisy
ÎŚ
Vi+
Vi-
M7 M8M5 M6
M1
Q+
Q-
M2
M9 M10 ÎŚ
ÎŚÎŚ
M4M3
Dynamic Latch
Y. Li & Y. Lian Comparator Slide 18
Zero DC current in reset
Q+ and Q- are both reset to â0â
Full logic level after regeneration
Ă Slow
Ref: A. Yukawa, âA CMOS 8-Bit High-Speed A/D Converter IC,â JSSC, vol. 20, pp. 775-779, issue 3, 1985.
Ref: T. B. Cho and P. R. Gray, âA 10 b, 20 Msample/s, 35 mW pipeline A/D converter,â JSSC, vol. 30, pp. 166-172, issue 3, 1995.
M4M3
ÎŚ
Vi+
Vi-
M7 M8M5 M6
M1
Q+
Q-
M2
M9 M10 ÎŚ
ÎŚÎŚ
A
B
Q
QB
Clockless Dynamic Latch
Y. Li & Y. Lian Comparator Slide 19
nand gate
Zero DC current in reset
Q+ and Q- are both reset to â0â
Ă Slow
Full logic level after regeneration
Clockless, reduce clock loading
M1 M2
M5
Vi+
M6
Vi-
M4M3
M7
ÎŚ
M8
ÎŚ ÎŚ
RL RL
Q+
Q-
Current-Steering Latch (CML)
Y. Li & Y. Lian Comparator Slide 20
Constant Current (Quiet)
Fast
Ă Not rail-to-rail output swing
Dynamic Comparator + Latches
Y. Li & Y. Lian Comparator Slide 21
⢠A dyanmic comparator can be followed by a latch.
⢠Return to Zero (RZ) signal Non-Return-to-Zero (NRZ)
⢠Latching time ~2-10 nsec with Vin,min ~ 10mV
Design Considerations
Power
Offset
Speed Hysteresis
Y. Li & Y. Lian Comparator Slide 22
Gain/Response time of Comparator
Y. Li & Y. Lian Comparator Slide 23
⢠Voltage gain: the DC differential gain of the comparator.
i.e. OUT > 3V and VAp-VAn ~ 1mV, gain of 3000 is sufficient.
⢠Response time: the time interval between the application
of a step input and the time when the output reaches the
respective logic level.
Noise, Offset and Hystersis
Slide 24 Y. Li & Y. Lian Comparator
Noise, Offset and Hystersis
Noise
- Thermal noise random thermal motion of electrons
- Flicker (1/f) noise
- Kickback noise
- Static noise
Offset
- Static (Circuit Mismatch)
- Dynamic (Dependent of Vin range)
Hysteresis
- Different threshold (High to Low and Low to High)
Slide 25 Y. Li & Y. Lian Comparator
Offset Compensation Techniques
Auto-zero technique
Input Offset Cancellation
Output Offset Cancellation
Auto-zero in multistage comparators
Differential Circuit
Compensation by auxiliary input stages
Slide 26 Y. Li & Y. Lian Comparator
Auto-zero Technique
Y. Li & Y. Lian Comparator Slide 27
Phase 1
đđđ + đđđ
đđđ
đđźđ â đđźđ = đđđ â đđđ + đđđ = âđđđ
Phase 2
Charge Vos
Input Offset Cancellation
Y. Li & Y. Lian Comparator Slide 28
⢠Two-phase operation,
ÎŚ1 (Amplifying ) and ÎŚ2 (offset storage)
⢠Capacitor acts as âAC couplingâ (ÎŚ1) and as an output load
of the gain stage (ÎŚ2)
A
VosÎŚ1
ÎŚ2
ÎŚ2'
Vi Vo
C
Input Offset Cancellation - ÎŚ2
Y. Li & Y. Lian Comparator Slide 29
⢠Gain stage is in unity gain closed-loop configuration, C acts
as an output load of the gain stage.
⢠Gain stage is in open loop configuration
A
Vos
ÎŚ2
ÎŚ2'
Vo
Vc
đđ = âđ´ đđ â đđđ
=đ´
1 + đ´ đđđ
â đđđ
Input Offset Cancellation - ÎŚ1
Y. Li & Y. Lian Comparator Slide 30
⢠Offset cancellation is incomplete if A is finite
Ă Input AC coupling attenuates signal gain
đđ = âđ´ đđđ + đđś â đđđ = âđ´(đđđ â đđđ
1 + đ´)
A
VosÎŚ1
Vi Vo
Vc
A
VosÎŚ1
ÎŚ2
Vi Vo
C ÎŚ1
ÎŚ2'
Output Offset Cancellation
Y. Li & Y. Lian Comparator Slide 31
⢠AC coupling at output with offset stored in C
⢠A must be small and well controlled (independent of Vo)
⢠Does not work for high-gain op-amps
Output Offset Cancellation - ÎŚ2
Y. Li & Y. Lian Comparator Slide 32
⢠Closed-loop stability is not required
⢠Clock feed through and Charge injection of Ό2 gets divided
by A when referred to input
đđ = đ´ âđđđ Vos
ÎŚ2
Vc
ÎŚ2'A
Ref: R. Poujois and J. Borel, âA low drift fully integrated MOSFET operational amplifier,â JSSC, vol. 13, pp. 499-503, issue 4,
1978.
Output Offset Cancellation - ÎŚ1
Y. Li & Y. Lian Comparator Slide 33
⢠Cancellation is complete if A is constant (independent of Vo)
⢠AC coupling at output attenuates signal gain
đđ = đ´ đđđ â đđđ â đđ = đ´đđđ
VosÎŚ1
Vi Vo
Vc ÎŚ1
A
đđ = đ´ âđđđ
Auto-zero in multistage comparators
Y. Li & Y. Lian Comparator Slide 34
⢠Offset of the kth stage is referred to the input attenuated
by the factor A1A2âŚAk-1
⢠Clock feedthrough from S1 and S2 causes the rising of two
equivalent offset voltages, Vos,1 and Vos,2 at the input of A1
and A2
The resulting input offset is:
đ´ = đ´1đ´2âŚđ´đ
đđđ = đđđ ,1 +1
đ´1đđđ ,2
Differential Circuit
Y. Li & Y. Lian Comparator Slide 35
⢠Clock feedthrough due to the Switch S1 and S2 gives a
common mode signal, is cancelled out.
Compensation by auxiliary stages
Y. Li & Y. Lian Comparator Slide 36
⢠Gm1 and Gm2 are the preamp and latch, respectively
⢠A form of output offset cancellation technique
Ref: B. Razavi and B. A. Wooley, âDesign techniques for high-speed, high-resolution comparators,â JSSC, vol. 27, pp. 1916-
1926, issue 12, 1992.
Vos1S1
S4
Vi+
Vo+
Gm2
Vos2
C1
S3
S2
Vi-
C2
S5
S6
RL
RL
Vo-
Gm1