INTRODUCTION TO MENTOR GRAPHICS DESIGN TOOLS

Erdem S. Erdogan

09.13.2006

1. RUNNING MENTOR GRAPHICS Note: These commands can be run remotely via ssh to one of the DSIL machines. If running remotely, ignore the references to GNOME, and there's no need to start up an xterm if you're in an ssh session. However, once you're physically in the DSIL lab, you MUST run the GNOME window manager.

• Log into a DSIL workstation. Make sure that at the login screen, you choose "GNOME" under the "Session" pulldown menu.

• Start up a terminal/xterm window. (Right click -> terminal)

• At the command prompt, type "cd" and hit the Enter key to make sure that you're in your

home directory. 2. USING ICSTUDIO

• Open the .cshrc file in your root directory. Add the following lines:

setenv MGC_ICSTD_CLASSIC_APPS yes source /ece/digital/share/mgc_hep/technology/ic/EE261_FALL_06/setup_mentor_ic_linux source /ece/digital/share/mgc_hep/technology/ic/AMI_5um_mentorkit/source_me

Note: Add them in this if-block: if ( `uname` == Linux ) then ... endif

• Create a folder named EE261CLASS in your user directory: Open terminal window and type: mkdir EE261CLASS

• Open a terminal window and type: icstudio

You will see the icstudio window. (Figure-1)

Figure 1

• Go to File->New->Project New project wizard will pop-up. (Figure-2) Click "Next".

Figure 2

• As project name, enter EE261CLASS (or anything you want)

As project location, select the folder you have just created (EE261CLASS) Note: Folder name is not important. Click "Next". (Figure-3)

Figure 3

• You need to set the location map in this step.

Click on "Open Location Map Editor". (Figure-4)

Figure 4

Click on "Import" button. (Figure-5) Go to /ece/digital/share/mgc_hep/technology/ic/EE261_FALL_06/ and select the file named mgc_location_map. Click on "Open". Then, click on "OK".

Figure 5

Figure 7

Click on "Next". (Figure-8)

Figure 8

• In this step, process rule files will be selected.

Click on "Open Settings Editor". (Figure-9)

Figure 9

For the fields shown in figure-10, enter/select the following values:

Process File: /ece/digital/share/mgc_hep/technology/ic/EE261_FALL_06/process/ami_c5

DRC Rules File: /ece/digital/share/mgc_hep/technology/ic/EE261_FALL_06/DRC/calAnaDRCc5.rul

LVS Rules File: /ece/digital/share/mgc_hep/technology/ic/EE261_FALL_06/LVS/calibreEXT.rul

SDL Rules File: /ece/digital/share/mgc_hep/technology/ic/EE261_FALL_06/process/sdl_process_rules

Figure 10

Then, click on OK. (Figure-11)

Figure 11

• Click on "Next" and then "Finish". (You can see the project configuration before clicking

finish button) (Figure-12)

Figure 12

NOTE: If you need to change some settings of the project:

Go to Tools -> Preferences -> Click on Project tab Go to Tools -> Location Map Editor

NOTE: ICStudio opens the last project at start-up. If you want to change this option,

Go to Tools -> Preferences -> Click on General tab Change the option for "When starting, open most recently opened project"

NOTE: You don't need create a new project for each homework or project. You can work in a single project environment, by adding different libraries. (File->New->Library) 3. DESIGN EXAMPLE: NAND3 1- In ICStudio, go to File New Library. Enter "test_library" as the library name. (Figure-13) ICStudio will create a folder for your library under the project folder.

Figure 13 2- Select the newly created test_library folder from Library window. (Figure-14) Then, go to File Import Verilog

Figure 14

3- Select "Verilog/Symbol" option for "Views to be created". (Figure-15) View Name: nand3 Verilog Netlist: /ece/digital/share/mgc_hep/technology/ic/mahmutkit/verilog/nand3.v Language: Verilog Click on "Import". (Figure-16)

Figure 15

Figure 16

NOTE: The folder /ece/digital/share/mgc_hep/technology/ic/mahmutkit/verilog includes verilog codes for some basic cells. If you are familiar with verilog, you can create your own verilog code and import it. If in the future, you need a verilog code for a cell that is not given in this folder, please contact your TA for help. 4- In the "create symbol options" window, select AND as shape type. Click "Create Symbol". (Figure-17)

Figure 17

5- Double click on "Symbol" in the "View" pane. (Figure-18)

Figure 18

6- The generated symbol is AND-3. We need to convert it to NAND-3. (Figure-19)

Figure 19

Go to Setup Select Filter and select all options, then click OK. Use Add Circle button (on the right side of the window) to create a small circle. Move the PIN at the output of the gate to right, and place the circle before the PIN. (Figure-20)

Figure 20

Then, connect the circle and the PIN using Add Polyline button. Delete vl_logic texts (Select and press Del) Click on Check&Save button (on the right side of the window). NOTE: You can use F2 key to deselect a selected object. Close DA-IC window and return to ICStudio. You will see in the "View" pane that the verilog code is now shown in red color for nand3 (Figure-22). Since we have changed the symbol, we need to compile the verilog code again to check for consistency. Right click the verilog code and select Check HDL.

Figure 22

7- Creating schematic of NAND3: Right click nand3 in the Cell pane, and select "New View". Select "Schematic" as view type and click "Finish". (Figure-23)

Figure 23

A DA-IC window will be opened. (Figure-24)

Figure 24

Click on "Library" button (on the right side of the window). Then, click on "MOS" button. (Figure-25)

Figure 25

Click on NMOS, and enter the following values: W=9, L=1, M=1 (Figure-26)

Figure 26

Place 3 NMOS transistors in this way. (Figure-27)

Figure 27

Similarly, click on MOS, select PMOS, and enter the following values: W=6, L=1, M=1

Place 3 PMOS transistors above NMOS ones. (Figure-28)

Figure 28

Click on "Basic Library" button (on the right side of the window). Then, click on "Generic Library". (Figure-29)

Figure 29

Click on "Ground" and place it below the NMOS transistors. Click on "VDD" and place it above the PMOS transistors. (Figure-30)

Figure 30

Click on "portin" and place three input ports on the left side. Click on "portout" and place an output port on the right side. (Figure-31)

Figure 31

Select the first input port, press "l" (el) to change its properties, and name it as A. (New Value=A) Similarly, name other input ports as B,C and output port as Q. (Figure-32-33) NOTE: Port names should be the same as stated in the verilog code. This was also the case for symbol, but for symbol, all ports were created automatically. Press "w" key to start wiring mode. Then, make the connections. (Figure-32-33) Then, press check&save button (3rd button under the menu bar) Close DA-IC.

Figure 32- 33

8- Digital Simulation of NAND3: Return to ICStudio. In the Cell pane, right click and select new view. (Not on nand3) Enter the name "nand3_digitaltest" and type Schematic. DA-IC window will be opened. Press "i" key to add instance. Select test_library : nand3 symbol (Figure-34)

Figure 34

Add a portin to the left side, rename it as IN[2:0], add a portout to the right side, rename it as OUT. (Figure-35)

Figure 35

(To add ports, either use the procedure described above or use Add Port button on the right side of the window. You can also use the toolbox on the left side.)

Press to "W" key (bus) and add a bus starting from input port (Figure-36).

Figure 36

Press to "w" key (wire) and connect the input ports of NAND to the bus. You will asked for bit numbers. Enter 0,1, and 2. Then, press "w" and connect the output of NAND3 to OUT. (Figure-37)

Figure 37

Click on "Check&Save" button. Then, click on "Simulation" button. (Figure-38)

Figure 38

Select "Digital Simulation" and enter the name "digitalSim". Click OK twice to enter simulation mode. (Figure-39)

Figure 39

In the simulation mode, click on Session button (left top button), and select Simulator/Viewer Options. Click on Advance Setup and select ns as time unit. (Figure-40)

Figure 40

Click on "Netlist and Run" to start simulation. Both EZWave (Figure-41) and Modelsim (Figure-42) windows will be opened. You will do your simulations in Modelsim and see the waves in EZWave.

Figure 41

Figure 42

In ModelSim, in the Objects pane, right click the signal names IN and OUT and select Add to Wave

Selected Signals. You have added these signals to wave window. Go to EZWave window and see. (Figure-43)

Figure 43

Return to ModelSim, go to Objects pane again. Right click the signal name IN, click "Force" and enter the signal values 101. Click OK. In ModelSim, set the run length as 1 ns (100fs default value). Press on "Run" button which is on the right side of Run Length box. Go to EZWave, and see the results in wave window. (Figure-44)

Figure 44

Return to ModelSim, go to Objects pane again. Right click the signal name IN [2], click "Clock" and enter period 1 ns. Click OK. (Figure-45) Right click the signal name IN [1], click "Clock" and enter period 2 ns. Click OK. Right click the signal name IN [0], click "Force" enter value 1. Click OK. Now, click Run button in ModelSim several times, then go to EZWave and see the results.

Figure 45

NOTE: Adding timing to digital simulations: - Go to Simulation window in DA_IC and see that NAND3 gate has properties called like: TDR_A_Q : A to Q rising signal delay TDF_A_Q : A to Q falling signal delay - Right click on NAND3, click "Edit Properties" (Figure-46) and enter the wanted delay values there. Click Apply-OK.

Figure 46

- Restart the simulation and observe the delay on signals. - If changing the cell properties does not add delays, you need to change your verilog code, and define delays in it. (Default values are set to 0.00ns) NOTE: If you don't want to use EZWave to view the waves, in DA_IC simulation mode, go to Session Simulator, and uncheck the option to see the waves in EZWave. Then, you can see the waves in ModelSim. 9- AMS Simulation: For AMS simulation, return to icstudio. In the Cell pane, right click and select new view. (Not on nand3) Enter the name "nand3_analogtest" and type Schematic. DA-IC window will be opened. Press "i" key to add instance. Select test_library : nand3 symbol (Figure-47)

Figure 47

Add a portin to the left side, rename it as IN1,IN2 and IN3, add a portout to the right side, rename it as OUT. (Figure-48)

Figure 48

Click on Basic Library button then Generic Lib. Choose VDD to add a VDD instance, Ground to add a Ground instance. Click on Back and then Sources Lib. Click on DC to add the power supply and click on Pulse to add a Pulse source. (Figure-49) Change delay of all pulse sources to 0 and adjust the periods and widths to the desired values (p1: 60ns w1:20ns, p2: 80ns w2:30ns, p3:100ns, w3:40ns). Change the magnitude of DC voltage to 1.2V. (Right click on instance properties edit)

Figure 49

Click on "Check&Save" button. Then, click on "Simulation" button. (Figure-50)

Figure 50

Select "AMS Simulation" and enter the name "analogSim". Click OK twice to enter simulation mode. (Figure-51)

Figure 51

Click on Setup menu and choose Model Libraries. Click browse button and choose mos_eldo.lib and click OK twice. (Figure 52)

Figure 52

Click on Setup Analysis button, check Transient and click on setup button right next to Transient. Add the values to the corresponding places as shown in the figure below. Click OK twice. (Figure-53).

Figure 53

Click on Setup Outputs button and choose Save. Check only Voltages and click OK. (Figure 54)

Figure 54

Click on netlist & simulate and see if any error comes out in the opened two log files. If there is no error, click on View Outputs button. An Ezwave window will be opened. Choose the waveforms from the left to plot. Right click on the waveform name and choose plot. (Figure 55)

Figure 55

10 DRC – LVS Check: Return to icstudio. Right click on Layout view of the cell properties, under Custom tab choose schematic as the Connectivity Source and click OK. Click twice on Layout view of the cell. IC Station window will be opened. (Figure-56)

Figure 56

DRC: Click on Tools Calibre Run DRC. Change $MGC_HOME to $CAL_HOME and click OK. (Figure-57)

Figure 57

In the opened window, click on Run DRC button then click OK. The Calibre will run DRC and opens some result windows, look for Calibre Interactive DRC: window. The third line states the DRC results (Figure 58)

Figure 58

LVS: Click on Tools Calibre Run LVS. Calibre Interactive LVS: window will be opened. (Figure 59)

Figure 59

Under the Netlist tab choose ‘Export from schematic viewer’ and click on Run LVS button. The Calibre will run LVS and opens some result windows, look for smiling face on the LVS Report File window (Figure 60).

Figure 60