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Introduction to Computer ScienceLecture 2: Data Manipulation
Tian-Li Yu
Taiwan Evolutionary Intelligence Laboratory (TEIL)Department of Electrical Engineering
National Taiwan University
Slides made by Tian-Li Yu, Jie-Wei Wu, and Chu-Yu Hsu
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Motherboard
CPU Slot
Memory Slot
Tian-Li Yu Data Manipulation 2 / 19
Computer Architecture
CPU(central processing unit)
Registers
Memory
Bus
Motherboard
Arithmetic/logic
unitControl
unit
Registers
Bus
Main memoryCentral processing unit
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Adding Values Stored in Memory
1 Get one of the values to be added from memoryand place it in a register.
2 Get the other value to be added from memory andplace it in another register.
3 Activate the addition circuitry with the registersused in Steps 1 and 2 as inputs and another registerdesignated to hold the result.
4 Store the result in memory.
5 Stop.
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Machine Instructions
Data transferLOAD, STORE, I/O
Arithmetic/logicAND, OR, ADD, SUB, etc.SHIFT, ROTATE
ControlJUMP, HALT
RISC (Reduced Instruction Set Computing) (PRC, SPARC)vs. CISC (Complex instruction set computing) (x86, x86-64)
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Architecture of a Simple Machine
Bus
00
Address Cells
01
02
FF
Main memoryCentral processing unit
Arithmetic/logic
unit
Control unit
Registers
0
1
F
Program counter
Instruction register
2
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Example of a Machine Instructions
0011 0101 1010 0111
Op-code Operand
3 5 A 7
Actual bit pattern (16 bits)
Hexadecimal form
Store (3) the content of register no. 5 to the memory cell addressed A7
Memory reference: 28 = 256 cells (bytes)
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Adding Two Values Revisited
Encodedinstructions
Translation Possible assembly Possible C
156CLoad register 5 with the bitpattern found in the memorycell at address 6C.
LOAD 5, 6C
166DLoad register 6 with the bitpattern found in the memorycell at address 6D.
LOAD 6, 6D
5056
Add the contents of register 5and 6 as two complementrepresentation and leave theresult in register 0.
ADD 0, 5, 6
306EStore the contents of register0 in the memory cell ataddress 6E.
STORE 0, 6E
C000 Halt. HALT
c = a + b;
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Program Execution
Instruction register, program counterMachine cycle
clockbenchmarking
Retrieve the next instruction
from memory (as indicated by
the program counter) and then
increment the program
counter.
1.
Decode the bit pattern in
the instruction register.
2.
Perform the action
required by the
instruction in the
instruction register.
3.
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Fetch
Main memoryCPU
Bus
Registers
0
1
F
A0
Program counter
Instruction register
Address Cells
15A0
6CA1
16A2
6DA3
50A4
56A5
30A6
6EA7
C0A8
00A9
Program counter contains address of first
instructions.
Program is
stored in main
memory
beginning at
address A0.
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Logic/Bit Operations
Masking
AND0101010100001111
00000101
Setting the first 4 bitsto 0.
OR0101010100001111
01011111
Setting the latter 4bits to 1.
XOR0101010100001111
01011010
Inverting the latter 4bits.
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Shift/Rotation
Logic shift10100000 → 01010000 (right)
→ 01000000 (left)
Arithmetic shift10100000 → 11010000 (right)
→ 11000000 (left)
Rotation10100000 → 01010000 (right)
→ 01000001 (left)
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Controller
SpecializedGeneral: USB, FireWire
CPUMain
memory
Bus
Controller
Monitor
Controller
Disk drive
Controller
CD drive
Controller
Modem
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Memory-mapped I/O
I/O as LOAD, STORE
CPU
Main
memory
Bus
Controller Peripheral device
Port
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Communication with Other Devices
DMA: direct memory access
Once authorized, controllers can access data directly from main memory without notifyingCPU.
Hand shaking
2-way communicationCoordinating activities
Parallel/Serial
Transfer rate: bit per second (bps, Kbps, Mbps, etc)
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Pipelining
Throughput increasedTotal amount of work accomplished in a given amount of time.
Example: pre-fetchingIssue: conditional jump
Fetch Decode Execute
Fetch Decode Execute
Fetch Decode Execute
Time
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Parallel/distributed Computing
ParallelMultiprocessorMIMD, SISD, SIMD
DistributedLinking several computers via networkSeparate processors, separate memory
Issues:Data dependencyLoad balancingSynchronizationReliability
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To Parallelize XOR Not to Parallelize
declare A[0]~A[99]
input A[0], A[1], A[2]
for (i = 3; i<100; i++)
A[i] = A[i-2] + A[i-3];
for (i = 3; i<98; i+=2) {
A[i] = A[i-2] + A[i-3];
A[i+1] = A[i-1] + A[i-2];
}
A[99] = A[97] + A[96];
2 CPUs
CPU 0
CPU 1
declare A[0]~A[99]
input A[0]
for (i = 1; i<100; i++)
A[i] = A[i-1] * 2;
How to parallelize?
A[1]=A[0] * 2;
for (i = 2; i<100; i+=2) {
A[i] = A[i-2] * 4;
A[i+1] = A[i-1] * 4;
}
CPU 0
CPU 1
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Speedup & Scaling
Speedup(Amdahl’s law)
SM
PGain
1=
+
5 10 15 20 25 30 35 400
5
10
15
20
25
30
Number of Processors
Gain
Ideal
Practical
P : parallelizableS : serial only
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License
Page File Licensing Source/ author
2
flickr, Author: viagallery.com, Source:
http://www.flickr.com/photos/viagallery/2036598755/, Date:
2012/02/19, This file is made available under the Creative
Commons Attribution 2.0 Generic
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