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Introduction to synthesis

Lecture 5

Logic Synthesis

Logic synthesis operates on boolean equationsand produce optimized combinational logic

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Logic Minimization• Two-level logic minimization

– Two-level logic usually is one of the• sum-of-product : f = ab+cd+ef …• product-of-sum : f = (a+b)(c+d)(e+f) ...

• Multi-level logic minimization– Find terms that can be shared– In algebraic term, find common “factors”

• f = ab+ac+db+dc = a(b+c) +d(b+c) = (a+d)(b+c)

Example – 2 level• F = abc + abd + a’c’d’ + b’c’d’

– 4 NOTs, 4 3-input ANDs, and 1 4-input OR

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Example – multi level• Decomposition

– X = ab, Y = c+d, F = XY + X’Y’• Implement F with multi-level logic

– 2 NOTs, 3 2-input ANDs, and 2 2-input ORs

Two level logic minimization• Two-level logic minimization can be seen as the origin of

logic synthesis– Theory and algorithms are well developed long time ago– We will study these algorithms this month

• Any 1-output combinational function can be implemented as 2-level SOP– In the worst case, you can get the truth table and collect min-terms

• Simple SOP may not be the most efficient way– Need to find “prime implicant”– Multi-level logic will reduce size– What if implementing multiple functions?

• Need to find minimal implementation (shared implicants)

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2-level minimal implementation• Theorem (Quine): A minimal SOP

implementation of a function must always consist of a sum of prime implicants– Apply to 2-level logic only– So finding prime implicants are crucial

• Implicant: a product term p that is included in the function f– F=xy’+yz => xy’ and xyz are implicant

• Prime Implicant: an implicant that is not included in any other implicant– xy’ is prime, but xyz is not

High Level Synthesis• Remember that your Verilog code is “event-

driven” under the simulation model– blocks are executed in parallel

• Your hardware is done from primary inputs to primary outputs

• How does it convert Verilog code into hardware?– Something is missing here ….

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Determine the order of data flow • To convert a parallel-styled description into

a sequential logic– it needs to first determine the ORDERING in the

data flow

• In synthesis, it constructs a so-called “data flow graph” to represent the overall computation– Based on the data flow graph, it will decide

• how many latches should be used• where to put them in the logic (the ordering), etc.

A Simple Example - Flow Graph

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Synthesis Has Limitations

• Synthesis is not a magic word• Many behavior descriptions are not

synthesizable!• Results of synthesis may not satisfy the

needs– too big, too slow, or even contain errors– custom designs are required– verification is required (never trust the synthesis

results completely)

Commonly-Supported Constructs

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Unsupported Constructs

Combinational Logic Elements

• Commonly synthesized combinational logic

Multiplexer Adder

Decoder Subtractor

Encoder ALU

Comparator Multiplier

Random Logic PLA Structure

Lookup Table Parity Generator

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Synthesis examples

A quick look

Synthesis Example A>B A1 B1 A0 B00 00

00

00 0

0 00

01

11 1

0 10

11

00 1

0 00

01

11 1

1 01

00

11 0

0 00

01

11 1

1 11

11

11 1

0 00

01

11 1

0010000011110010

A_lt_B = A1 B1 + A1 A0 B0 + A0 B1 B0

A_gt_B = A1 B1 + A0 B1 B0 + A1 A0 B0

A_eq_B = A1 A0 B1 B0 + A1 A0 B1 B0 + A1 A0 B1 B0 + A1 A0 B1 B0

TWO-BIT

COMPARATOR

A_lt_B

A_gt_B

A_eq_B

A1

B1

A0

B0

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Gate ImplementationA1

B1

A0

B0

W6

W7

W1

W2

W3

W4

W5

A_lt_B

A_gt_B

A_eq_B

module compare_2_str (A_lt_B, A_gt_B, A_eq_B, A0, A1, B0, B1);

input A0, A1, B0, B1;output A_lt_B, A_gt_B, A_eq_B;wire w1, w2, w3, w4, w5, w6, w7;

or (A_lt_B, w1, w2, w3);nor (A_gt_B, A_lt_B, A_eq_B);and (A_eq_B, w4, w5);and (w1, w6, B1);and (w2, w6, w7, B0);and (w3, w7, B0, B1);not (w6, A1);not (w7, A0);xnor (w4, A1, B1);xnor (w5, A0, B0);

endmodule

Using If-Else

Procedure-style behavior code

module compare_2_algo (A_lt_B, A_gt_B, A_eq_B, A, B);

input [1:0] A, B;output A_lt_B, A_gt_B, A_eq_B;reg A_lt_B, A_gt_B, A_eq_B;

always @ (A or B) // Behavior and event expressionbeginA_lt_B = 0;A_gt_B = 0;A_eq_B = 0;if (A==B) A_eq_B = 1;else if (A > B) A_gt_B = 1;else A_lt_B = 1;

endendmodule

BEHAVIOR

A_lt_B

A_gt_B

A_eq_B

A1

B1

A0

B0

reg

reg

reg

A_lt_B

A_gt_B

A_eq_B

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Two Synthesized Results

A1

B1

A0

B0

W6

W7

W1

W2

W3

W4

W5

A_lt_B

A_gt_B

A_eq_B

A_lt_B

A_gt_B

A_eq_B

A[1]

B[1]

A[0]

B[0]B[1:0]

A[1:0]

From behavior:

From gates:

Synthesize decision w/ MUX

The example is just a pseudo code

Procedure CC(Rin) {if ( test(Rin) )

{res = Rin + 32;}else

{res = Rin – 32;}end

test

+/-32

Rin

resselect

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Synthesis with library cellsmodule or_nand_1 (enable, x1, x2, x3, x4, y);input enable, x1, x2, x3, x4;output y;wire w1, w2, w3;or (w1, x1, x2);or (w2, x3, x4);or (w3, x3, x4); // redundantnand(y, w1, w2, w3, enable);endmodule

Example – bit-wise operations

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Multi-level synthesis

Identify shared logic in multi-level structure

Control Logic for MUX Datapath

• 4 channel mux with a continuous assignment

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Synthesized LogicCheck sel=0,1,2,3

Synthesis of MUX

Decoded MUX

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If-then-else

2-1 MUXfor an if

Control Logic at Select Line

Control logic

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Unexpected Latches

• When a case statement is incomplete, the synthesis may infer the need of a latch to hold result while unspecified inputs present

General Synthesis Result

when (sel_a, sel_b)=00, 11, y_out keeps the old value

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Priority Decode Structure

highlow

Technology Mapping

Tech Libraries contains cell implemented withcertain technology (0.13μ, 0.18 μ, or 0.25 μ, etc.)

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Technology Mapping

Library Cell Mapping

5-bit adder

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Enforce Shared Resource

We want to use 1 adder, instead of 2

Cont…

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Buses and Tri-state Buffer

Bidirectional Buses

bidirectional

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Mux Bus Driver

Tri-State and Don’t Care

Don’t care

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Two Versions

Optimized with don’t care

Summary• Synthesis is not magic

– It can make mistakes– Or produce unsatisfactory results

• Much of the synthesis intelligence comes from add-hoc rules and pattern matching

• Writing code to influence a synthesis tool demands great experience– Today, because of EDA tools, doing design has a lot to do

with working around the tool(s)• Synthesis happens at different levels

– Behavior, high-level– 2-level and multi logic level

• Synthesis can be independent of technology mapping• Physical synthesis is an entirely different process

– Contains placement and routing