Interfacing the TLV2541 ADC and the TLV5618A DAC to the

Application ReportSLAA111 - November 2000

1

Interfacing the TLV2541 ADC and the TLV5618A DAC tothe TMS320C31 DSP

Joselito Parguian AAP Data Converters

ABSTRACT

This application report is written to help design engineers or technicians implement a simpledata acquisition system using serial analog-to-digital converters (ADCs) anddigital-to-analog converters (DACs) from Texas Instruments. A hardware and softwaresolution for interfacing the TLV2541 ADC and the TLV5618A DAC to the TMS320C31 DSPwith the use of the TMS320C3x DSP starter kit (DSK) is presented here.

In addition, the new multi-converter EVM (EVM0309) from Texas Instruments is brieflydiscussed, since this is the evaluation module used to demonstrate the functionality of bothADCs and DACs.

Contents

1 Introduction 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Hardware 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Host PC 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 TMS320C3x DSP Starter Kit (DSK) 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 DSK Overview 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 The Multi-Converter EVM 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 The TMS320C31 DSP Bidirectional Serial Port 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Serial-Port Global Control Register 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 FSX/DX/CLKX Port-Control Register 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 FSR/DR/CLKR Port-Control Register 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Receive/Transmit Timer-Control Register 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Receive/Transmit Timer-Counter Register 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Receive/Transmit Timer-Period Register 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Serial-Port Timing 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 Serial-Port Initialization/Reconfiguration 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 Serial Port Operation 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 The ADC 14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 TLV2541 Pin Function 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Hardware Considerations 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 The DAC 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 The DAC Pin Function 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 The DAC Data Format 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 DAC Timing Requirement 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 The System 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SLAA111

2 Interfacing the TLV2541 ADC and the TLV5618A DAC to the TMS320C31 DSP

6.1 Operation and Timing 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Summary 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 References 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix A TLV2541.ASM 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix B Program and Data Memory Mapping 30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Figures

1 Serial-Port Global Control Register 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Serial-Port Configuration Word 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 FSX/DX/CLKX Port-Control Register 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 FSR/DR/CLKR Port-Control Register 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Receive/Transmit Timer-Control Register 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Receive/Transmit Timer-Counter Register 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Receive/Transmit Timer-Period Register 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TLV2541 Functional Block Diagram 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Typical Hardware Configuration for a Glueless Logic Connection (Dedicated Device) 16. . . . . . . . . . . 10 Alternative Hardware Configuration for a Glueless Logic Connection (Dedicated Device) 17. . . . . . . 11 Timing Diagram (CS = 0, FS = Frame Sync Signal) 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Timing Diagram (CS = Frame Sync Signal, FS = 1) 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Hardware Configuration for Devices Sharing the DSP Serial Port 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Timing Diagram (CS = Chip Select, FS = Frame Sync) 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Functional Block Diagram of the TLV5618A 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 DSP Data Manipulation of ADC Data for DAC Data Format 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DAC Data Format 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DAC Timing Diagram 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Hardware Configuration 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ADC and DAC Timing Diagram 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Illustration of the Complete Data Acquisition System 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Tables

1 List of Serial Analog-to-Digital Converters Supported by the Multi-Converter EVM 6. . . . . . . . . . . . . . . 2 List of Serial Digital-to-Analog Converters Supported by the Multi-Converter EVM 6. . . . . . . . . . . . . . . 3 Registers Associated With the Serial Port 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Serial-Port Global Control Register Definition 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Receive/Transmit Timer-Control Register Bit Definition 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Register-Select Bits 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SLAA111


1 Introduction

Texas Instruments provides a wide variety of digital signal processors (DSPs). While there aremany TI DSPs to choose from, this application report will focus on the TMS320C31 DSP forsimplicity. The TMS320C31 DSP is a high-performance CMOS 32-bit floating-point digital signalprocessor. The ’C31 DSP integrates both system control and math-intensive functions on asingle controller and is capable of 25 million instructions per second (MIPS) and 50 millionfloating-point operations per second (MFLOPS). This processor provides a total memory spaceof 16 million 32-bit words that contain program, data, and I/O space. Two RAM blocks of 1K × 32bits each and a boot loader permits the ’C31 DSP to perform two CPU accesses in a singlecycle. A 64 × 32-bit instruction cache is also provided to store often-repeated sections of code toreduce the number of off-chip accesses. The ’C31 DSP has one standard, bidirectional serialport, which will be the main focus of this report for interfacing the ADC and the DAC. TheTMS320C3x DSK is used to facilitate interfacing the ADC and DAC to the DSP.

The TLV2541 is a high-performance, 12-bit, low-power, CMOS analog-to-digital converter(ADC). The architecture of this device is based upon a successive approximation register (SAR).This ADC operates from a single wide-range power supply, typically from a minimum of 2.7 V toa maximum of 5.5 V. This device is designed to operate with very low power consumption, withpower savings further enhanced by an auto-power-down mode. The conversion speed is notprogrammable, because the device uses only a built-in oscillator as its source of conversionclocking. The built-in oscillator provides a fixed conversion time of 3.5 µs.

The TLV5618A is a dual 12-bit voltage output DAC and is also a CMOS device. This device isdesigned to operate from a single, wide-range supply voltage. The dual channel output of theDAC is buffered by a 2×-gain rail-to-rail output buffer. The buffer features a Class-AB outputstage to improve stability and reduce settling time. The programmable settling time allows thedesigner to optimize speed versus power dissipation. The DAC is specifically included toreconstruct the original analog input of the ADC for verification purposes. The DAC output is anapproximation of the ADC input signal.

This application report therefore provides an overview of the hardware interface as well as thesoftware interface. It should aid the user to become familiar with the DSP as well as the dataconverters used. The software programs included in this report will also allow the user to bequickly acquainted with the data converters and the DSP standard serial port.

2 Hardware

The hardware consists of a host PC, the TMS320C3x DSK, and the multi-converter evaluationmodule.

2.1 Host PC

The following is a list of the minimum recommended requirements for the host PC:

• An IBM PC/AT or 100%-compatible PC

• Hard disk drive

• Floppy-disk drive

IBM and AT are trademarks of International Business Machines Corporation.

SLAA111


• 640 Kbytes minimum memory

• Monochrome or color display (color recommended)

• Parallel printer port communication link

• Straight-through parallel printer port cable

• MS-DOS or PC-DOS (version 5.0 or later), Windows or OS/2 operating system

• XDS510 emulator card (optional)

• MPSD cable (optional)

The optional XDS510 (TI P/N TMDS00510M, MPSD cable and emulator card) emulator ispreferred if available.

The assembly program provided in this report, to interface the data converters to the DSP, iswritten using Code Composer software. If the DSK assembler/debugger is preferred overCode Composer software, then the program provided in the appendix section of this reportmust be modified slightly to suit the DSK assembler environment. You can use almost any ASCIIprogram editor to create and modify a DSK assembler source file. The modification consists ofadding an assembler directive to the beginning of the program to tell the assembler where tostart the program. You must ensure that the assembler directive (opcode) is not in the firstcolumn, otherwise it is interpreted as a label. An example of proper opcode positioning is shownin bold in the following code sequence.

.start “SP0TEST”, 0x809802

.sect “SP0TEST”;=========================================================================; Serial Port 0 registers;=========================================================================sport .set 808040h ; Serial Port 0 global control registerxpctrl .set 808042h ; FSX/DX/CLKX port control

. . .

Refer to the TMS320C3x DSP Starter Kit User’s Guide (literature number SPRU163) for moredetails in creating the assembler source codes.

2.2 TMS320C3x DSP Starter Kit (DSK)

Texas Instruments provides this TMS320C3x DSK, a low-cost, easy-to-use, high-performance,and expandable development platform that lets you experiment and develop real-time signalprocessing applications with the TMS320C3x DSP. This particular DSK has a TMS320C31 DSPonboard to allow full-speed verification of the TMS320C3x code. The DSK also gives you thefreedom to develop your own software on a PC and run it on the DSK board. The DSK caninterface to a host PC through the parallel printer port or through the use of the modular portscan device (MPSD) port interface to control the on-chip emulation. The MPSD interfacerequires additional accessories such as the MPSD cable and an emulator card as discussed insection 2.1.

MS-DOS and Windows are trademarks of Microsoft Corporation.OS/2 is a trademark of International Business Machines Corporation.Other trademarks are the property of their respective owners.

SLAA111


TMS320C31 DSK features are:

• Industry-standard TMS320C31 floating-point DSP

• 40-ns instruction cycle time, 50 MFLOPS, 25 MIPS

• Standard or enhanced parallel printer port interface which connects to a host PC allows theTMS320C31 DSP to communicate with PC programs

• Analog data acquisitions via the TLC32040 analog interface circuit (AIC):

– Variable rate analog-to-digital converter (ADC) and digital-to-analog converter (DAC) with14-bit dynamic range at 20 kSPS

– Output reconstruction filter and bypassable, switched-capacitor antialias input filter

• Standard RCA plug connectors for analog input and output that provide a direct connectionto microphone and speaker

• XDS510 emulator connector (Note: jumper and header are not installed)

• Expansion connectors, which route all the TMS320C31 pins for use with DSKdaughterboards

2.2.1 DSK Overview

The DSK hardware is a complete platform solution for the development of any conceivableproject that requires the processing power of the TMS320C31 DSP. This DSK can be used tointerface and communicate directly to a host PC and allow you to create your own software,download the software onto the DSK, and run the software on the DSK board. It also gives youthe freedom to evaluate the onboard analog interface circuit (AIC) or analyze external analoginput and output signals through the two RCA connectors provided onboard. The TLC32040 AICinterfaces to the TMS320C31 DSP serial port. A jumper block allows removal of this connectionto route the serial port to a user-supplied DSK daughterboard.

Refer to the TMS320C3x DSP Starter Kit User’s Guide (literature number SPRU163) for moreinformation regarding DSK installation and operation.

2.3 The Multi-Converter EVM

Texas Instruments offers a low-cost solution for customers who would like to quickly evaluatecertain devices through the use of an evaluation module (EVM). The EVM used for this report isthe multi-converter EVM (P/N MULTICNVTR-EVM), a platform designed to evaluate families of8-pin serial ADCs and DACs under various signal, reference, and supply conditions. Althoughthe multi-converter EVM is used in this report, coverage includes only the ADC and DACdevices mentioned previously. This does not prevent the use of any other devices listed inTable 1 and Table 2, provided that the user is familiar with devices not discussed in this report.Alternatively, the user can refer to the device data sheet and the Multi-Converter EVM User’sGuide (literature number SLAU047A) for information. Parts in bold letters are the only devicesdiscussed in this report.

SLAA111


Table 1. List of Serial Analog-to-Digital Converters Supported by the Multi-Converter EVM

PART NUMBER INPUT CHANNELS INPUT SIGNAL MAXIMUM THROUGHPUT

TLV2541 Single Unipolar 200 kSPS

TLV2542 Dual with autosweep Unipolar 200 kSPS

TLV2545 Single with pseudo-differential Pseudo-differential 200 kSPS

TLC2551 Single Unipolar 400 kSPS

TLC2552 Dual with autosweep Unipolar 400 kSPS

TLC2555 Single with pseudo-differential Pseudo-differential 400 kSPS

Table 2. List of Serial Digital-to-Analog Converters Supported by the Multi-Converter EVM

PART NUMBER RESOLUTION (BITS) OUTPUT CHANNEL INTERNAL REFERENCE

TLV5623 8 1 No

TLV5624 8 1 Yes

TLV5625 8 2 No

TLV5626 8 2 Yes

TLV5606 10 1 No

TLV5617A 10 2 No

TLV5637 10 2 Yes

TLV5616 12 1 No

TLV5618A 12 2 No

TLV5636 12 1 Yes

TLV5638 12 2 Yes

The multi-converter EVM is also capable of operating continuously in stand-alone mode (SAM).This feature is very useful when checking the functionality of the EVM itself, or the ADC or DACdevice when a host DSP is not readily available. A quick reference guide (QRG) is included inthe package when ordering this multi-converter EVM. The QRG will assist the user to configurethe EVM quickly for the different data converter combination setups, and to have it up andrunning in a minimum amount of time.

3 The TMS320C31 DSP Bidirectional Serial Port

The TMS320C31 DSP has one standard bidirectional serial port. The TMS320C31 serial port isa versatile communication channel that allows interfacing to most serial interface analogconversion chips without glue logic. The serial port can be configured to transfer 8, 16, 24, or 32bits of data per word simultaneously in both directions. The clock for the serial port can besupplied externally, or can originate internally through the serial port timer and period registers.The internally generated clock is a divide-down of the clock-out (CLKOUT) frequency, f(H1). Thisis discussed in Section 3.7.

The serial port is used to transmit and receive data between the DSP and the ADC, and theconfiguration described below is specific to the way that the DSP communicates with the ADCfor this application. Note that the user can always tailor the configuration to situationrequirements. The DSP serial port requires a little more time and understanding when initializingand configuring, compared to the data converters. Therefore, this report will explain the serialinterface in some detail. Six control lines from the DSP are used to interface to the dataconverters:

SLAA111


CLKX Transmit frame synchronization input or output

This signal clocks data from the transmit shift register (XSR) to the data transmit(DX) pin. The serial port can be configured for internal clock generation or toaccept an external clock. If the port is configured to generate the data clockon-chip, CLKX becomes an output, providing the data clock for the serial interface.If the port is configured to accept an external clock, CLKX changes to an input,receiving the external clock signal.

FSX Transmit frame synchronization input or output

FSX indicates the start of a data transfer. The serial port can be configured forinternal frame-sync generation or to accept an external frame-sync signal. If theport is configured to generate the frame-sync pulse on-chip, FSX becomes anoutput. If the port is configured to accept an external frame-sync pulse, this pinbecomes an input.

DX Serial data transmit

DX transmits the actual data from the transmit shift register (XSR).

CLKR Receive clock input

CLKR always receives an external clock for clocking the data from the datareceive (DR) pin into the receive shift register (RSR).

FSR Receive frame synchronization input

FSR always receives an external frame-sync pulse to initiate the reception of dataat the beginning of a frame.

DR Serial data receive

DR receives the actual data which are clocked into the receive shift register(RSR).

In addition to these six control lines, there are control, shift, and buffer registers that are all 32bits wide. These 32-bit wide registers support the standard serial port interface operation of theDSP. Each of these registers, except for the two shift registers (XSR and RSR), is located in itsspecific address mapped in memory. Table 3 shows the register names and their respectiveaddresses, and the values used for configuration.

Table 3. Registers Associated With the Serial PortREGISTER NAME ADDRESS (Hex) VALUE (Hex)

Serial-port global control 808040 0C140044

FSX / DX / CLKX port-control 808042 00000111

FSR / DR / CLKR port-control 808043 00000111

R / X timer-control 808044 000001CF

R / X timer-counter 808045 00000000

R / X timer-period 808046 00000000

Data-transmit (DXR) 808048 Variable

Data-receive (DRR) 80804C Variable

The control registers contain the control bits set by the CPU to configure the operation of thestandard serial port. The addressable buffer registers, DXR and DRR, are discussed further inSerial Port Operation, Section 3.9.

SLAA111


3.1 Serial-Port Global Control Register

The first thing to do is to define how the serial-port global control register (GCR) controls thefunction of the serial port and determines its operating mode. The physical structure of the serialport global control register is shown in Figure 1, and the function of the serial port global controlbits is described in Table 4. The serial port GCR is mapped in memory location 808040 hex andis referred as the serial port base address.

SERIAL-PORT GLOBAL CONTROL REGISTER (Upper Word)

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

NAME RRESET XRESET RINT RTINT XINT XTINT RLEN XLEN FSRP FSXP

TYPE X X X X R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0

SERIAL-PORT GLOBAL CONTROL REGISTER (Lower Word)

BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NAME DRP DXP CLKRP CLKXP RFSM XFSM RVAREN XVAREN RCLKSRCE

XCLKSRCE

HS RSRFULL

XSR

EMPTY

FSXOUT XRDY RRDY

TYPE R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R R

DEFAULT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

NOTE: R = read, W = write, X = reserved bit, read as 0

Figure 1. Serial-Port Global Control Register

SLAA111


Table 4. Serial-Port Global Control Register Definition

BIT NAME FUNCTION

0 RRDY RECEIVER READY (if 1, DRR has new data and is ready to be read; if 0, DRR has no new data)

1 XRDY TRANSMITTER READY (if 1, DXR has written the last bit of data to XSR and is ready for new data; if 0, DXR hasnot written the last bit of data to XSR and is not ready for a new data)

2 FSXOUT TRANSMIT FRAME SYNC (if 1, FSX is configured as an input; if 0, FSX is configured as an output)

3 XSREMPTY TRANSMIT SHIFT REGISTER (if 1, XSR is not empty; if 0, XSR is empty; Reset and XRESET causes this bit to beset to 0)

4 RSRFULL RECEIVE SHIFT REGISTER (if 1, RSR and DRR are full; if 0, no overrun of the receiver has occurred)

5 HS Handshake mode enable (if 1, HS is enabled; if 0, HS is disabled)

6 XCLK SRCE TRANSMIT CLOCK SOURCE (if 1, the internal transmit clock is used; if 0, the external transmit clock is used)

7 RCLK SRCE RECEIVE CLOCK SOURCE (if 1, the internal receive clock is used; if 0, the external receive clock is used)

8 XVAREN TRANSMIT DATA RATE MODE (if 1, data rate is variable and FSX is held active while all bits are being transmitted;if 0, data rate is fixed and FSX is only active for at least one XCLK cycle)

9 RVAREN RECEIVE DATA RATE MODE (if 1, data rate is variable and FSR is held active while all bits are being received; if 0,data rate is fixed and FSR is only active for at least one RCLK cycle)

10 XFSM TRANSMIT FRAME SYNC MODE (if 1, mode is continuous and FSX is only generated at the start of the first wordof a block transmitted; if 0, mode is standard and FSX is generated for every word transmit)

11 RFSM RECEIVE FRAME SYNC MODE (if 1, mode is continuous and FSR is only generated at the start of the first word ofa block received; if 0, mode is standard and FSR is generated for each word received)

12 CLKXP TRANSMIT CLOCK POLARITY (if 1, CLKX is active low; if 0, CLKX is active high)

13 CLKRP RECEIVE CLOCK POLARITY (if 1, CLKR is active low; if 0, CLKR is active high)

14 DXP DATA TRANSMIT POLARITY (if 1, DX is active low; if 0, DX is active high)

15 DRP DATA RECEIVE POLARITY (if 1, DR is active low; if 0, DR is active high)

16 FSXP TRANSMIT FRAME SYNC POLARITY (if 1, FSX is active low; if 0, FSX is active high)

17 FSRP RECEIVE FRAME SYNC POLARITY (if 1, FSR is active low; if 0, FSR is active high)

18–19 XLEN TRANSMIT WORD LENGTH ( 8/16/24/32 )

20–21 RLEN RECEIVE WORD LENGTH ( 8/16/24/32 )

22 XTINT TRANSMIT TIMER INTERRUPT ENABLE (if 1, transmit timer interrupt is enabled; if 0, transmit timer interrupt isdisabled)

23 XINT TRANSMIT INTERRUPT ENABLE (if 1, transmit interrupt is enabled; if 0, transmit interrupt is disabled)

24 RTINT RECEIVE TIMER INTERRUPT ENABLE (if 1, receive timer interrupt is enabled; if 0, receive timer interrupt isdisabled)

25 RINT RECEIVE INTERRUPT ENABLE (if 1, receive interrupt is enabled; if 0, receive interrupt is disabled)

26 XRESET TRANSMIT RESET (if 1, the transmit side of the serial port is taken out of reset; if 0, transmit side of the serial port isreset)

27 RRESET RECEIVE RESET (if 1, the receive side of the serial port is taken out of reset; if 0, receive side of the serial port isreset)

28–31 RESERVE BITS READ AS ZERO

SLAA111


Figure 2 shows in both binary and hex format the code that is loaded into the serial-port globalcontrol register.

BIT 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

VALUE (BIN) X X X X 1 1 0 0 0 0 0 1 0 1 0 0

VALUE (HEX) 0 C 1 4

BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

VALUE (BIN) 0 0 0 0 0 0 0 0 0 1 0 R R 1 R R

VALUE (HEX) 0 0 4 4

NOTE: X represents reserved bits and R are read-only bits.

Figure 2. Serial-Port Configuration Word

The configuration word chosen for the serial-port GCR configures the serial port as follows:

• FSX pin is configured as an output pin.

• Handshake mode is disabled.

• Internal transmit clock is used.

• External receive clock is used.

• Fixed data rate mode is chosen when transmitting and receiving.

• Receive and transmit frame sync mode selected as standard mode, where each wordtransmitted or received has an associated sync pulse.

• CLKX and CLKR polarity are chosen as active high.

• DX and DR polarity are chosen as active high; FSX and FSR polarity are chosen as activehigh.

• Transmit and receive word lengths are 16 bits.

• Transmit and receive timers and interrupts are disabled.

• Transmit and receive sides are set to take out of reset mode.

3.2 FSX/DX/CLKX Port-Control Register

This 32-bit port-control register controls the function of the serial port FSX, DX, and CLKX pins.Each pin function is described by four bits as follows:

• Bit 0, FUNC: Function. General-purpose I/O pin if 0; serial-port pin if 1

• Bit 1, I/O: Input/output. General-purpose input pin if 0; general-purpose output pin if 1

• Bit 2, DATOUT: Data output to pin if selected as general-purpose output pin

• Bit 3, DATIN: Data input on pin if selected as general-purpose input pin

Therefore, bits [3:0] describe the use of the CLKX pin, bits [7:4] describe the use of the DX pin,and bits [11:8] describe the use of the FSX pin. The rest of the bits (bits [31:12]) are reservedand read as zero. See Figure 3.

SLAA111


Hence, the value of 0111h describes the transmit pins to be configured as serial-port pins.

FSX/DX/CLKX Port-Control Register

BIT 31–16 15–12 11 10 9 8 7 6 5 4 3 2 1 0

NAME FSXDATIN

FSXDATOUT

FSXI/O

FSXFUNC

DXDATIN

DXDATOUT

DXI/O

DXFUNC

CLKXDATIN

CLKXDATOUT

CLKXI/O

CLKXFUNC

TYPE X X R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W

DEFAULT 0 or 1 0 0 0 0 or 1 0 0 0 0 or 1 0 0 0


Figure 3. FSX/DX/CLKX Port-Control Register

3.3 FSR/DR/CLKR Port-Control Register

This 32-bit port-control register controls the function of the serial-port FSR, DR, and CLKR pins.Each pin function is described by four bits as follows:

• Bit 0, FUNC: Function. General-purpose I/O pin if 0; serial-port pin if 1

• Bit 1, I/O: Input/output. General-purpose input pin if 0; general-purpose output pin if 1

• Bit 2, DATOUT: Data output to pin if selected as general-purpose output pin

• Bit 3, DATIN: Data input on pin if selected as general-purpose input pin

Therefore, bits [3:0] describe the use of the CLKR pin, bits [7:4] describe the use of the DR pin,and bits [11:8] describe the use of the FSR pin. The rest of the bits (bits [31:12]) are reservedand read as zero. See figure 4.

Hence, the value of 0111h describes the receive pins to be configured as serial-port pins.

FSR/DR/CLKR Port-Control Register

BIT 31–16 15–12 11 10 9 8 7 6 5 4 3 2 1 0

NAME FSRDATIN

FSRDATOUT

FSRI/O

FSRFUNC

DRDATIN

DR DAT-OUT

DRI/O

DRFUNC

CLKRDATIN

CLKRDATOUT

CLKRI/O

CLKRFUNC

TYPE X X R R/W R/W R/W R R/W R/W R/W R R/W R/W R/W

DEFAULT 0 or 1 0 0 0 0 or 1 0 0 0 0 or 1 0 0 0


Figure 4. FSR/DR/CLKR Port-Control Register

3.4 Receive/Transmit Timer-Control Register

This 32-bit receive/transmit timer-control register contains the control bits for the timer module.At reset, all bits are set to zero. Bits [5:0] control the transmitter timer and bits [11:6] control thereceiver timer. Bits 4 and 10 are reserved bits and have no effect on the receive/transmittimer-control register. See Table 5 for the bit definitions.

SLAA111


Table 5. Receive/Transmit Timer-Control Register Bit Definition

BIT DESCRIPTION (Abbreviation) FUNCTION

0 Transmit timer counter restart (XGO) Go. Resets and starts transmit timer counter

1 Transmit counter hold signal (XHLD) Hold the counter. If 0, the counter is disabled and held in its current state. If 1, theinternal divide-by-two counter is also held so that the counter continues where it left off.

2 Transmit clock/pulse mode control (XC/P) If 1, the clock mode is chosen and outputs a 50% duty cycle. If 0, the pulse mode ischosen and output is active for one CLKOUT cycle during each timer period.

3 Transmit clock source (XCLKSRC) If 1, an internal clock with frequency equal to 1/2 the CLKOUT frequency is used toincrement the counter. If 0, you can use an external signal from the CLKX pin toincrement the counter.

5 Transmit timer status (XTSTAT) Indicates the status of the transmit timer.

6 Receive timer counter (RGO) Go. Resets and starts receive timer counter.

7 Receive counter hold signal (RHLD) Hold the counter. If 0, the counter is disabled and held in its current state. If 1, theinternal divide-by-two counter is also held so that the counter continues where it left off.

8 Receive clock/pulse mode control (RC/P) If 1, the clock mode is chosen and outputs a 50% duty cycle. If 0, the pulse mode ischosen and output is active for one CLKOUT cycle during each timer period.

9 Receive timer clock source (RCLKSRC) If 1, an internal clock with frequency equal to 1/2 the CLKOUT frequency is used toincrement the counter. If 0, you can use an external signal from the CLKR pin toincrement the counter.

11 Receive timer status (RSTAT) Indicates the status of the receive timer.

The physical structure of the receive/transmit timer-control register is shown in Figure 5.

RECEIVE/TRANSMIT TIMER-Control Register

BIT 31–16 15–12 11 10 9 8 7 6 5 4 3 2 1 0

NAME RSTAT RCLKSRC RC/P RHLD RGO XTAT XCLKSRC XC/P XHLD XGO

TYPE X X R X R/W R/W R R/W R X R/W R/W R/W R/W

DEFAULT 0 0 0 0 0 0 0 0 0 0


Figure 5. Receive/Transmit Timer-Control Register

Thus, the value of 01CF hex configures the serial port of the DSP to be as follows:

• R/X timer is not held, counter is zeroed and begins incrementing on the next rising edge ofthe timer input clock.

• The internal divide-by-two counter is also held so that the counter continues where it left off.

• Clock mode is chosen.

• Internal clock source is used for transmit clock (frequency is discussed later).

• External clock source is used for receive clock (CLKX is tied to CLKR).

3.5 Receive/Transmit Timer-Counter Register

This 32-bit receive/transmit timer-counter register (along with the receive/transmit timer-periodregister, see Section 3.6) specifies the frequency of the timer signaling. The counters arecleared to zero whenever they increment to the value of the receive/transmit timer-periodregister (see section 3.6), or upon reset. Bits [15:0] are the transmit timer counter, and bits[31:16] are the receive timer counter (see Figure 6).

SLAA111


31 16

15 0

Receive Timer Counter

Transmit Timer Counter

Figure 6. Receive/Transmit Timer-Counter Register

3.6 Receive/Transmit Timer-Period Register

This 32-bit receive/transmit timer-period register specifies the period of the timer and is clearedto zero upon reset. Bits [15:0] are the transmit timer period, and bits [31:16] are the receive timerperiod (see Figure 7).

31 16

15 0

Receive Timer Period

Transmit Timer Period

Figure 7. Receive/Transmit Timer-Period Register

3.7 Serial-Port Timing

Although the receive and transmit timers can be configured to be of different rates, it is always agood practice to synchronize both rates to avoid problems. The formula for calculating thefrequency of the serial port clock with an internally generated clock depends upon the operationmode of the serial port timers.

If the timer is configured for pulse-mode operation, then:

f(PULSE MODE) = f(TIMER CLOCK) / period register

If the timer is configured for clock-mode operation, then:

f(CLOCK MODE) = f(TIMER CLOCK) / (2 × period register)

Where:

f(TIMER CLOCK) = f(H1) / 2 ; maximum frequency for internally generated clock

f(TIMER CLOCK) < f(H1) / 2.6 ; maximum frequency for externally generated serial-port clock

f(H1) = f(SYSTEM CLOCK) / 2

3.8 Serial-Port Initialization/Reconfiguration

After defining the port operation, follow this procedure to initialize and configure or reconfigurethe serial port:

1. Halt the serial port by clearing XRESET (bit 26) and/or RRESET (bit 27) bit of the serialport global control register. Serial ports are halted on reset.

2. Configure the serial port via the global register (with XRESET = RRESET = 0) and the portcontrol registers. If necessary, configure the timer control (with XHLD = RHLD = 0), timercounter and timer period.

SLAA111


3. Start the serial-port operation by setting the XRESET and RRESET bits of the serial portglobal control register and the XHLD and RHLD bits of the serial port timer control register,if necessary.

Upon successful initialization and configuration of the serial port, data transmit and receiveshould be possible between the DSP and the data converters. Refer to the code examplesincluded in the appendix section of this application report.

3.9 Serial Port Operation

During the transmit operation, the CPU loads the transmit data into the data transmit register(DXR), the DXR then loads the word into the transmit-shift register (XSR), and the bits areshifted out. The word does not get loaded into the XSR until it is empty. Once the DXR is loadedinto the XSR, the XRDY status bit is set, which specifies that the buffer (DXR) is available toreceive the next word, thus providing a double buffering function. The rising edge of XRDYsignal sets the XINT0 bit in the interrupt flag (IF) register, provided that the transmit interruptenable (XINT) bit in the serial-port global control register and the CPU serial-port 0 transmitinterrupt enable (EXINT0) bit in the interrupt enable (IE) register are set.

During the receive operation, the CPU reads the received data from the data receive register(DRR), which is double-buffered as well. When the serial data (such as the ADC data) is input,the receive shift register (RSR) receives the data. When the specified number of bits are shiftedin, the DRR is loaded from RSR and the RRDY status bit is set, which specifies that there is newdata ready to be read from the DRR. If the DRR is not yet read and the RSR is full, the receiveris frozen. Any new data coming into the DR pin is ignored until the DRR is read. RSR does notwrite over the DRR, therefore DRR must be read to allow new data in the RSR to be transferredto the DRR. The rising edge of the RRDY signal sets the RINT0 bit in the interrupt flag (IF)register, provided that the receive interrupt enable (RINT) bit in the serial port global controlregister and the CPU serial port 0 receive interrupt enable (ERINT0) bit in the interrupt enable(IE) register are set.

4 The ADC

The TLV2541 is a high-performance, 12-bit, 140/200-kSPS-maximum-throughput, low-power,CMOS, analog-to-digital converter (ADC), with a fast conversion time of 3.5 µs. This ADCoperates from a single 2.7-V to 5.5-V supply. The architecture of this device is based upon asuccessive approximation register (SAR) utilizing a charge redistribution DAC. The samplingcapacitor acquires the signal on AIN during the sampling period. When the conversion processstarts, the SAR control logic and charge redistribution DAC are used to add and subtract fixedamounts of charge from the sampling capacitor to bring the comparator into a balancedcondition. When the comparator is balanced, the conversion is complete and the ADC outputcode is generated.

The onboard oscillator for this ADC has a minimum frequency of 4 MHz. The conversionprocess requires 14 conversion clocks to complete the conversion, which leads to a 3.5 µsconversion time.

The functional block diagram of the TLV2541 is shown in Figure 8.

SLAA111


SDO

VREF

VDD

S/HLOW POWER

12-BITSAR ADC

OSCConversion

Clock

CONTROLLOGIC

AIN

SCLKCSFS

GND

Figure 8. TLV2541 Functional Block Diagram

4.1 TLV2541 Pin Function

The TLV2541 ADC has only one analog signal input channel, and provides at the most afour-wire interface for the DSP, namely: SCLK, SDO, CS and FS. The pin functions aredescribed as follows:

AIN Analog input channelThis terminal receives the analog signal to be digitized.

VREF Voltage referenceVREF terminal receives the external reference voltage that defines the analogconversion range and specifies the maximum input signal level at the AIN channel.

SCLK Serial data clock

The SCLK pin receives the serial clock provided by the host processor, and canreceive up to a maximum of 20 MHz for the supply voltage range specified.

SDO Serial data output

The 3-state SDO pin is the serial data output for the ADC conversion result. The SDOis kept in the high-impedance state until the CS falling edge or FS rising edge,whichever occurs first.

SLAA111


CS Chip select

The function of this pin may vary between chip select and frame sync depending onthe system application configuration requirements. If the DSP serial port is dedicatedto interface with the TLV2541 ADC alone, then the CS pin can either be tied to ground(typical configuration) or can function as frame synchronization signal input. Thiseliminates a need for the DSP to use another I/O pin for selecting the device. If theDSP serial port is shared with another device, such as the DAC, then the CS pinfunctions as a chip select signal and should be connected to the system addressdecoder.

FS Frame synchronization

The FS pin is used to indicate the start of a serial data frame. If this pin is not going tobe used it should be tied to VDD through a pullup resistor.

For the purpose of this report, the XF0 pin of the DSP is used (where applicable) to drive boththe CS pin of the ADC and the CS pin of the DAC, with some additional gating on the FSX pinrequired to isolate the two devices from each other when using the DSP serial port. The use ofthe XF0 pin is the simplest method to implement the device selection because it is ageneral-purpose I/O that is easy to program. The XF0 signal pin is asynchronous to serial porttransfers, so you have to be aware when to select and deselect the devices.

4.2 Hardware Considerations

The TLV2541 ADC is easy to use and fairly simple to implement. If this is the only device withwhich the DSP interfaces through the serial port, then the interface between the DSP and theADC can be direct, without any logic gates involved. If there are any other devices that share theDSP serial port, then external logic is required. The external logic can range in complexity fromthe use of a single inverter up to a complex logic gate combination. The implementation ofmultiple-gate logic is discussed in Section 5, where the use of the TLV5618A DAC is described.

The possible hardware configurations that can be considered for the ADC are shown in Figures 9, 10, and 13.

TLV2541CLKR0

CLKX0

DX0

DR0

XF0FSX0

FSR0

INT3

8

5

64

2

3

7

1

96

116

110

114

111112

108

107

TMS320C31

VDD

0.1 µF 10 µF

Analog Input AIN

VREF

GND

VDDSCLK

SDO

CS

FS

Reference Voltage Input

Not Used

Not Used

Not Used

Figure 9. Typical Hardware Configuration for a Glueless Logic Connection (Dedicated Device)

SLAA111


Figure 9 shows the typical hardware configuration if the ADC is the only device connected to theDSP serial port. The ADC device is always selected and the rising edge of FS removes the SDOpin from the high-impedance state within a maximum setup time. The MSB is presented to theSDO pin after the rising edge of FS. The falling edge of FS is the start of the ADC cycle and theoutput data is valid on the first falling edge of SCLK after the falling edge of FS. The output datachanges on the rising edge of SCLK. The cycle is completed when a falling edge transition ofSCLK occurs while FS is high.

TLV2541CLKR0

CLKX0

DX0

DR0

XF0FSX0

FSR0

INT3

8

5

64

2

3

1

7

96

116

110

114

111112

108

107

TMS320C31

VDD

0.1 µF 10 µF

Analog Input AIN

VREF

GND

VDDSCLK

SDOCS

FS


Not Used

Not Used

Not Used

RP

Figure 10. Alternative Hardware Configuration for a Glueless Logic Connection(Dedicated Device)

Figure 10 shows an alternative hardware configuration if the ADC is the only device connectedto the DSP serial port. The FS pin now is inactive and the CS pin functions as frame sync input.The falling edge of CS is the start of the ADC cycle and the MSB is presented to the SDO pinafter a specified delay time. The output data is valid on the first falling edge of SCLK after CS islow, and the output data changes on the rising edge of SCLK. One falling edge transition onSCLK is needed after CS is high to complete the cycle.

Figures 9 and 10 show the two possible glueless logic interfaces between the ADC and the DSP.The TLV2541 ADC has no user-configuration register onboard. Therefore, configuration is notrequired, and a write to the ADC device is not possible. For this reason, DX pin is not used. TheXF pin is not used in the typical or alternative configuration because the CS pin either is tied toground or is used as the frame sync input signal. This device does not support the use of aninterrupt to notify the host processor when conversion process is completed. Therefore, the INT3pin of the DSP is not used, so enough time for conversion should be allowed before initiatinganother cycle. This is to ensure that the current conversion process is not terminatedprematurely.

Figure 11 and Figure 12 illustrate the timing diagram for the start of a cycle when FS or CS isused as control, respectively. Refer to the data sheet (literature number SLAS245) for moredetailed information.

SLAA111


SCLK

1

CS

FS

SDO

2

OD10OD11 OD9 OD8 OD7

3 4 5 6 12 13 14 15 16 17 18 nth

OD6 OD0 X X X XÎÎÎÎ

t(sample)

t(convert)

td(SCLK17H-SDOZ)

th(EOC-CSH)

Don’t Care

Valid Conversion Data

td(SCLKH-SDOV)

td(CSL-FSH)

td(CSL-SDOV)

Notes:1. OD11 – OD0 = Output Data2. X = Don’t Care

Figure 11. Timing Diagram (CS = 0, FS = Frame Sync Signal)

td(CSL-SDOV)

SCLK

1

CS

SDO

2

OD10 OD9 OD8 OD7

3 4 5 6 12 13 14 15 16 17 18 nth

OD6 OD0 X X X XÎÎÎÎÎÎ

t(sample)

t(convert)

td(SCLK17H-SDOZ)

th(EOC-CSH)

Don’t Care

Valid Data From Previous Conversion Cycle

OD11

FS


Figure 12. Timing Diagram (CS = Frame Sync Signal, FS = 1)

SLAA111


TLV2541CLKR0

CLKX0

DX0

DR0

XF0FSX0

FSR0

INT3

8

5

64

2

3 7

1 96

116

110

114

111112

108

107

TMS320C31

TLV5636

76

8

5

23

4

1

VDD

0.1 µF 10 µF

Analog Input AIN

VREF

GND

VDDSCLK

SDOCS

FS


Not Used

FS

DIN

CS

SCLKVDD

0.1 µF 10 µF

Analog Output

Reference Voltage Input VREFVDDGND

OUT

Figure 13. Hardware Configuration for Devices Sharing the DSP Serial Port

Figure 13 shows the hardware configuration for the two data converter devices sharing the sameserial port of the DSP. The simple method of using an inverter is implemented to select only onedevice at a time when the serial port is accessed. When XF is low, the ADC is selected and byvirtue of the inverter, the DAC is disabled and vice versa. Since there are two devices sharingthe DSP serial port, the ADC device CS and FS pins function as chip select and frame syncsignals, respectively. The timing diagram for this is illustrated in Figure 14.

SCLK

1

CS

FS

SDO

2

OD10OD11 OD9 OD8 OD7

3 4 5 6 12 13 14 15 16 17 18 nth

OD6 OD0 X X X XÎÎÎÎÎÎ

t(sample)

t(convert)

td(SCLK17H-SDOZ)

th(EOC-CSH)

Don’t Care

Valid Data From Previous Conversion Cycle

td(CSL-SDOV)


Figure 14. Timing Diagram (CS = Chip Select, FS = Frame Sync)

SLAA111


5 The DAC

The TLV5618A is a dual 12-bit voltage output DAC, which has a flexible 3-wire serial interfaceand is programmed with a 16-bit serial string containing 4 control and 12 data bits. This device isbased on a resistor-string architecture and is designed for a single supply operation from 2.7 Vto 5.5 V. The 4-bit control word (D[15:12]) is the most significant nibble of the 16-bit serial stringand makes up the DAC data format. The serial data is shifted in on the falling edges of SCLK,bit-by-bit starting with the MSB, as soon as the falling edge of the DAC CS is issued. After 16bits have been transferred, the content of the internal shift register is moved to the target latches(DAC A, DAC B, BUFFER, CONTROL), depending on the control bits within the data wordreceived.

The DAC output voltage (full scale determined by the reference) is given by:

2 REF � CODE0x1000

[V]

where REF is the reference voltage and CODE is the digital input value in the range of 0x000 to0xFFF. A power-on reset initially puts the internal latches to a defined state (all bits zero).

The DAC can operate at a maximum serial clock frequency of 20 MHz, and the maximumupdate rate is given by:

f(UPDATEMAX) �1

16 �tWHMIN � tWLMIN�� 1.25 MHz

where tWHMIN is the minimum high period and tWLMIN is the minimum low period of SCLK.

The functional block diagram of the TLV5618A DAC is shown in Figure 15.

SLAA111


SerialInterface

andControl

SCLK

DIN

CS

OUTAx2

Power andSpeed Control

2

12-BitDAC ALatch

REF AGND VDD

1212

OUTBx2

Buffer

12

Power-OnReset

12-BitDAC BLatch

1212

Figure 15. Functional Block Diagram of the TLV5618A

5.1 The DAC Pin Function

The TLV5618A DAC pin functions are described below:

DIN Digital serial data input channelThis pin receives the digital serial data.

REF Analog reference voltage inputThe REF pin receives the external reference voltage that defines the analogconversion range. Due to the ×2 output buffer, a reference input voltage,(VDD – 0.4V) / 2, causes clipping of the transfer function.

SCLK Digital serial data clock

The SCLK pin receives the serial clock provided by the host processor, and canreceive a maximum of 20 MHz for the supply voltage range specified.

OUTA DAC A analog voltage output

This pin outputs the analog voltage of DAC A.

SLAA111


OUTB DAC B analog voltage output

This pin outputs the analog voltage of DAC B.

CS Chip select

This pin is used to enable and disable the DAC and is active low.

5.2 The DAC Data Format

The data collected from the ADC is presented to the DAC by the DSP. A slight adjustment to theADC data must be done before presenting it to the DAC. Since the data received from the ADChas only 12 bits of usable data, starting from the MSB, the DSP has to perform a shift of 4 bitpositions to the right. The 4-bit control word for the DAC is then padded to the most significantnibble to make a good 16-bit string of data for the DAC. The DSP data manipulation flow, whichformats the ADC data to fit the DAC data format, is described in Figure 16.

Bit 11

16-bit string received from ADC with 12 bits of good data

GarbageBit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Garbage Garbage Garbage

MSB LSB

Bit 11

After DSP execution of a 4-bit right shift

Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MSB LSB

Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

MSB LSB

GarbageGarbageGarbageGarbage

Bit 12Bit 13Bit 14Bit 15

4-bit control word for DAC commandpadded after shift execution

12-bit data of the ADC shifted to the right by 4 bit positions

4-bit Control Word

Figure 16. DSP Data Manipulation of ADC Data for DAC Data Format

The DAC 4-bit control word, as shown in the 4 MSB of figure 17, is described as follows:

• R0 and R1 select all possible combination of register-select bits (see Table 6)

• PWR is to control the DAC to be in power down or normal operation

• SPD is to control the speed mode of the DAC SPD = 1 → fast mode SPD = 0 → slow modePWR = 1 → power down PWR = 0 → normal operation

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4

R1 SPD PWR R0 MSB

D3 D1D2 D0

12 Data Bits LSB

Figure 17. DAC Data Format

SLAA111


Table 6. Register-Select Bits

R1 R0 REGISTER

0 0 Write data to DAC B and BUFFER

0 1 Write data to BUFFER

1 0 Write data to DAC A and update DAC B with BUFFER content

1 1 Reserved

5.3 DAC Timing Requirement

The DAC timing requirement is described in Figure 18.

See Notes

SCLK

1

CS

DIN

2

D12 D11 D10 D9

3 4 5 6 10 11 12 13 14 15 16

D8 D6 D5 D4 D3 D2

10 ns Min

Notes:1. 10 ns Minimum for C and I Suffixes2. 8 ns Minimum for Q and M Suffixes

7 8 9

D7D15 D13D14 D1 D0

10 ns Min

5 ns Min

25 ns Min

25 ns Min

Figure 18. DAC Timing Diagram

6 The System

A simple data acquisition system is realized with the use of the TLV2541 ADC, TLV5618A DAC,and TMS320C31 DSP. The task of interfacing these data converter devices to the DSP is fairlysimple, and is described in Figure 19.

SLAA111


TLV2541CLKR0

CLKX0

DX0

DR0

XF0FSX0

FSR0

INT3

8

5

64

2

3 7

1 96

116

110

114

111112

108

107

TMS320C31

TLV5618A

76

8

5

23

4

1

VDD

0.1 µF 10 µF

Analog Input AIN

VREF

GND

VDDSCLK

SDOCS

FS


Not Used

DIN

REF

CS

SCLKVDD

0.1 µF 10 µF

DAC A Analog Output

DAC B Analog Output OUTB

VDDAGND

OUTA

VDD – 0.4

2[V]

ADC_SDOADC_CS

ADC_FS

DAC_CS

DAC_DIN

Figure 19. Hardware Configuration

As discussed in Section 4.2, Hardware Considerations, Figure 19 shows the use of multiple-gatelogic to control the selection of the data converters sharing the same serial port of the DSP. TheDAC write cycle is started when the device detects a falling-edge transition on its CS pin. TheMSB is expected by the DAC after the falling edge of CS; therefore, the DSP must send the datainstantaneously when a write to the DAC is performed. Since the DSP sends a frame syncsignal for every word transfer, the DSP must be able to discern which device it wants tocommunicate with. Gating the required signals correctly, as shown in Figure 19, achievescomplete isolation of the devices and ensures correct data transfer to each device.

6.1 Operation and Timing

Figure 20 shows a typical timing diagram of the ADC and DAC data transfer through and fromthe DSP respectively. The low time of ADC_CS indicates that the ADC is active and the hightime indicates its inactivity. On the other hand, the low time of DAC_CS (high time of ADC_CS)indicates the DAC active state. The specific assertion between the DAC and the ADC is madepossible by the logic gates added in the hardware for sharing the DSP serial port.

SLAA111


1 2 3 4 5 12 13 14 15 16 1 4 5 16

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

1 2 3 4 5 11 12 13 14 15 16

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SCLK

XF

FSX

ADC_FS

ADC_SDO

DAC_DIN

ADC_CS

DAC_CS

nth nth

OD

10

ADC Sample and Convert(1st Cycle)

OD

11

OD

9

OD

8

OD

7

OD

0

ADC Read Cycle

1st Data Read is Garbage

t(sample)

t(convert)

Not a Valid DAC Write Access

ÎÎÎÎÎÎ

OD

10

OD

11

OD

9

OD

8

OD

7

OD

1

OD

0

Valid Data Read FromPrevious Cycle

ÎÎÎÎÎÎÎÎ

t(sample)

t(convert)

ADC Read Cycle

DAC Write(1st Cycle)

ID

15

ID

12

ID

0

ID

11

CMD

DATA

ADC Sample and Convert(2nd Cycle)

Figure 20. ADC and DAC Timing Diagram

The process flow of the timing diagram shown in figure 20 is as follows:

1. The DSP serial port is configured and provides a continuous serial clock for serial datatransmission (CLKX to CLKR and SCLK).

2. The DSP selects the ADC by asserting ADC_CS (CS pin) by driving the XF output pin ofthe DSP low. This pin has to be asserted for a minimum of 16 SCLKs, starting from thefalling edge of FS signal (↓FS), plus 3.5 µs conversion time (tCONVERT). Simultaneously,the DAC device is effectively deselected while the ADC is active.

3. The DSP initializes data transfer to the ADC by executing a dummy write to generate thetransmit frame sync pulse, which is gated with XF, to the ADC_FS (FS pin) input. Althougha write to the ADC device is not valid, a write command must be executed to start theADC conversion cycle. When the write command is executed a subsequent readcommand should follow to read the conversion data.

4. The DSP manipulates the ADC data read, which is the result from the previous conversioncycle, to fit the DAC data format, as discussed in section 5.2.

5. The DSP initializes data transfer to the DAC by issuing the transmit frame sync pulse. Thelow period of FSX signal is gated with the high period of the XF signal of the DSP toensure that the MSB of the data written to the DAC is not lost. Therefore, the DAC iseffectively selected until the write cycle to the DAC is completely done.

SLAA111


6. The process is repeated starting from step 2.

A simple illustration of the complete data acquisition system is shown in figure 21. The functionaloperation of the illustration is performed using the code provided in appendix A of this report.

A/D D/ADSP

Figure 21. Illustration of the Complete Data Acquisition System

7 Summary

This report discusses the features of the TLV2541 ADC, TLV5618A DAC, and the TMS320C31DSP serial port. In addition, some hardware considerations are included for user reference.Although there are many different possible hardware interface solutions, this report covers onlya few of the simplest hardware interfaces. Section 6 shows the hardware configuration and theprocess flow between the DSP and the data converter devices. The process is fairly simple,because the ADC does not require any configuration write cycles. The system throughput delayis only hindered by the rate at which the DSP can read data from the ADC, process the data tofit the DAC data format, and write the data to the DAC. This reading, processing, and writing ofdata is performed by execution of the assembly code included in Appendix A. Once started, theassembly code will execute continuously until the user terminates the program.

8 References

1. TMS320C3x DSP User’s Guide (SPRU031)

2. TMS320C3x Starter Kit User’s Guide (SPRU163)

3. TMS320C3X/C4X Assembly Language Tools User’s Guide (SPRU035)

4. TLV2541 ADC data sheet (SLAS245)

5. TLV5618A DAC data sheet (SLAS230)

6. Multi-Converter EVM User’s Guide (SLAU047)

7. Code Composer Studio User’s Guide (SPRU328)

SLAA111


Appendix A TLV2541.ASM;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––; TLV2541.asm; Jojo Parguian; TMS320C31 DSP Applications; Copyright 2000; Texas Instruments Incorporated;; This example exercise will assert ADC to sample and convert an; analog input signal through Ain0, read the data into the DSP register; and manipulate the data to fit the DAC data format requirement. The; data is then shifted out through the DSP transmit data register into; the DAC, and the DAC transforms the digitized input into its original; analog signal.; DEVICE Used: TLV2541(ADC) and TLV5618A(DAC); For EVM0309;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––; LEGAL DISCLAIMER; The source code programs included herein contain Texas Instruments copyrighted; material and are protected by copyright laws and international copyright; treaties, as well as other intellectual property laws. Texas Instruments hereby; grants a copyright clearance to use these programs solely with or in conjunction; with Texas Instruments products. Texas Instruments reserves all rights not; expressly granted herein. TEXAS INSTRUMENTS MAKES NO WARRANTIES OR; REPRESENTATIONS THAT THE SOURCE CODE PROGRAMS INCLUDED HEREIN ARE MERCHANTABLE OR; FIT FOR ANY PARTICULAR PURPOSE.;–––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––;Serial Port 0 registers

.global BEGINsport .set 808040h ; Serial Port 0 global control registerxpctrl .set 808042h ; FSX/DX/CLKX port controlrpctrl .set 808043h ; FSR/DR/CLKR port controlrxtctrl .set 808044h ; r/x timer control registerrxtcnt .set 808045h ; r/x timer counter registerrxtprd .set 808046h ; r/x period registerxdata .set 808048h ; Data transmit registerrdata .set 80804Ch ; Data receive registert0_GO .set 001cfh ; Timer configuration to GO .datasp0_cfg .word 0c140044hs0_rxcntr .word 00000000hs0_rxprd .word 00000000h ; 12.5MHz CLKXDP_reg .word 00800000h****************************************************** Main Program*****************************************************

.textBEGIN ldp DP_reg

ldi 111h,r0 ; Setup Serial Port to be:sti r0,@xpctrl ; FSX is a serial port pin

; DX is a serial port pin; CLKX is a serial port pin

sti r0,@rpctrl ; FSR is a serial port pin

SLAA111


; DR is a serial port pin; CLKR is a serial port pin

ldi @s0_rxcntr,r0 ; counter valuesti r0,@rxtcnt ; Load counter valueldi @s0_rxprd,r0 ; period valuesti r0,@rxtprd ; Load the period valueldi t0_GO,r0 ; start timer0 configsti r0,@rxtctrl ; Start the counterldi @sp0_cfg,r0 ; 0x0c140044 config for SP0 GCRsti r0,@sport ; configure sp0 gcrldi 0,r0

************************************************************************* DAC Write to zero double buffer************************************************************************

ldi 5000h,r6 ; DAC command to zero bufferldi 6,iof ; select DACsti r6,@xdata ; write to DAC Ch B and Bufferldi 9,r1

wait0 subi 1,r1bnz wait0

************************************************************************* ADC Read and Convert Cycle************************************************************************loop ldi 2,iof ; Assert CS* to select ADC

sti r5,@xdata ; Generate a dummy write for FS pulse to occurldi @rdata,r4 ; Read ADC data now

************************************************************************* DSP manipulation of ADC data to fit DAC data format************************************************************************

ldi r4,r5lsh –4,r5 ; fix data to fit DAC data formatldi 5000h,r6 ; DAC command to store to bufferor r6,r5 ; with fast settling time (2.5us)ldi 8,r1 ; allow current ADC conversion to finish

delay0 subi 1,r1bnz delay0

************************************************************************* DAC Write to store to double buffer************************************************************************

ldi 6,iof ; Select DACsti r5,@xdata ; write to DAC double Bufferldi 9,r1


************************************************************************* DAC write to output channel************************************************************************

ldi 0c000h,r7 ; for DAC command to output on A and Bor r7,r5 ; with fast settling time (2.5us)sti r5,@xdata ; write to DAC Ch A & update DAC Ch B w/ Bufferldi 9,r1 ;


SLAA111


b loop ; repeat process.end

************************************************************************** EOF*************************************************************************

SLAA111


Appendix B Program and Data Memory Mapping/********************************************************************//* Generic C31 linker command file for all routine files included in*//* this application report. *//********************************************************************/MEMORY{ RAM0: org = 0x809800 len = 0x400 /* RAM BLOCK 0 */ RAM1: org = 0x809C00 len = 0x3C1 /* RAM BLOCK 1 */ VECS: org = 0x809fc4 len = 0x010 /* INTERRUPT VECTORS */}SECTIONS{ .text: > RAM0 /* CODE */ .data: > RAM1 /* DATA */ ”int3_isr” > RAM0 /* ISR */ ”vectors” > VECS /* Interrupt Vectors */}

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinueany product or service without notice, and advise customers to obtain the latest version of relevant informationto verify, before placing orders, that information being relied on is current and complete. All products are soldsubject to the terms and conditions of sale supplied at the time of order acknowledgment, including thosepertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extentTI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarilyperformed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.

In order to minimize risks associated with the customer’s applications, adequate design and operatingsafeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or representthat any license, either express or implied, is granted under any patent right, copyright, mask work right, or otherintellectual property right of TI covering or relating to any combination, machine, or process in which suchsemiconductor products or services might be or are used. TI’s publication of information regarding any thirdparty’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright 2000, Texas Instruments Incorporated

Documents

Interfacing the TLV2541 ADC and the TLV5618A DAC to the