Intel FPGA Low Latency Ethernet 10G MAC Design Example ... · 1 Quick Start Guide ... Intel FPGA Low Latency Ethernet 10G MAC Design Example User Guide for Intel Stratix 10 Devices

Intel FPGA Low Latency Ethernet10G MAC Design Example User Guidefor Intel Stratix 10 Devices

Updated for Intel® Quartus® Prime Design Suite: 17.1

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Contents

1 Quick Start Guide.............................................................................................................51.1 Directory Structure................................................................................................. 61.2 Generating the Design.............................................................................................8

1.2.1 Procedure..................................................................................................81.2.2 Design Example Parameters.........................................................................9

1.3 Compiling and Simulating the Design.......................................................................101.3.1 Procedure................................................................................................ 101.3.2 Testbench................................................................................................ 11

1.4 Compiling and Testing the Design in Hardware..........................................................121.4.1 Procedure................................................................................................ 121.4.2 Hardware Setup........................................................................................13

2 10GBASE-R Ethernet Design Example for Intel Stratix 10 Devices................................. 142.1 Features.............................................................................................................. 142.2 Hardware and Software Requirements..................................................................... 142.3 Functional Description........................................................................................... 15

2.3.1 Design Components.................................................................................. 152.3.2 Clocking and Reset Scheme........................................................................16

2.4 Simulation........................................................................................................... 162.5 Hardware Testing..................................................................................................16

2.5.1 Test Cases............................................................................................... 172.5.2 Signal Tap Debug Signals........................................................................... 18

2.6 Interface Signals...................................................................................................202.7 Configuration Registers..........................................................................................20

3 10M/100M/1G/2.5G/10G Ethernet Design Example for Intel Stratix 10 Devices...........223.1 Features.............................................................................................................. 223.2 Hardware and Software Requirements..................................................................... 223.3 Functional Description........................................................................................... 22

3.3.1 Design Components.................................................................................. 233.3.2 Clocking Scheme...................................................................................... 243.3.3 Reset Scheme.......................................................................................... 24


3.5.1 Test Procedure..........................................................................................263.6 Interface Signals...................................................................................................293.7 Configuration Registers..........................................................................................29

4 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10Devices....................................................................................................................314.1 Features.............................................................................................................. 314.2 Hardware and Software Requirements..................................................................... 314.3 Functional Description........................................................................................... 32


4.4 Simulation........................................................................................................... 354.4.1 Test Case—Design Example with the IEEE 1588v2 Feature..............................35

Contents

Intel FPGA Low Latency Ethernet 10G MAC Design Example User Guide for Intel Stratix 10 Devices2

4.5 Hardware Testing..................................................................................................364.5.1 Test Procedure..........................................................................................36


5 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix10 Devices............................................................................................................... 415.1 Features.............................................................................................................. 415.2 Hardware and Software Requirements..................................................................... 415.3 Functional Description........................................................................................... 41


5.4 Simulation........................................................................................................... 455.4.1 Test Case—Design Example with the IEEE 1588v2 Feature..............................45

5.5 Hardware Testing..................................................................................................465.5.1 Changing to SFP+ Setting.......................................................................... 475.5.2 Test Procedure..........................................................................................47


6 10G USXGMII Ethernet Design Example for Intel Stratix 10 Devices..............................526.1 Features.............................................................................................................. 526.2 Hardware and Software Requirements..................................................................... 526.3 Functional Description........................................................................................... 52



6.5.1 Test Procedure..........................................................................................566.6 Interface Signals...................................................................................................586.7 Configuration Registers..........................................................................................59

7 Interface Signals Description.........................................................................................607.1 Clock and Reset Interface Signals........................................................................... 607.2 Avalon-MM Interface Signals.................................................................................. 607.3 Avalon-ST Interface Signals....................................................................................627.4 PHY Interface Signals............................................................................................ 647.5 Status Interface....................................................................................................647.6 IEEE 1588v2 Timestamp Interface Signals................................................................657.7 Packet Classifier Interface Signals........................................................................... 667.8 ToD Interface Signals............................................................................................ 67

8 Configuration Registers Description...............................................................................688.1 Register Access.................................................................................................... 688.2 Low Latency Ethernet 10G MAC.............................................................................. 688.3 PHY.................................................................................................................... 72

8.3.1 Register Map............................................................................................ 728.3.2 Register Definitions................................................................................... 73

8.4 Transceiver Reconfiguration....................................................................................788.5 TOD....................................................................................................................78

Contents


9 Document Revision History for Intel FPGA Low Latency Ethernet 10G MAC DesignExample User Guide for Intel Stratix 10 Devices..................................................... 80

Contents


1 Quick Start GuideThe Intel® FPGA Low Latency 10G Ethernet (LL 10GbE) MAC IP core for Intel Stratix®

10 provides the capability of generating design examples for selected configurations.

Figure 1. Development Stages for the Design Example

DesignExample

Generation

Compilation(Simulator)

FunctionalSimulation

Compilation(Quartus Prime)

HardwareTesting

Related Links

• 10GBASE-R Ethernet Design Example for Intel Stratix 10 Devices on page 14Provides details for the 10GBASE-R Ethernet design example.

• 10M/100M/1G/2.5G/10G Ethernet Design Example for Intel Stratix 10 Devices onpage 22

Provides details for the 10M/100M/1G/2.5G/10G Ethernet design example.

• 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10Devices on page 31

Provides details for the 1G/2.5G Ethernet design example.

• 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix10 Devices on page 41

Provides details for the 1G/2.5G/10G Ethernet design example with IEEE1588v2 feature.

• 10G USXGMII Ethernet Design Example for Intel Stratix 10 Devices on page 52Provides details for the 10G USXGMII Ethernet design example.

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Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartusand Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or othercountries. Intel warrants performance of its FPGA and semiconductor products to current specifications inaccordance with Intel's standard warranty, but reserves the right to make changes to any products and servicesat any time without notice. Intel assumes no responsibility or liability arising out of the application or use of anyinformation, product, or service described herein except as expressly agreed to in writing by Intel. Intelcustomers are advised to obtain the latest version of device specifications before relying on any publishedinformation and before placing orders for products or services.*Other names and brands may be claimed as the property of others.

ISO9001:2008Registered

http://www.altera.com/support/devices/reliability/certifications/rel-certifications.html



1.1 Directory Structure

Figure 2. Directory Structure for the Design Example

<Design Example>

rtl

altera_eth_multi_channel.sv

altera_eth_channel.sv

<Design Component>

<Design Component>

altera_eth_top.svaltera_eth_top.sdcaltera_eth_top.sof

altera_eth_top.qpfaltera_eth_top.qsfsimulation

models

hwtesting

system_console

output_files

ed_sim

cadence

mentor

synopsys

vcs

Table 1. Directory and File Description

Directory/File Description

altera_eth_top.qpf Intel Quartus® Prime Pro Edition project file.

altera_eth_top.qsf Intel Quartus Prime Pro Edition settings file.

altera_eth_top.sv Design example top-level HDL.

altera_eth_top.sdc Synopsys Design Constraints (SDC) file.

rtl The folder that contains the design example synthesizable components.

rtl/altera_eth_10g_mac_base_r.sv

rtl/altera_10g_mac_base_r_wrap.v

Design example DUT top-level files for 10GBASE-R ethernet design example.

rtl/altera_mge_rd.sv

rtl/altera_mge_channel.v

Design example DUT top-level files for the following ethernet design examples:• 1G/2.5G with 1588v2 feature• 1G/2.5G/10G

rtl/altera_eth_channel.v

rtl/altera_eth_multi_channel.sv

Design example DUT top-level files for the following ethernet design examples:• 10M/100M/1G/10G• 1G/10G

rtl/altera_eth_channel_1588.v

rtl/altera_eth_multi_channel_1588.sv

Design example DUT top-level files for the following ethernet design examples:• 10M/100M/1G/10G with with 1588v2 feature• 1G/10G with 1588v2 feature

rtl/altera_mge_multi_channel.sv

rtl/altera_mge_channel.v

Design example DUT top-level files for 10G USXGMII ethernet design example.

rtl/<Design Component> The folder for each synthesizable component including Platform Designergenerated IPs, such as LL10GbE MAC, PHY, and FIFO.

simulation/ed_sim/models The folder that contains the testbench files.

simulation/ed_sim/cadence

simulation/ed_sim/mentor

The folder that contains the simulation script. It also serves as a working area forthe simulator.

continued...

1 Quick Start Guide

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Directory/File Description

simulation/ed_sim/synopsys/vcs

hwtesting/system_console The folder that contains system console scripts for hardware testing.

output_files The folder that contains Intel Quartus Prime Pro Edition output files includingIntel Quartus Prime Pro Edition compilation reports and design programing file(.sof file).

1 Quick Start Guide

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1.2 Generating the Design

1.2.1 Procedure

You can generate the design example from the IP Parameter Editor.

Start ParameterEditor

Specify IP Variationand Select Device

SelectDesign Parameters

InitiateDesign Generation

Specify Example Design

Figure 3. Example Design Tab

1. Select Tools ➤ IP Catalog to open the IP Catalog and select Low LatencyEthernet 10G MAC.The IP parameter editor appears.

2. Specify a top-level name and the folder for your custom IP variation, and thetarget device. Click OK.

3. To generate a design example, select a design example preset from the Presetslibrary and click Apply. When you select a design, the system automaticallypopulates the IP parameters for the design.

The Parameter Editor automatically sets the parameters required to generate thedesign example. Do not change the preset parameters in the IP tab.

4. Specify the parameters in the Example Design tab.

5. Click the Generate Example Design button.

The software generates all design files in sub-directories. You require these files to runsimulation, compilation, and hardware testing.

Related Links

Directory Structure on page 6Provides more information about the generated design example directories andfiles.

1 Quick Start Guide

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1.2.2 Design Example Parameters

Table 2. Parameters in the Example Design Tab

Parameter Description

Select Design Available example designs for the IP parameter settings. When youselect an example design from the Preset library, this field shows theselected design.

Example Design Files for Simulation orSynthesis

The files to generate for the different development phase.• Simulation—generates the necessary files for simulating the example

design.• Synthesis—generates the synthesis files. Use these files to compile

the design in the Intel Quartus Prime Pro Edition software forhardware testing and perform static timing analysis.

Generate File Format The format of the RTL files for simulation—Verilog or VHDL.

Select Board Supported hardware for design implementation. When you select anIntel FPGA development board, the Target Device is the one thatmatches the device on the Development Kit.If this menu is grayed out, there is no supported board for the optionsthat you select.Intel Stratix 10 H-Tile GX Transceiver Signal IntegrityDevelopment Kit: This option allows you to test the design example onselected Intel FPGA IP development kit. This selection automaticallyselects the Target Device to match the device on the Intel FPGA IPdevelopment kit. If your board revision has a different device grade, youcan change the target device.Custom Development Kit: This option allows you to test the designexample on a third party development kit with Intel FPGA IP device, acustom designed board with Intel FPGA IP device, or a standard IntelFPGA IP development kit not available for selection. You can also select acustom device for the custom development kit.No Development Kit: This option excludes the hardware aspects forthe design example.

Change Target Device Select this parameter to display and select all devices for the Intel FPGAIP development kit.

Specify Number of Channels The number of Ethernet channels.

Analog Voltage VCCR_GXB and VCCT_GXB supply voltage for the Transceiver.

Enable ADME support Turn on this option to enable Transceiver ADME feature.

1 Quick Start Guide

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1.3 Compiling and Simulating the Design

1.3.1 Procedure

You can compile and simulate the design by running a simulation script from thecommand prompt.

Change to Testbench Directory

Run<Simulation Script>

AnalyzeResults

1. At the command prompt, change the working directory to <Example Design>\simulation\ed_sim\<Simulator>.

2. Run the simulation script for the simulator of your choice.

Simulator Working Directory Command

Modelsim* <Example Design>/simulation/ed_sim/mentor vsim -c -do tb_run.tcl

VCS* <Example Design>/simulation/ed_sim/synopsys/vcs

sh tb_run.sh

NCSim* <Example Design>/simulation/ed_sim/cadence sh tb_run.sh

A successful simulation ends with the following message:

Simulation stopped due to successful completion! Simulation passed.

After successful completion, you can analyze the results.

1 Quick Start Guide

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1.3.2 Testbench

Figure 4. Block Diagram of the Testbench

Avalon-MMControlRegister

Avalon-STTransmit

FrameGenerator

Avalon-STReceiveFrame

Monitor

EthernetPacket

Monitor

avalon_bfm_wrapper.sv

Avalon Driver

Channel 0

Channel 1

Ordinary Clock

EthernetPacket

Monitor

Loopbackon Serial

DUT

TX data

RX data

Testbench

Avalon-MM

Channel n-1

Channel n

.

.

.

Table 3. Testbench Components

Component Description

Device under test (DUT) The design example.

Avalon driver Consists of Avalon-ST master bus functional models (BFMs). This driverforms the TX and RX paths. The driver also provides access to theAvalon-MM interface of the DUT.

Ethernet packet monitors Monitor TX and RX datapaths, and display the frames in the simulatorconsole.

1 Quick Start Guide

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1.4 Compiling and Testing the Design in Hardware

1.4.1 Procedure

You can compile and test the design in the supported Intel FPGA development kit.

Compile Designin Quartus Prime

Software

Set up Hardware Program Device Test Designin Hardware

1. Launch the Intel Quartus Prime Pro Edition software and select Processing ➤Start Compilation to compile the design.

The timing constraints for the design example and the design components areautomatically loaded during compilation.

2. Connect the development board to the host computer.

3. Launch the Clock Control tool, which is part of the development kit, and set newfrequencies for the design example.

Note: For the frequencies to set, refer to the Hardware Testing section of thespecific design example chapter.

4. In the Intel Quartus Prime Pro Edition software, select Tools ➤ Programmer toconfigure the FPGA on the development board using the generated .sof file.

5. Reset the system by pressing the PB0 push button.

6. In the Intel Quartus Prime software, select Tools ➤ System Debugging Tools ➤System Console to launch the system console.

7. Change the working directory to <Example Design>\hwtesting\system_console.

You can now run any of the predefined hardware tests from the System Console.

Observe the test results displayed.

1 Quick Start Guide

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1.4.2 Hardware Setup

Figure 5. Block Diagram of the Hardware Setup

Intel Stratix 10 Transceiver Signal Integrity Development Board

JTAG TAPController

SystemController

Ethernet Frame Generation& Monitoring (Master) Ethernet Channel 0

Ethernet Frame Generation& Monitoring (Slave)

Ethernet Channel 1

Ethernet Frame Generation& Monitoring Ethernet Channel n - 1

Ethernet Frame Generation& Monitoring

Ethernet Channel n

Intel Stratix 10 FPGA

Intel SystemConsole

Software

PC

(1)

(2)

(1)(2)

Use this type of loopback to test IEEE 1588v2 features.Use this type of loopback to test features other than IEEE 1588v2. This loopback is different than the loopback usedfor simulating multiple channels.

1 Quick Start Guide

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2 10GBASE-R Ethernet Design Example for Intel Stratix10 Devices

The 10GBASE-R Ethernet design example demonstrates an Ethernet solution for IntelStratix 10 devices using the LL 10GbE MAC IP core, the native PHY IP core, and asmall form factor pluggable (SFP +) module.

Generate the design example from the Example Design tab of the LL 10GbE IPparameter editor.

2.1 Features

• Supports dual Ethernet channel operating at 10G using Intel Stratix 10 Native PHY.

• On the transmit and receive paths:

— Provides packet monitoring system.

— Reports Ethernet MAC statistics counter.

• Supports testing using different types of Ethernet packet transfer protocol.

2.2 Hardware and Software Requirements

Intel uses the following hardware and software to test the design example in a Linuxsystem:

• Intel Quartus Prime Pro Edition software

• ModelSim-AE, ModelSim-SE, NCSim (Verilog only), and VCS simulator

• For hardware testing:

— Intel Stratix 10 Signal Integrity Development Board (1SG280LU3F50E3VGS1)and Intel Stratix 10 H-Tile GX Signal Integrity Development Board(1SG280HU3F50E3VGS1)

— Cables—SMA cable, SFP+, and fiber optic cable

Related Links

Analyzing and Debugging Designs with System Console

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https://www.altera.com/documentation/jbr1437428483891.html#mwh1410384184752




2.3 Functional Description

Figure 6. Block Diagram—10GBASE-R Ethernet Design Example

Input Clock Reset

Avalon-ST

Avalon-MMMaster

Avalon-MM

FIFOLL 10GbE MAC

PHY

Transceiver ResetController

TX/RXSerialData

PLL ResetSynchronizer

Design Example

Adapter

Adapter

(altera_eth_10g_mac_base_r)

ATX PLL

Address Decoderaltera_eth_10g_mac_base_r_wrap

Generated with Platform DesignerGenerated with IP Catalog

S

SS M

2.3.1 Design Components

Table 4. Design Components


LL 10GbE MAC The Intel FPGA Low Latency Ethernet 10G MAC IP core with the following configuration:• Speed: 10G• Datapath options: TX & RX• Enable ECC on memory blocks: Not selected• Enable 10GBASE-R register mode: Not selected• Enable supplementary address: Selected• Enable statistics collection: Selected• Statistics counters: Memory-based• Use legacy XGMII Interface: Selected.• Use legacy Avalon Memory-Mapped Interface: Not Selected• Use legacy Avalon Streaming Interface: Not selected

PHY • Intel FPGA Transceiver Native PHY configured for the 10GBASE-R protocol.• The preset sets the PHY's TX FIFO MODE to Phase Compensation and RX FIFO MODE to

10GBASE-R.


Intel FPGA Transceiver PHY Reset Controller IP core. Resets the transceiver.

Address decoder Decodes the addresses of the components.

Reset synchronizer Synchronizes the reset of all design components.

ATX PLL Generates a TX serial clock for the Intel Stratix 10 10G transceiver.

FIFO • Avalon Streaming (Avalon-ST) single-clock and dual-clock FIFO.• Buffers the RX and TX data between the MAC IP core and the client.

2 10GBASE-R Ethernet Design Example for Intel Stratix 10 Devices

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Related Links

• Low Latency Ethernet 10G MAC User GuideProvides more information about the MAC parameters.

• 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with KR FEC VariantsProvides more information about the PHY parameters.

2.3.2 Clocking and Reset Scheme

Figure 7. Clocking and Reset Scheme for 10GBASE-R Design Example

Generator andChecker

reset_n clk

FIFO

rx_sc_fifo_clk_reset_reset tx_sc_fifo_clk_reset_reset

rx_sc_fifo_clk_clk tx_sc_fifo_clk_clk

Avalon-ST Adapteravalon_st_rx_clk_312avalon_st_rx_312_reset_n

avalon_st_tx_clk_312avalon_st_tx_312_reset_n

avalon_st_rx_clk_156avalon_st_rx_156_reset_n

avalon_st_tx_clk_156avalon_st_tx_156_reset_n

LL 10GbE MAC

csr_clkcsr_rst_n

rx_312_5_clkrx_156_25_clk

rx_rst_n

tx_312_5_clktx_156_25_clk

tx_rst_n PHY

reconfig_clkrx_cdr_refclk0reconfig_reset

tx_xcvr_half_clktx_serial_clk

tx_clkoutrx_clkout

Address Decodertx_xcvr_half_clk_clksync_tx_half_rst_reset_n

clk_csr_clkcsr_reset_n

rx_xcvr_clk_clksync_rx_rst_reset_n

tx_xcvr_clk_clksync_tx_rst_reset_n

ResetController

reset clock

ResetSynchronizer

ATX PLL

125 MHz csr_clk

ref_clk_clk644.53125 MHz

master_reset_n

PLLoutclk_0

outclk_1

Avalon-MM Adaptersl_clocksl_reset

ms_clockms_reset

Transceiver

2.4 Simulation

The simulation test case demonstrates how the MAC and PHY configuration is changedat 10-Gbps throughput. The test case is for dual Ethernet channels.

At the end of the simulation, the simulator generates the statistics of TX and RXpackets in the Transcript window.

Related Links

Compiling and Simulating the Design on page 10Provides information on the procedure and testbench.

2.5 Hardware Testing

Follow the procedure at the provided link to test the design example in the selectedhardware.

In the Clock Control tool, which is part of the development kit, set the followingfrequencies:

• Y1—322.265625 MHz

• U5, OUT 8 —125 MHz


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https://www.altera.com/documentation/bhc1395127830032.html#bhc1395127588036

https://www.altera.com/documentation/joc1445446725697.html#joc1446490105251

Related Links

Compiling and Testing the Design in Hardware on page 12

2.5.1 Test Cases

You can run any of the following tests from the System Console.

Table 5. Hardware Test Cases

Test Case Command Description

SFP+ loopback source gen_conf.tcl The generator generates and sends about 100 000 packets. Wait1 minutes for it to complete its tasks.

source monitor_conf.tcl The monitor checks the number of good and bad packetsreceived.

source show_stats.tcl This script displays the values of the statistics counters.

Avalon-ST loopback source loopback_conf.tcl This command enables the Avalon-ST loopback. This test is usedwith an external tester such as Spirent tester.

After the test is completed, observe the output displayed in the System Console.

Figure 8. Test Output Sample for SFP+ Loopback


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Figure 9. Test Output Sample—TX and RX Statistics Counters

2.5.2 Signal Tap Debug Signals

The Signal Tap file is included for debugging.

This feature is disabled by default. To enable it, set the following assignment:

set_global_assignment -name ENABLE_SIGNALTAP ON

Table 6. Signal Tap Debug Signals

Component Module Name Signal

Top-leveldesignexample

altera_eth_top • csr_clk

• ref_clk_clk

• master_reset_n

• block_lock_n

• tx_ready_export_n

• rx_ready_export_n

DesignExample

altera_eth_top.altera_eth_10g_mac_base_r_low_latency

• atx_pll_locked

• iopll_locked

MAC IP core altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_base_r_low_latency_wrap.low_latency_mac

• avalon_st_tx_startofpacket

• avalon_st_tx_endofpacket

• avalon_st_tx_data

• avalon_st_tx_ready

• avalon_st_tx_valid

continued...


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Component Module Name Signal

• avalon_st_tx_error

• avalon_st_tx_empty

• avalon_st_rx_startofpacket

• avalon_st_rx_endofpacket

• avalon_st_rx_data

• avalon_st_rx_ready

• avalon_st_rx_valid

• avalon_st_rx_error

• avalon_st_rx_empty

MAC TX altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_base_r_low_latency_wrap.low_latency_mac.alt_em10g32.alt_em10g32unit.alt_em10g32_tx_top.alt_em10g32_tx_rs_layer.alt_em10g32_tx_rs_xgmii_layer_ultra

• xgmii_tx_valid

• xgmii_tx_data

• xgmii_tx_control

MAC RX altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_base_r_low_latency_wrap.low_latency_mac.alt_em10g32.alt_em10g32unit.alt_em10g32_rx_top.alt_em10g32_rx_rs_layer.alt_em10g32_rx_rs_xgmii_ultra

• xgmii rx valid

• xgmii rx data

• xgmii rx control

• xgmii rx link fault status

PHY altera_eth_top.altera_eth_10g_mac_base_r_low_latency.altera_eth_10g_mac_base_r_low_latency_wrap.low_latency_baser

• tx_analogreset

• tx_digitalreset

• rx_analogreset

• rx_digitalreset

• tx_cal_busy

• rx_cal_busy

• rx_is_lockedtodata

• tx_clkout


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2.6 Interface Signals

Figure 10. Interface Signals of the 10GBASE-R Ethernet Design Example

10BASE-R Ethernet Design Example

PHY Interface

tx_ready_export[n]rx_ready_export[n]block_lock[n]atx_pll_locked tx_serial_data[n]

rx_serial_data[n]

Clock andReset

csr_clk

rx_rst_n

tx_rst_n

csr_rst_n

ref_clk_clktx_clk_312 tx_clk_156

avalon_st_rxstatus_valid[n]avalon_st_rxstatus_data[n][40]avalon_st_rxstatus_error[n][7]

Avalon-ST ReceiveStatus Interface

avalon_st_rx_endofpacket[n]avalon_st_rx_startofpacket[n]

avalon_st_rx_valid[n]avalon_st_rx_ready[n]avalon_st_rx_error[n][6]avalon_st_rx_data[n][32]avalon_st_rx_empty[n][2]

Avalon-ST ReceiveData Interface

Avalon-ST TransmitStatus Interface

avalon_st_txstatus_valid[n]avalon_st_txstatus_data[n][40]avalon_st_txstatus_error[n][7]

Avalon-ST TransmitFlow Control Interface

avalon_st_pause_data[n][2]

Avalon-ST TransmitData Interface

avalon_st_tx_startofpacket[n]avalon_st_tx_endofpacket[n]avalon_st_tx_valid[n]avalon_st_tx_ready[n]avalon_st_tx_error[n]avalon_st_tx_data[n][32]avalon_st_tx_empty[n][2]

link_fault_status_xgmii_rx_data[2]

rx_clk_312 rx_clk_156

Avalon-MMInterface

mac_csr_read[n]mac_csr_readdata[n][32]

mac_csr_write[n]mac_csr_writedata[n][32]

mac_csr_address[n][10]mac_csr_waitrequest[n]

phy_csr_read[n]phy_csr_readdata[n][32]

phy_csr_write[n]phy_csr_writedata[n][32]

phy_csr_address[n][11]phy_csr_waitrequest[n]

Status Interface

Related Links

Interface Signals Description on page 60For more information on each interface signal.

2.7 Configuration Registers

You can access the 32-bit configuration registers of the design components throughthe Avalon-MM interface.

Table 7. Register Map

Byte Offset Block

0x0000_0000 – 0x0001_CFFF Reserved

0x0001_D000 – 0xFFFF_FFFF Client Logic

Channel 0

0x0000_0000 MAC

0x0000_8000 PHY

0x0000_d400 RX SC FIFO

0x0000_d600 TX SC FIFO

0x0000_c000 Packet Generator and Checker

Channel 1continued...


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Byte Offset Block

0x0001_0000 MAC

0x0001_8000 PHY

0x0001_d400 RX SC FIFO

0x0001_d600 TX SC FIFO

0x0001_c000 Packet Generator and Checker

Related Links

Configuration Registers Description on page 68For more information on each configuration register.


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3 10M/100M/1G/2.5G/10G Ethernet Design Example forIntel Stratix 10 Devices

The 10M/100M/1G/2.5G/10G Ethernet design example demonstrates an Ethernetsolution for Intel Stratix 10 using the LL 10GbE MAC IP core operating at 10M, 100M,1G, 2.5G, and 10G.


3.1 Features

• Supports dual Ethernet channel operating at 10M, 100M, 1G, 2.5G, and 10G usingIntel Stratix 10 Multi-rate PHY.













The design example consists of various components. The following block diagramshows the design components and the top-level signals of the design example.

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Figure 11. Block Diagram—10M/100M/1G/2.5G/10G Ethernet Design Example

1G Input ClockReset

AddressDecoder

S

M

Avalon-MM

LL 10GbE MACS

TX/RXSerialData

Ethernet channel 0..(n-1)

Transceiver Reconfig

Avalon-ST

Design Example

(alt_mge_channel)

(alt_mge_rd)

Avalon-MM MuxTransceiver

ReconfigS

TransceiverReset

Controller

PHYS

M

M

.

.

.

ATX PLL(10G)

ATX PLL(2.5G)

10G Input Clock

fPLL(1G)





LL 10GbE MAC The Low Latency Ethernet 10G MAC IP core with the following configuration:• Speed: 10M/100M/1G/2.5G/10G• Datapath options: TX & RX• Enable ECC on memory blocks: Not selected• Enable supplementary address: Selected• Enable statistics collection: Selected• Statistics counters: Memory-based• All Legacy Ethernet 10G MAC Interfaces options: Selected

PHY The 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP with the following configuration:• Speed: 1G/2.5G/10G• SGMII bridge: Selected• Connect to MGBASE-T PHY: Selected• Connect to NBASE-T PHY: Not selected• PHY ID (32 bit): 0x00000000• VCCR_GXB and VCC_GXB supply voltage for the Tranceiver: 1_0V• Reference clock frequency for 10GbE (MHz): 644.53125• Selected TX PMA local clock division factor for 1 GbE: 1• Selected TX PMA local clock division factor for 2.5 GbE: 1• Enable Altera Debug Master Endpoint: Not selected• Enable capability registers: Not selected• Enable control and status registers: Not selected• Enable PRBS soft accumulators: Not selected

Transceiver Reset Controller The Intel FPGA Transceiver PHY Reset Controller IP core. Resets the transceiver.

continued...

3 10M/100M/1G/2.5G/10G Ethernet Design Example for Intel Stratix 10 Devices

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Avalon-MM Mux TransceiverReconfig

Provides the transceiver reconfig block and system console access to the PHY's Avalon-MMinterface.

Transceiver Reconfig Reconfigures the transceiver channel speed from 1G to 2.5G, or to 10G, and vice versa.

ATX PLL Generates a TX serial clock for the Intel Stratix 10 2.5G and 10G transceiver.

fPLL Generates a TX serial clock for the Intel Stratix 10 1G transceiver.

Related Links

Low Latency Ethernet 10G MAC User GuideProvides more information about the MAC parameters.

3.3.2 Clocking Scheme

Figure 12. Clocking Scheme for 10M/100M/1G/2.5G/10G Ethernet Design Example

MAC PHY


1G/2.5G/10GReconfiguration

Block

Channel 0

MAC PHY

Channel 1

2.5G PLL

1G PLL

Design Example

125 MHzReference

Clock

User Logic

User Logic

CSR Clock2.5G TXSerial Clock

1G TXSerial Clock

10G TXSerial Clock

PLL

125 MHz Reference Clock

2.5G TX Serial Clock (1562.5 Mbps)

1G TX Serial Clock (625 Mbps)HSSI TX Clock Out 62.5 MHz at 1G, 156.25 MHz at 2.5G125 MHz CSR Clock

156.25 MHz MAC Clock

MAC Clock CDR Reference Clocks

CDR Reference Clock

10G PLL

644.53125 MHzReference

Clock

10G TX Serial Clock (5156.25 Mbps)644.53125 MHz Reference Clock

3.3.3 Reset Scheme

The global reset signal of the design example is asynchronous and active-high.Asserting this signal resets all channels and their components. Upon power-up, resetthe design example.


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Figure 13. Reset Scheme for 10M/100M/1G/2.5G/10G Ethernet Design Example

MAC PHY



Block

Channel 0

MAC PHY

Channel 1

2.5G PLL

1G PLL

Design Example

User Logic

Global ResetAnalog Reset

Digital Reset

Global Reset

Reconfiguration Done (triggers reset)

10G PLL

User Logic

3.4 Simulation

The simulation test case performs the following steps:

1. Starts up the example design with an operating speed of 10 Gbps.

2. Configures the MAC, PHY, and FIFO buffer for both channels.

3. Waits until the design example asserts the channel_tx_ready andchannel_rx_ready signals for both channels.

4. Sends the following packets:

• 64-byte packet

• 1518-byte packet

• 100-byte packet

5. Repeats steps 2 to 4 for 2.5G, 1G, 100M, and 10M.

When simulation ends, the values of the MAC statistics counters are displayed in thetranscript window. The transcript window also displays PASSED if the RX Avalon-STinterface of channel 0 received all packets successfully, all statistics error counters arezero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.


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• Y1— 644.53125 MHz

• U5, OUT 1—125 MHz

• U5, OUT 8—125 MHz

Related Links


3.5.1 Test Procedure

Follow these steps to test the design examples in hardware:

1. Run the following command in the system console to start the test.

TEST_EXT_LB <channel> <speed> <burst_size>

Example: TEST_EXT_LB 0 10G 80000000

Table 9. Command Parameters

Parameter Valid Values Description

channel 0, 1 The channel number to test.

speed 1G, 2.5G, 10G The PHY speed.

burst_size An integer value The number of packets to generate for the test.

2. When the test is completed, observe the output displayed. The following diagramsshow excerpts of the output, which shows that the packet monitor block receivesthe same number of packets generated without error, and the TX and RX statisticscounters.


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Figure 14. Sample Output—Packet Monitor


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Figure 15. Sample Output—TX and RX Statistics Counters


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Figure 16. Interface Signals of the Design Example

MAC RX

10M/100M/1G/2.5G/10G Ethernet Design Example

avalon_st_rx_status_valid[n]avalon_st_rx_status_data[n][40]avalon_st_rx_status_error[n][7]






avalon_st_tx_status_valid[avalon_st_tx_status_data[n][40]avalon_st_tx_status_error[n][7]

n]





Avalon-MM Interface

Clock andReset

csr_clk

refclk_10g

mac_clk

reset

tx_digitalreset[n]rx_digitalreset[n]

rx_pma_clkout

mac64b_clk

refclk_1g2p5g

n: Number of channels

PHY Interface rx_serial_data[n]tx_serial_data[n]

led_link[n]

led_char_err[n]led_disp_err[n]led_an[n]

channel_tx_ready[n]channel_rx_ready[n]

rx_block_lock[n]

csr_mac_read[n]csr_mac_readdata[n][32]

csr_mac_write[n]csr_mac_writedata[32]

csr_mac_address[n][10]csr_mac_waitrequest[n]

csr_phy_read[n]csr_phy_readdata[n][32]

csr_phy_write[n]csr_phy_writedata[32]csr_phy_address[n][11]

csr_phy_waitrequest[n]

csr_rcfg_readcsr_rcfg_readdata[32]

csr_rcfg_writecsr_rcfg_writedata[32]

csr_rcfg_address[2]

(LL 10GbE MAC)

Avalon-MM Interface(1G/2.5G/10G Multi-rate Ethernet PHY)

Avalon-MM Interface(Reconfiguration)

Status Interface

led_panel_link[n]

Related Links





Byte Offset Block

0x00_0000 Transceiver Reconfiguration

0x00_4000 Reserved

Channel 0

0x01_0000 MAC

0x01_8000 PHY

0x01_A000 Native PHY Reconfiguration

Channel 1

0x02_0000 MAC

0x02_8000 PHY

continued...


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Byte Offset Block


Traffic Controller

0x10_0000 Traffic Controller

Related Links



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4 1G/2.5G Ethernet Design Example with IEEE 1588v2Feature for Intel Stratix 10 Devices

The 1G/2.5G Ethernet design example with the IEEE 1588v2 feature demonstrates anEthernet solution for Intel Stratix 10 devices using the LL 10GbE MAC IP coreoperating at 1G and 2.5G.


4.1 Features

• Supports dual Ethernet channel operating at 1G and 2.5G using Intel Stratix 10Multi-rate PHY.












Related Links

Analyzing and Debugging Designs with System Console

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https://www.altera.com/documentation/jbr1437428483891.html#mwh1410384184752





Figure 17. Block Diagram—1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature

Avalon-MM

S

alt_mge_channel

PTP PacketClassifier

LL 10GbEMAC

S

PHYS

LocalTOD

STODSync

Pulse perSecond

alt_mge_channel

TransceiverReset

ControllerS

I/O PLL

MasterTOD

S

Pulse perSecond

Avalon-MMMultiplexerTransceiver

Reconfiguration

S

TransceiverReconfiguration

S

Reset Input Clock

Master PulsePer Second

TX/RX SerialData

1G/2.5G PulsePer Second

Avalon-ST

alt_mge_rd_addrdec_mch

Avalon-MMMaster

S M

altera_eth_top


alt_mge_rd

CSR Clock

ATX PLL fPLL

fPLL




LL 10GbE MAC The Low Latency Ethernet 10G MAC IP core with the following configuration:• Speed: 1G/2.5G• Datapath options: TX & RX• Enable ECC on memory blocks: Not selected• Enable supplementary address: Selected• Enable statistics collection: Selected• Statistics counters: Memory-based• All Legacy Ethernet 10G MAC Interfaces options: SelectedFor the example design with the IEEE 1588v2 feature, the following additional parametersare configured:• Enable time stamping: Selected• Enable PTP one-step clock support: Selected• Timestamp fingerprint width: 4• Time Of Day format: Enable both 96b and 64b Time of Day Format

PHY The 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP with the following configuration:

continued...

4 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices

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• Speed: 1G/2.5G• Enable SGMII bridge: Not selected• Enabled IEEE 1588 Precision Time Protocol: Selected• PHY ID (32 bit): 0x00000000• VCCR_GXB and VCC_GXB supply voltage for the Tranceiver: 1_0V• Selected TX PMA local clock division factor for 1 GbE: 1• Selected TX PMA local clock division factor for 2.5 GbE: 1• Enable Altera Debug Master Endpoint: Not selected• Enable capability registers: Not selected• Enable control and status registers: Not selected• Enable PRBS soft accumulators: Not selected




Transceiver Reconfig Reconfigures the transceiver channel speed from 1 Gbps to 2.5 Gbps, and vice versa.

ATX PLL Generates a TX serial clock for the Intel Stratix 10 2.5G transceiver.


Design Components for the IEEE 1588v2 Feature

IO PLL Generates the clocks for the 1588 design components.

Master Time-of-Day (TOD) The master TOD for all channels.

TOD Synch Synchronizes the Master TOD to all Local TODs.

Local TOD The TOD for each channel.

Master Pulse Per Second(PPS)

The master PPS. Returns pulse per second (pps) for all channels.

PPS The slave PPS. Returns pulse per second (pps) for each channel.

PTP Packet Classifier Decodes the packet type of incoming PTP packets and returns the decoded information tothe LL10GbE MAC IP core.

Related Links

Low Latency Ethernet 10G MAC User GuideProvides more information about the MAC parameters.


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Figure 18. Clocking Scheme for 1G/2.5G Ethernet Design Example with IEEE 1588v2Feature

MACClock

125 MHzCSR Clock


MAC

PHY

TOD 2.5G SyncTOD 2.5G PPS 2.5G

TOD 1G SyncTOD 1G PPS 1G

UserLogic

Channel N

AddressDecoder

TransceiverReset

Controller

1G/2.5GReconfiguration

Block1G fPLL

2.5GATX PLL

SamplingIOPLL

MasterToD

MasterPPS

Reference Design

125 MHzReference

Clock

Reference Clock (125 MHz)2.5G TX Serial Clock (1562.5 MHz)1G TX Serial Clock (625 MHz)HSSI TX Clock Out: 62.5 MHz at 1G, 156.25 MHz at 2.5G

CSR Clock (125 MHz)Sampling Clock (53.33 MHz)Sampling Clock (80 MHz)MAC Clock (156.25 MHz)

HSSI TX Clock In: 62.5 MHz at 1G, 156.25 MHz at 2.5G

CorePLL

4.3.3 Reset Scheme

The global reset signal of the design example is asynchronous and active-low.Asserting this signal resets all channels and their components. Upon power-up, resetthe design example.


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Figure 19. Reset Scheme for 1G/2.5G Ethernet Design Example with IEEE 1588v2Feature


MAC

PHY

TOD 2.5G SyncTOD 2.5G PPS 2.5G

TOD 1G SyncTOD 1G PPS 1G

UserLogic

Channel N

AddressDecoder

TransceiverReset

Controller

1G/2.5GReconfiguration

Block1G fPLL

2.5GATX PLL

SamplingIOPLL

TODMaster

PPSMaster

Design Example

Global Reset

Digital ResetDigital/Analog Reset Stat Analog Reset

Reconfiguration Done(to trigger reset after reconfiguration)

GlobalReset

4.4 Simulation

4.4.1 Test Case—Design Example with the IEEE 1588v2 Feature


1. Starts up the design example with an operating speed of 2.5G.


3. Waits until the design example asserts the channel_tx_ready andchannel_rx_ready signals for each channel.


• Non-PTP

• No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP

• VLAN, PTP over UDP/IPv4, PTP Sync Message, 1-step PTP

• Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP

• No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP

• VLAN, PTPover UDP/IPv4, PTP Delay Request Message, 2-step PTP

• Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP

5. Repeats steps 2 to 4 for 1G.



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Figure 20. Sample Simulation Output




• U5, OUT 0—125 MHz

• U5, OUT 8—125 MHz

Related Links






Example: TEST_EXT_LB 0 2.5G 1000000000


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speed 1G, 2.5G The PHY speed.





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Figure 22. Sample Output—TX and RX statistics counters


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Figure 23. Interface Signals of the 1G/2.5G Ethernet Design Examples with IEEE 1588v2Feature

MAC RX

1G/2.5G Ethernet Design Example with 1588v2 Feature

avalon_st_rxstatus_valid[n]avalon_st_rxstatus_data[n][40]avalon_st_rxstatus_error[n][7]






avalon_st_txstatus_valid[n]avalon_st_txstatus_data[n][40]avalon_st_txstatus_error[n][7]





Avalon-MM Interface

Clock andReset

csr_clk

refclkmac_clk

reset

tx_digital_reset[n]rx_digital_reset[n]

rx_pma_clkout

rx_digital_reset_stat[n]

IEEE 1588v2Time-Stamp

Interface

tx_egress_timestamp_96b_valid[n]tx_egress_timestamp_96b_data[n][96]tx_egress_timestamp_96b_fingerprint[n][f]tx_egress_timestamp_64b_valid[n]tx_egress_timestamp_64b_data[n][64]tx_egress_timestamp_64b_fingerprint[n][f]rx_ingress_timestamp_96b_valid[n]rx_ingress_timestamp_96b_data[n][96]rx_ingress_timestamp_64b_valid[n]rx_ingress_timestamp_64b_data[n][64]

n: Number of channelsf: Timestamp fingerprint width

master_pulse_per_secondstart_tod_sync[n]

pps[n]TOD Interface

Packet ClassifierInterface

tx_egress_timestamp_request_in_valid[n]tx_egress_timestamp_request_in_fingerprint[n][f]

clock_operation_mode_mode[n][2]pkt_with_crc_mode[n]

tx_ingress_timestamp_valid[n]tx_ingress_timestamp_96b_data[n][96]tx_ingress_timestamp_64b_data[n][64]

tx_ingress_timestamp_format[n]


led_char_err[n]led_disp_err[n]led_an[n]channel_tx_ready[n]

led_link[n]

channel_rx_ready[n]




csr_master_tod_waitrequest[n]

csr_master_tod_read[n]csr_master_tod_readdata[n][32]

csr_master_tod_write[n]csr_master_tod_writedata[n][32]

csr_master_tod_address[n][4]


csr_phy_write[n]csr_phy_writedata[32]

csr_phy_address[n][11]csr_phy_waitrequest[n]

csr_rcfg_read[n]csr_rcfg_readdata[32]

csr_rcfg_write[n]csr_rcfg_writedata[32]

csr_rcfg_address[2]csr_native_phy_rcfg_read

csr_native_phy_rcfg_readdata[32]csr_native_phy_rcfg_write

csr_native_phy_rcfg_writedata[32]

csr_native_phy_rcfg_waitrequestcsr_native_phy_rcfg_address[10]

(LL 10GbE MAC)

Avalon-MM Interface(1G/2.5G/10G Multi-rate Ethernet PHY)

Avalon-MM Interface(Reconfiguration)

Avalon-MM Interface(Native PHY Reconfiguration)

Avalon-MM Interface(Master ToD Clock)

Status Interface

Related Links





Byte Offset Block


0x00_4000 TOD Master

continued...


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Byte Offset Block

Channel 0

0x01_0000 MAC

0x01_8000 PHY


Channel 1

0x02_0000 MAC

0x02_8000 PHY


Traffic Controller


Related Links



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5 1G/2.5G/10G Ethernet Design Example with IEEE1588v2 Feature for Intel Stratix 10 Devices

The 1G/2.5G/10G Ethernet design example with the IEEE 1588v2 featuredemonstrates an Ethernet solution for Intel Stratix 10 using the LL 10GbE MAC IP coreoperating at 1G, 2.5G, and 10G.


5.1 Features

• Supports dual Ethernet channel operating at 1G, 2.5G, and 10G using Intel Stratix10 Multi-rate PHY.














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Figure 24. Block Diagram—1G/2.5G/10G Ethernet Design Example with IEEE 1588v2Feature

Avalon-MM

S

alt_mge_channel


LL 10GbE MAC

S

PHYS

LocalTOD

S TODSync

Pulse perSecond

alt_mge_channel

TransceiverReset

ControllerS Master

TODS

Pulse perSecond

Avalon-MMMultiplexerTransceiver

Reconfiguration

S

TransceiverReconfiguration

S

Reset 1G/2.5G/10G Core Reference Clocks

Master PulsePer Second

TX/RX SerialData

1G/2.5G/10G Pulse Per Second

Avalon-ST

alt_mge_rd_addrdec_mch

Avalon-MMMaster

S M

altera_eth_top

Generated with IP CatalogGenerated with Platform Designer

alt_mge_rd

CSR Clock

ATXPLL

ATXPLL

fPLL fPLL fPLL

CorePLL




LL 10GbE MAC The Low Latency Ethernet 10G MAC IP core with the following configuration:• Speed: 1G/2.5G/10G• Datapath options: TX & RX• Enable ECC on memory blocks: Not selected• Enable supplementary address: Selected• Enable statistics collection: Selected• Statistics counters: Memory-based• All Legacy Ethernet 10G MAC Interfaces options: SelectedFor the design example with the IEEE 1588v2 feature, the following additional parametersare configured:• Enable time stamping: Selected• Enable PTP one-step clock support: Selected• Timestamp fingerprint width: 4• Time Of Day format: Enable both 96b and 64b Time of Day Format

PHY The 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP with the following configuration:• Speed: 1G/2.5G/5G/10G• Enable SGMII bridge: Not selected• Enabled IEEE 1588 Precision Time Protocol: Selected• Connect to MGBASE-T PHY: Selected

continued...

5 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature for Intel Stratix 10 Devices

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• Connect to NBASE-T PHY: Not selected• PHY ID (32 bit): 0x00000000• VCCR_GXB and VCC_GXB supply voltage for the Tranceiver: 1_0V• Reference clock frequency for 10GbE (MHz): 644.53125• Selected TX PMA local clock division factor for 1 GbE: 1• Selected TX PMA local clock division factor for 2.5 GbE: 1• Enable Altera Debug Master Endpoint: Not selected• Enable capability registers: Not selected• Enable control and status registers: Not selected• Enable PRBS soft accumulators: Not selected




Transceiver Reconfig Reconfigures the transceiver channel speed from 1G to 2.5G, or to 10G, and vice versa.

ATX PLL Generates a TX serial clock for the Intel Stratix 10 2.5G and 10G transceiver.


Design Components for the IEEE 1588v2 Feature

Core PLL Generates the clocks for the 1588 design components.

Master ToD The master ToD for all channels.

ToD Synch Synchronizes the Master ToD to all Local ToDs.

Local ToD The ToD for each channel.

Master PPS The master PPS. Returns pulse per second (pps) for all channels.

PPS The slave PPS. Returns pulse per second (pps) for each channel.

PTP Packet Classifier Decodes the packet type of incoming PTP packets and returns the decoded information tothe LL10GbE MAC IP core.



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Figure 25. Clocking Scheme for 1G/2.5G/10G Ethernet Design Example with IEEE1588v2 Feature

mac64b_clk

125 MHzcsr_clk


MAC

PHY

ToD 2.5G PPS 2.5G

ToD 1G PPS 1G

UserLogic

Channel N

AddressDecoder

TransceiverReset

Controller


Block

10GATX PLL

2.5GATX PLL

ToDSampling

fPLL

MasterToD

MasterPPS

Design Example

644.53125 MHzrefclk_10g

refclk_10g (644.53125 MHz)refclk_1g2p5g (125 MHz)refclk_core (125 MHz)xcvr_pll_10g_serial_clk (5156.25 MHz)

xcvr_pll_1g_serial_clk (625 MHz)gmii16b_tx_clk (62.5 MHz [1G], 156.25 MHz [2.5G])gmii16b_rx_clk (62.5 MHz [1G], 156.25 MHz [2.5G])csr_clk (125 MHz)

xcvr_pll_2p5g_serial_clk (1562.5 MHz)

ToD 10GSync

ToD 10G PPS 10G

TransceiverSampling

fPLL

1GfPLL

125 MHzrefclk_core

TOD 10GSync

ToD 10GSync

125 MHzrefclk_1g2p5g

latency_sclk (153.846153 MHz)tod_sampling_clk (80 MHz)mac_clk (312.5 MHz)mac64b_clk (156.25 MHz)

CorePLL

5.3.3 Reset Scheme

The global reset signal of the design example is asynchronous and active-low.Asserting this signal resets all channels and their components. Upon power-up, resetthe design example.

Figure 26. Reset Scheme for 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2Feature


MAC

PHY

ToD 10G SyncToD 10G PPS 10G


UserLogic

Channel N

AddressDecoder

TransceiverReset

Controller


Block

Design Example

Global Reset

Digital ResetAnalog Reset

Reconfiguration Done(to trigger reset after reconfiguration)

GlobalReset


10GATX PLL

2.5GATX PLL

ToDSampling

fPLL

MasterToD

MasterPPS

TransceiverSampling

fPLL

1GfPLL


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5.4 Simulation

5.4.1 Test Case—Design Example with the IEEE 1588v2 Feature


1. Starts up the design example with an operating speed of 10G.


3. Waits until the design example asserts the channel_tx_ready andchannel_rx_ready signals for each channel.


• Non-PTP

• No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP

• VLAN, PTP over UDP/IPv4, PTP Sync Message, 1-step PTP

• Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP

• No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP

• VLAN, PTPover UDP/IPv4, PTP Delay Request Message, 2-step PTP

• Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP

5. Repeats steps 2 to 4 for 1G and 2.5G.



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The design example is using board trace loopback by default. To use SFP+, followinstruction in Changing to SFP+ Setting on page 47.


For board trace loopback setting:

• U5, OUT 0—644.53125 MHz

• U5, OUT 4—125 MHz

• U5, OUT 8—125 MHz

For SFP+ setting:


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• Y1—644.53125 MHz

• U5, OUT 1—125 MHz

• U5, OUT 8—125 MHz

Related Links


5.5.1 Changing to SFP+ Setting

In order to use SFP+, modify altera_eth_top.qsf file with the following setting:







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speed 1G, 2.5G, 10G The PHY speed.





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Figure 30. Interface Signals of the 1G/2.5G/10G Ethernet Design Examples with IEEE1588v2 Feature

MAC RX

1G/2.5G/10G Ethernet Design Example with 1588v2 Feature







avalon_st_tx_status_valid[n]avalon_st_tx_status_data[n][40]avalon_st_tx_status_error[n][7]





Avalon-MM Interface

Clock andReset

csr_clk

refclk_10g

mac_clk

resettx_digitalreset[rx_digitalreset[

mac64b_clk

refclk_1g2p5grefclk_core

rx_digitalreset_stat[

n]n]n]

n: Number of channels


led_char_err[n]led_disp_err[n]led_an[n]channel_tx_ready[n]

led_link[n]

channel_rx_ready[n]





csr_phy_write[n]csr_phy_writedata[32]

csr_phy_address[n][11]csr_phy_waitrequest[n]

csr_rcfg_readcsr_rcfg_readdata[32]

csr_rcfg_writecsr_rcfg_writedata[32]

csr_rcfg_address[2]

csr_native_phy_rcfg_readcsr_native_phy_rcfg_readdata[32]

csr_native_phy_rcfg_writecsr_native_phy_rcfg_writedata[32]

csr_native_phy_rcfg_waitrequestcsr_native_phy_rcfg_address[11]

(LL 10GbE MAC)

Avalon-MM Interface(1G/2.5G/5G/10G Multi-rate Ethernet PHY)

Avalon-MM Interface(1G/2.5G/10G

Avalon-MM Interface(Direct Native PHY

Status Interface

Ethernet Reconfiguration)

Reconfiguration)

csr_master_tod_write[

csr_master_tod_read[

n]

csr_master_tod_address[n]csr_master_tod_waitrequest[n]

n]

csr_master_tod_writedata[n][32]

csr_master_tod_readdata[n][32]Avalon-MM Interface(Master ToD Clock)

IEEE 1588v2Time-Stamp

Interface

tx_egress_timestamp_96b_valid[n]tx_egress_timestamp_96b_data[n][96]tx_egress_timestamp_96b_fingerprint[n][f]tx_egress_timestamp_64b_valid[n]tx_egress_timestamp_64b_data[n][64]tx_egress_timestamp_64b_fingerprint[n][f]rx_ingress_timestamp_96b_valid[n]rx_ingress_timestamp_96b_data[n][96]rx_ingress_timestamp_64b_valid[n]rx_ingress_timestamp_64b_data[n][64]

master_pulse_per_secondstart_tod_sync[n]

pps[n]TOD Interface

Packet ClassifierInterface

tx_egress_timestamp_request_in_valid[n]tx_egress_timestamp_request_in_fingerprint[n][f]

clock_operation_mode_mode[n][2]pkt_with_crc_mode[n]

tx_ingress_timestamp_valid[n]tx_ingress_timestamp_96b_data[n][96]tx_ingress_timestamp_64b_data[n][64]

tx_ingress_timestamp_format[n]

f: Timestamp fingerprint width




Byte Offset Block


0x00_4000 TOD Master

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Byte Offset Block

Channel 0

0x01_0000 MAC

0x01_8000 PHY


Channel 1

0x02_0000 MAC

0x02_8000 PHY


Traffic Controller



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6 10G USXGMII Ethernet Design Example for Intel Stratix10 Devices

The 10G USXGMII design example demonstrates an Ethernet solution for Intel Stratix10 devices using the LL 10GbE MAC IP core operating at 1G, 2.5G, 5G, and 10G.


6.1 Features

• Supports dual Ethernet channel operating at 1G, 2.5G, 5G, and 10G.














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Figure 31. Block Diagram—10G USXGMII Ethernet Design Example

Reset

AddressDecoder

Avalon-MMTX/RXSerialData

Ethernet channel 0..(n-1)

Design Example

(alt_mge_channel)

(alt_mge_rd)

TransceiverReset

Controller

.

.

.

Core PLL

10G Input Clock

Avalon-ST

312.5 MHz156.25 MHz


ATX PLL(10G)

S LL 10GbEMAC

S PHY

S

M

M




LL 10GbE MAC The Intel FPGA Low Latency Ethernet 10G MAC IP core with the following configuration:• Speed: 1G/2.5G/5G/10G (USXGMII)• Datapath options: TX & RX• Enable ECC on memory blocks: Not selected• Enable supplementary address: Selected• Enable statistics collection: Selected• Statistics counters: Memory-based• Use legacy XGMII Interface: Not selected• Use legacy Avalon Memory-Mapped Interface: Not selected• Use legacy Avalon Streaming Interface: Selected

PHY The 1G/2.5G/5G/10G Multi-rate Ethernet PHY IP with the following configuration:• Speed: 1G/2.5G/5G/10G• Enable SGMII bridge: Not selected• Enabled IEEE 1588 Precision Time Protocol: Not Selected• Connect to MGBASE-T PHY: Not selected• Connect to NBASE-T PHY: Selected• VCCR_GXB and VCC_GXB supply voltage for the Tranceiver: 1_0V• Reference clock frequency for 10GbE (MHz): 644.53125• Enable Altera Debug Master Endpoint: Not selected• Enable capability registers: Not selected• Enable control and status registers: Not selected• Enable PRBS soft accumulators: Not selected

continued...

6 10G USXGMII Ethernet Design Example for Intel Stratix 10 Devices

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Channel address decoder Decodes the addresses of the components in each Ethernet channel.

Multi-channel addressdecoder

Decodes the addresses of the components used by all channels, such as the Master ToDmodule.

Top address decoder Decodes the addresses of the top-level components, such as the Traffic Controller.


ATX PLL Generates a TX serial clock for the Intel Stratix 10 transceiver.

Core PLL Generates clocks for all design components.


Figure 32. Clocking Scheme for 10G USXGMII Ethernet Design Example

MAC PHY


Channel 0

MAC PHY

Channel 1

10G PLL

Design Example

322.265625 MHzReference Clock

User Logic

User Logic

CSR Clock10G TXSerial Clock

PLL

322.265625 MHz Reference Clock 10G TX Serial Clock (5156.25 MHz)

312.5 MHz MAC Clock

MAC ClockCDR Reference Clock

CDR Reference Clock

125 MHz CSR Clock

6.3.3 Reset Scheme

The global reset signal of the design example is asynchronous and active-high.Asserting this signal resets all channels and their components. Upon power-up, resetthe design example.


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Figure 33. Reset Scheme for 10G USXGMII Ethernet Design Example

MAC PHY


Channel 0

MAC PHY

Channel 1

10G PLL

Design Example

XGMII withData Valid

XGMII withData Valid

User Logic

User Logic

Global Reset

Global Reset

Analog Reset

Digital Reset

6.4 Simulation


1. Starts up the example design with an operating speed of 10G.


3. Waits until the design example asserts the channel_tx_ready andchannel_rx_readysignals for both channels.


• 64-byte packet

• 1518-byte packet

• 100-byte packet

5. Repeats steps 2 to 4 for 1G, 2.5G, and 5G.



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• Y1—644.53125 MHz

• U5, OUT 8—125 MHz

Related Links






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speed 1G, 2.5G, 5G, 10G The PHY speed.





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Figure 37. Interface Signals of the 10G USXGMII Ethernet Design Example

10G USXGMII Ethernet Design Example

Clock andReset

csr_clk

mac32b_clk

reset

refclk_10g

mac64_clkrx_pma_clkout[

tx_digitalreset[rx_digitalreset[







avalon_st_tx_status_valid[n]avalon_st_tx_status_data[n][40]avalon_st_tx_status_error[n][7]





Avalon-MMInterface

csr_mch_read[n]csr_mch_readdata[n][32]

csr_mch_write[n]csr_mch_writedata[32]

csr_mch_address[n][20]csr_mch_waitrequest[n]

channel_tx_readychannel_rx_ready

rx_block_lockled_an

tx_serial_data[rx_serial_data[

PHY Interface

Status Interface

n]n]

n]

n]n]

n : Number of channels


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Byte Offset Block

0x00_0000 Reserved

Channel 0

0x02_0000 Reserved

0x02_4000 PHY

0x02_8000 MAC

Channel 1

0x03_0000 Reserved

0x03_4000 PHY

0x03_8000 MAC

Traffic Controller



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7 Interface Signals DescriptionUse the following tables to find the description of the signals in the design example.The pinout diagram for each design example specifies the width of the signals.

7.1 Clock and Reset Interface Signals

Table 20. Clock and Reset Interface Signals

Signal Direction Width Description

csr_clk In 1 125 MHz configuration clock for the Avalon-MMinterface and core logic. In Intel Stratix 10, it alsoprovides clock for core logics.

csr_rst_n In 1 Active-low reset signal for the Avalon-MM interface.

tx_rst_n In 1 Active-low reset signal for the TX datapath.

rx_rst_n In 1 Active-low reset signal for the RX datapath.

mac_clk In 1 156.25 MHz configuration clock for the Avalon-STinterface and 0 ppm frequency difference withrefclk.

refclk In 1 125 MHz reference clock for the TX PLLs.

ref_clk_clk In 1 644.53125 MHz clock for the TX PLL.

core_clk_312 Out 1 312.5 MHz clock for the fast domain.

core_clk_156 Out 1 156.25 MHz clock for the slow domain.

rx_pma_clkout Out 1 CDR recovered clock.

reset In 1 Assert this asynchronous and active-high signal toreset the whole design example.

tx_digitalreset Out [NUM_CHANNELS] Asynchronous and active-high signal to reset the TXdata path of the user logic.

rx_digitalreset Out [NUM_CHANNELS] Asynchronous active high reset signal for RX datapath of user logic.

rx_digitalreset_stat Out [NUM_CHANNELS] Status signal for rx_digitalreset from PHY.

7.2 Avalon-MM Interface Signals

Table 21. Avalon MM Interface Signals

Signal Direction Description

write

csr_write

csr_mac_write

In Assert this signal to request a write.

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csr_phy_write

csr_rcfg_write

csr_native_phy_rcfg_write

csr_master_tod_write

read

csr_read

csr_mac_read

csr_phy_read

csr_rcfg_read

csr_native_phy_rcfg_read

csr_master_tod_read

In Assert this signal to request a read.

address

csr_address

csr_mac_address

csr_phy_address

csr_rcfg_address

csr_native_phy_rcfg_address

csr_master_tod_address

In Use this bus to specify the register address you want to read from or write to.

writedata

csr_writedata

csr_mac_writedata

csr_phy_writedata

csr_rcfg_writedata

csr_native_phy_rcfg_writedata

csr_master_tod_writedata

In Carries the data to be written to the specified register.

readdata

csr_readdata

csr_mac_readdata

csr_phy_readdata

csr_rcfg_readdata

csr_native_phy_rcfg_readdata

csr_master_tod_readdata

Out Carries the data read from the specified register.

waitrequest

csr_waitrequest

csr_mac_waitrequest

csr_phy_waitrequest

csr_native_phy_rcfg_waitrequest

csr_master_tod_waitrequest

Out When asserted, this signal indicates that the IP core is busy and not ready toaccept any read or write requests.

7 Interface Signals Description

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7.3 Avalon-ST Interface Signals

Table 22. Avalon-ST Interface Signals

Signal Direction width Description

avalon_st_tx_startofpacket[]

In [NUM_CHANNELS] Assert this signal to indicate the beginning of the TXdata.

avalon_st_tx_endofpacket[]

In [NUM_CHANNELS] Assert this signal to indicate the end of the TX data.

avalon_st_tx_valid[] In [NUM_CHANNELS] Assert this signal to indicate that theavalon_st_tx_data signal and other signals onthis interface are valid.

avalon_st_tx_ready[] Out [NUM_CHANNELS] When asserted, indicates that the MAC IP core isready to accept data. The reset value of this signalis nondeterministic.

avalon_st_tx_error[] In [NUM_CHANNELS] Assert this signal to indicate that the current TXpacket contains errors.

avalon_st_tx_data[][]

In [NUM_CHANNELS][m] TX data from the client.m is 64 when the Use legacy Avalon StreamingInterface parameter is selected. Otherwise, m is32.

avalon_st_tx_empty[][]

In [NUM_CHANNELS][m] Use this signal to specify the number of emptybytes in the cycle that contain the end of the TXdata.m is 3 when the Use legacy Avalon StreamingInterface parameter is selected. Otherwise, m is 2.• 0x0—All bytes are valid.• 0x1—The last byte is invalid.• 0x2—The last two bytes are invalid.• 0x3—The last three bytes are invalid.

avalon_st_rx_startofpacket[]

Out [NUM_CHANNELS] When asserted, indicates the beginning of the RXdata.

avalon_st_rx_endofpacket[]

Out [NUM_CHANNELS] When asserted, indicates the end of the RX data.

avalon_st_rx_valid[] Out [NUM_CHANNELS] When asserted, indicates that theavalon_st_rx_data signal and other signals onthis interface are valid.

avalon_st_rx_ready[] In [NUM_CHANNELS] Assert this signal when the client is ready to acceptdata.

avalon_st_rx_error[][]

Out [NUM_CHANNELS][6] When set to 1, the respective bits indicate an errortype:• Bit 0—PHY error.

— — For 10 Gbps, the data on xgmii_rx_datacontains a control error character (FE).

— For 10 Mbps,100 Mbps,1 Gbps,gmii_rx_err or mii_rx_err is asserted.

• Bit 1—CRC error. The computed CRC value doesnot match the CRC received.

• Bit 2—Undersized frame. The receive framelength is less than 64 bytes.

continued...


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• Bit 3—Oversized frame. The receive framelength is more than MAX_FRAME_SIZE.

• Bit 4—Payload length error. The actual framepayload length is different from the value in thelength/type field.

• Bit 5—Overflow error. The receive FIFO buffer isfull while it is still receiving data from the MACIP core.

avalon_st_rx_data[][]

Out [NUM_CHANNELS][m] RX data to the client.m is 64 when the Use legacy Avalon StreamingInterface parameter is selected. Otherwise, m is32.

avalon_st_rx_empty[][]

Out [NUM_CHANNELS][m] Contains the number of empty bytes during thecycle that contain the end of the RX data.m is 3 when the Use legacy Avalon StreamingInterface parameter is selected. Otherwise, m is 2.

avalon_st_tx_status_valid[]

Out [NUM_CHANNELS] When asserted, this signal qualifies theavalon_st_txstatus_data andavalon_st_txstatus_error signals.

avalon_st_tx_status_data[][]

Out [NUM_CHANNELS][40] Contains information about the TX frame.• Bits 0 to 15: Payload length.• Bits 16 to 31: Packet length.• Bit 32: When set to 1, indicates a stacked VLAN

frame.• Bit 33: When set to 1, indicates a VLAN frame.• Bit 34: When set to 1, indicates a control frame.• Bit 35: When set to 1, indicates a pause frame.• Bit 36: When set to 1, indicates a broadcast

frame.• Bit 37: When set to 1, indicates a multicast

frame.• Bit 38: When set to 1, indicates a unicast frame.• Bit 39: When set to 1, indicates a PFC frame.

avalon_st_tx_status_error[][]

Out [NUM_CHANNELS][7] When set to 1, the respective bit indicates thefollowing error type in the TX frame:• Bit 0: Undersized frame.• Bit 1: Oversized frame.• Bit 2: Payload length error.• Bit 3: Unused.• Bit 4: Underflow.• Bit 5: Client error.• Bit 6: Unused.The error status is invalid when an overflow occurs.

avalon_st_rx_status_valid[]

Out [NUM_CHANNELS] When asserted, this signal qualifies theavalon_st_rxstatus_data and avalon_st_rxstatus_error signals.The MAC IP core asserts this signal in the sameclock cycle the avalon_st_rx_ endofpacketsignal is asserted.

avalon_st_rx_status_data[][]

Out [NUM_CHANNELS][40] Contains information about the RX frame.• Bits 0 to 15: Payload length.• Bits 16 to 31: Packet length.• Bit 32: When set to 1, indicates a stacked VLAN

frame.

continued...


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• Bit 33: When set to 1, indicates a VLAN frame.• Bit 34: When set to 1, indicates a control frame.• Bit 35: When set to 1, indicates a pause frame.• Bit 36: When set to 1, indicates a broadcast

frame.• Bit 37: When set to 1, indicates a multicast

frame.• Bit 38: When set to 1, indicates a unicast frame.• Bit 39: When set to 1, indicates a PFC frame.

avalon_st_rx_status_error[][]

Out [NUM_CHANNELS][7] When set to 1, the respective bit indicates thefollowing error type in the RX frame.• Bit 0: Undersized frame.• Bit 1: Oversized frame.• Bit 2: Payload length error.• Bit 3: Unused.• Bit 4: Underflow.• Bit 5: Client error.• Bit 6: Unused.The error status is invalid when an overflow occurs.

avalon_st_pause_data[][]

In [NUM_CHANNELS][2] This signal takes effect when the register bits,tx_pauseframe_enable[2:1], are both set tothe default value 0. Set this signal to the followingvalues to trigger the corresponding actions.• 0x0—Stops pause frame generation.• 0x1—Generates an XON pause frame.• 0x2—Generates an XOFF pause frame. The MAC

IP core sets the pause quanta field in the pauseframe to the value in thetx_pauseframe_quanta register.

• 0x3—Reserved.

Related Links

Avalon-ST Data Interface Clocks, Intel FPGA Low Latency Ethernet 10G MAC UserGuide

7.4 PHY Interface Signals

Table 23. PHY Interface Signals


rx_serial_data In 2 RX serial input data

tx_serial_data Out 2 TX serial output data

7.5 Status Interface

Table 24. Status Interface Signals


led_link

block_lock

Out Asserted when the link synchronization is successful.

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https://www.altera.com/documentation/bhc1395127830032.html#qvk1471920953837



rx_block_lock

led_an

ethernet_1g_an

Out Asserted when auto-negotiation is completed.

led_char_err

ethernet_1g_char_err

Out Asserted when a 10-bit character error is detected in the RX data.

led_disp_err

ethernet_1g_disp_err

Out Asserted when a 10-bit running disparity error is detected in the RX data.

channel_ready

channel_tx_ready

channel_rx_ready

tx_ready_export

rx_ready_export

Out Asserted when the channel is ready for data transmission.

atx_pll_locked Out Asserted when the TX PLL is locked.

7.6 IEEE 1588v2 Timestamp Interface Signals

Table 25. IEEE 1588v2 Timestamp Interface Signals


tx_egress_timestamp_96b_valid Out [NUM_CHANNELS] When asserted, this signal qualifies thetimestamp,tx_egress_timestamp_96b_data[], and the fingerprint,tx_egress_timestamp_96b_fingerprint[], of the TX frame.

tx_egress_timestamp_96b_data Out [NUM_CHANNELS][96] Carries the 96-bit egress timestamp inthe following format:• Bits 48 to 95: 48-bit seconds field• Bits 16 to 47: 32-bit nanoseconds

field• Bits 0 to 15: 16-bit fractional

nanoseconds field

tx_egress_timestamp_96b_fingerprint

Out [NUM_CHANNELS][TSTAMP_FP_WIDTH]

Specifies the fingerprint of the TXframe that the 96-bit timestamp is for.

tx_egress_timestamp_64b_valid Out [NUM_CHANNELS] When asserted, this signal qualifies thetimestamp,tx_egress_timestamp_64b_data[], and the fingerprint,tx_egress_timestamp_64b_fingerprint[], of the TX frame.

tx_egress_timestamp_64b_data Out [NUM_CHANNELS][64] Carries the 64-bit egress timestamp inthe following format:• Bits 16 to 63: 48-bit nanoseconds


nanoseconds field

tx_egress_timestamp_64b_fingerprint

Out [NUM_CHANNELS][TSTAMP_FP_WIDTH]

Specifies the fingerprint of the TXframe that the 64-bit timestamp is for.

continued...


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rx_egress_timestamp_96b_valid Out [NUM_CHANNELS] When asserted, this signal qualifies thetimestamp,rx_ingress_timestamp_96b_data[]. The MAC IP core asserts thissignal in the same clock cycle it assertsavalon_st_rx_startofpacket.

rx_egress_timestamp_96b_data Out [NUM_CHANNELS][96] Carries the 96-bit ingress timestamp inthe following format:• Bits 48 to 95: 48-bit seconds field• Bits 16 to 47: 32-bit nanoseconds


nanoseconds field

rx_egress_timestamp_64b_valid Out [NUM_CHANNELS] When asserted, this signal qualifies thetimestamp,rx_ingress_timestamp_64b_data[]. The MAC IP core asserts thissignal in the same clock cycle it assertsavalon_st_rx_startofpacket.

rx_egress_timestamp_64b_data Out [NUM_CHANNELS][64] Carries the 64-bit ingress timestamp inthe following format:• Bits 16 to 63: 48-bit nanoseconds


nanoseconds field

Related Links

IEEE 1588v2 Interface Clocks, Intel FPGA Low Latency Ethernet 10G MAC User Guide

7.7 Packet Classifier Interface Signals

Table 26. Packet Classifier Interface Signals


tx_egress_timestamp_request_in_valid[]

In [NUM_CHANNELS] Assert this signal to requesttimestamping for the TX frame.This signal must be asserted inthe same clock cycleavalon_st_tx_startofpacket is asserted.

tx_egress_timestamp_request_in_fingerprint[][]

In [NUM_CHANNELS][TSTAMP_FP_WIDTH]

Use this bus to specify thefingerprint that validates thetimestamp for the incomingpacket.

clock_operation_mode_mode[][] In [NUM_CHANNELS][2] Use this signal to specify theclock mode.• 00: Ordinary clock• 01: Boundary clock• 10: End to end transparent

clock• 11: Peer to peer transparent

clock

pkt_with_crc_mode[] In [NUM_CHANNELS] Use this signal to specifywhether or not a packetcontains CRC.

continued...


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• 0: Packet contains CRC• 1: Packet does not contain

CRC

tx_ingress_timestamp_valid[] In [NUM_CHANNELS] Indicates whether or not theresidence time can be updated.• 0: Prevents update for

residence time• 1: Allows update for

residence time based ondecoded results

When this signal is deasserted,thetx_etstamp_ins_ctrl_out_residence_ti me_updatesignal also gets deasserted.

tx_ingress_timestamp_96b_ data[][]

In [NUM_CHANNELS][96] 96-bit format of ingresstimestamp that holds the dataso that the output can alignwith the start of an incomingpacket.

tx_ingress_timestamp_64b_ data[][]

In [NUM_CHANNELS][64] 64-bit format of ingresstimestamp that holds the dataso that the output can alignwith the start of an incomingpacket.

tx_ingress_timestamp_format[] In [NUM_CHANNELS] The format of the timestampfor calculating the residencetime.• 0: 96 bits• 1: 64 bitsThis signal must be aligned tothe start of an incomingpacket.

7.8 ToD Interface Signals

Table 27. ToD Interface Signal

Signal Direction

Width Description

master_pulse_per_second

Out 1 Pulse per second (PPS) from the master PPS module. Thesignal stay asserted for 10 ms.

start_tod_sync[] In [NUM_CHANNELS] Use this signal to trigger the ToD synchronization process.The time of day of the local ToD is synchronized to the timeof day of the master ToD. The synchronization processcontinues as long as this signal remains asserted.

pulse_per_second_10g[] Out [NUM_CHANNELS] PPS from the 10G PPS module of channel n. The signal stayasserted for 10 ms.

pulse_per_second_1g[] Out [NUM_CHANNELS] PPS from the 1G PPS module of channel n. The signal stayasserted for 10 ms.


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8 Configuration Registers Description

8.1 Register Access

Table 28. Types of Register Access

Access Definition

RO Read only.

RW Read and write.

RW1C Read, and write and clear. The user application writes 1 to the register bit(s) to invoke a definedinstruction. The IP core clears the bit(s) upon executing the instruction.

8.2 Low Latency Ethernet 10G MAC

This topic lists the byte offsets the MAC registers.

Table 29. Primary MAC Address

Byte Offset R/W Name HW Reset

0x2008 RW primary_mac_addr0 0x0

0x200C RW primary_mac_addr1 0x0

Table 30. TX Configuration and Status Registers


0x4000 RW tx_packet_control 0x0

0x4004 RO tx_packet_status 0x0

0x4100 RW tx_pad_control 0x1

0x4200 RW tx_crc_control 0x3

0x4400 RW tx_preamble_control 0x0

0x6004 RW tx_frame_maxlength 0x5EE(1518)

0x4300 RO tx_underflow_counter0 0x0

0x4304 RO tx_underflow_counter1 0x0

Table 31. Flow Control Registers


0x4500 RW tx_pauseframe_control 0x0

0x4504 RW tx_pauseframe_quanta 0x0

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0x4508 RW tx_pauseframe_enable 0x1

0x4680 RW tx_pfc_priority_enable 0x0

0x4600 RW pfc_pause_quanta_0 0x0



0x460C RW pfc_pause_quanta_3 0x0




0x461C RW pfc_pause_quanta_7 0x0

0x4640 RW pfc_holdoff_quanta_0 0x1



0x464C RW pfc_holdoff_quanta_3 0x1




0x465C RW pfc_holdoff_quanta_7 0x1

Table 32. RX Configuration and Status Registers


0x0000 RW rx_transfer_control 0x0

0x0004 RO rx_transfer_status 0x0

0x0100 RW rx_padcrc_control 0x1

0x0200 RW rx_crccheck_control 0x2

0x0400 RW rx_custom_preamble_forward 0x0

0x0500 RW rx_preamble_control 0x0

0x2000 RW rx_frame_control 0x3

0x2004 RW rx_frame_maxlength 0x5EE(1518)

0x2010 RW rx_frame_spaddr0_0 0x0



0x201C RW rx_frame_spaddr1_1 0x0



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0x202C RW rx_frame_spaddr3_1 0x0

0x2060 RW rx_pfc_control 0x1

0x0300 RO rx_pktovrflow_error 0x0

Table 33. TX Timestamp Registers


0x4440 RW tx_period_10G 0x33333

0x4448 RW tx_fns_adjustment_10G 0x0

0x444C RW tx_ns_adjustment_10G 0x0

0x4460 RW tx_period_mult_speed 0x80000

0x4468 RW tx_fns_adjustment_mult_speed 0x0

0x446C RW tx_ns_adjustment_mult_speed 0x0

Table 34. RX Timestamp Registers


0x0440 RW rx_period_10G 0x33333

0x0448 RW rx_fns_adjustment_10G 0x0

0x044C RW rx_ns_adjustment_10G 0x0

0x0460 RW rx_period_mult_speed 0x80000

0x0468 RW rx_fns_adjustment_mult_speed 0x0

0x046C RW rx_ns_adjustment_mult_speed 0x0

Table 35. TX and RX Statistics Registers


0x7000 RO tx_stats_clr 0x0

0x3000 RO rx_stats_clr 0x0

0x7008:0x700C RO tx_stats_framesOK 0x0

0x3008:0x300C RO rx_stats_framesOK 0x0

0x7010:0x7014 RO tx_stats_framesErr 0x0

0x3010:0x3014 RO rx_stats_framesErr 0x0

0x7018:0x701C RO tx_stats_framesCRCErr 0x0

0x3018:0x301C RO rx_stats_framesCRCErr 0x0

0x7020:0x7024 RO tx_stats_octetsOK 0x0

0x3020:0x3024 RO rx_stats_octetsOK 0x0

0x7028:0x702C RO tx_stats_pauseMACCtrl_Frames 0x0

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0x3028:0x302C RO rx_stats_pauseMACCtrl_Frames 0x0

0x7030:0x7034 RO tx_stats_ifErrors 0x0

0x3030:0x3034 RO rx_stats_ifErrors 0x0

0x7038:0x703C RO tx_stats_unicast_FramesOK 0x0

0x3038:0x303C RO rx_stats_unicast_FramesOK 0x0

0x7040:0x7044 RO tx_stats_unicast_FramesErr 0x0

0x3040:0x3044 RO rx_stats_unicast_FramesErr 0x0

0x7048:0x704C RO tx_stats_multicast_FramesOK 0x0

0x3048:0x304C RO rx_stats_multicast_FramesOK 0x0

0x7050:0x7054 RO tx_stats_multicast_FramesErr 0x0

0x3050:0x3054 RO rx_stats_multicast_FramesErr 0x0

0x7058:0x705C RO tx_stats_broadcast_FramesOK 0x0

0x3058:0x305C RO rx_stats_broadcast_FramesOK 0x0

0x7060:0x7064 RO tx_stats_broadcast_FramesErr 0x0

0x3060:0x3064 RO rx_stats_broadcast_FramesErr 0x0

0x7068:0x706C RO tx_stats_etherStatsOctets 0x0

0x3068:0x306C RO rx_stats_etherStatsOctets 0x0

0x7070:0x7074 RO tx_stats_etherStatsPkts 0x0

0x3070:0x3074 RO rx_stats_etherStatsPkts 0x0

0x7078:0x707C RO tx_stats_etherStatsUndersizePkts 0x0

0x3078:0x307C RO rx_stats_etherStatsUndersizePkts 0x0

0x7080:0x7084 RO tx_stats_etherStatsOversizePkts 0x0

0x3080:0x3084 RO rx_stats_etherStatsOversizePkts 0x0

0x7088:0x708C RO tx_stats_etherStatsPkts64Octets 0x0

0x3088:0x308C RO rx_stats_etherStatsPkts64Octets 0x0

0x7090:0x7094 RO tx_stats_etherStatsPkts65to127Octets 0x0

0x3090:0x3094 RO rx_stats_etherStatsPkts65to127Octets 0x0

0x7098:0x709C RO tx_stats_etherStatsPkts128to255Octets 0x0

0x3098:0x309C RO rx_stats_etherStatsPkts128to255Octets 0x0

0x70A0:0x70A4 RO tx_stats_etherStatsPkts256to511Octets 0x0

0x30A0:0x30A4 RO rx_stats_etherStatsPkts256to511Octets 0x0

0x70A8:0x70AC RO tx_stats_etherStatsPkts512to1023Octets 0x0

0x30A8:0x30AC RO rx_stats_etherStatsPkts512to1023Octets 0x0

0x70B0:0x70B4 RO tx_stats_etherStatPkts1024to1518Octets 0x0

continued...


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0x30B0:0x30B4 RO rx_stats_etherStatPkts1024to1518Octets 0x0

0x70B8:0x70BC RO tx_stats_etherStatsPkts1519toXOctets 0x0

0x30B8:0x30BC RO rx_stats_etherStatsPkts1519toXOctets 0x0

0x70C0:0x70C4 RO tx_stats_etherStatsFragments 0x0

0x30C0:0x30C4 RO rx_stats_etherStatsFragments 0x0

0x70C8:0x70CC RO tx_stats_etherStatsJabbers 0x0

0x30C8:0x30CC RO rx_stats_etherStatsJabbers 0x0

0x70D0:0x70D4 RO tx_stats_etherStatsCRCErr 0x0

0x30D0:0x30D4 RO rx_stats_etherStatsCRCErr 0x0

0x70D8:0x70DC RO tx_stats_unicastMACCtrlFrames 0x0

0x30D8:0x30DC RO rx_stats_unicastMACCtrlFrames 0x0

0x70E0:0x70E4 RO tx_stats_multicastMACCtrlFrames 0x0

0x30E0:0x30E4 RO rx_stats_multicastMACCtrlFrames 0x0

0x70E8:0x70EC RO tx_stats_broadcastMACCtrlFrames 0x0

0x30E8:0x30EC RO rx_stats_broadcastMACCtrlFrames 0x0

0x70F0:0x70F4 RO tx_stats_PFCMACCtrlFrames 0x0

0x30F0:0x30F4 RO rx_stats_PFCMACCtrlFrames 0x0

Related Links

Low Latency Ethernet 10G MAC User GuideFor the description of the MAC registers.

8.3 PHY

This topic lists the byte offsets of the Intel Stratix 10 1G/2.5G/5G/10G Multi-ratevariant registers.

8.3.1 Register Map

You can access the 16-bit/32-bit configuration registers(1) via the Avalon®-MMinterface.

(1) These registers are identical to the Intel Arria® 10 variation of 1G/2.5G/5G/10G Multi-rateEthernet PHY IP core.


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Address Range Usage Register Width Configuration

0x00 : 0x1F 1000BASE-X/SGMII 16

2.5G, 1G/2.5G, 10M/100M/1G/2.5G, 10M/

100M/1G/2.5G/10G, 1G/2.5G/10G

0x400 : 0x41F USXGMII 32 1G/2.5G/5G/10G (USXGMII)

0x461 Serial Loopback 32 1G/2.5G/5G/10G (USXGMII)

8.3.2 Register Definitions

Observe the following guidelines when accessing the registers:

• Do not write to reserved or undefined registers.

• When writing to the registers, perform read-modify-write operation to ensure thatreserved or undefined register bits are not overwritten.

Table 37. Register Definitions

Address Name Description Access HW ResetValue

0x00 control Bit [15]: RESET. Set this bit to 1 to trigger a softreset.The PHY clears the bit when the reset is completed.The register values remain intact during the reset.

RWC 0

Bit[14]: LOOPBACK. Set this bit to 1 to enableloopback on the serial interface.

RW 0

Bit [12]: AUTO_NEGOTIATION_ENABLE. Set this bitto 1 to enable auto-negotiation.Auto-negotiation is supported only in 1GbE.Therefore, set this bit to 0 when you switch to aspeed other than 1GbE.

RW 0

Bit [9]: RESTART_AUTO_NEGOTIATION. Set this bitto 1 to restart auto-negotiation.The PHY clears the bit as soon as auto-negotiation isrestarted.

RWC 0

All other bits are reserved. — —

0x01 status Bit [5]: AUTO_NEGOTIATION_COMPLETE. A value of"1" indicates that the auto-negotiation is completed.

RO 0

Bit [3]: AUTO_NEGOTIATION_ABILITY. A value of"1" indicates that the PCS function supports auto-negotiation.

RO 1

Bit [2]: LINK_STATUS. A value of "0" indicates thatthe link is lost. A value of "1" indicates that the link isestablished.

RO 0


0x02:0x03 phy_identifier The value set in the PHY_IDENTIFIER parameter. RO Value ofPHY_IDEN

TIFIERparameter

continued...


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0x04 dev_ability Use this register to advertise the device abilitiesduring auto-negotiation.

— —

Bits [13:12]: RF. Specify the remote fault.• 00: No error.• 01: Link failure.• 10: Off-line.• 11: Auto-negotiation error.

RW 00

Bits [8:7]: PS. Specify the PAUSE support.• 00: No PAUSE.• 01: Symmetric PAUSE.• 10: Asymmetric PAUSE towards the link partner.• 11: Asymmetric and symmetric PAUSE towards

the link device.

RW 11

Bit [5]: FD. Ensure that this bit is always set to 1. RW 1


0x05(1000BASE-X

mode)

partner_ability The device abilities of the link partner during auto-negotiation.

— —

Bit [14]: ACK. A value of "1" indicates that the linkpartner has received three consecutive matchingability values from the device.

RO 0

Bits [13:12]: RF. The remote fault.• 00: No error.• 01: Link failure.• 10: Off-line.• 11: Auto-negotiation error.

RO 0

Bits [8:7]: PS. The PAUSE support.• 00: No PAUSE.• 01: Symmetric PAUSE.• 10: Asymmetric PAUSE towards the link partner.• 11: Asymmetric and symmetric PAUSE towards

the link device.

RO 0

Bit [6]: HD. A value of "1" indicates that half-duplexis supported.

RO 0

Bit [5]: FD. A value of "1" indicates that full-duplex issupported.

RO 0


0x05 (SGMIImode)

partner_ability The device abilities of the link partner during auto-negotiation.

— —

Bit [11:10]: COPPER_SPEEDLink partner speed:• 00: copper interface speed is 10 Mbps• 01: copper interface speed is 100 Mbps• 10: copper interface speed is 1 Gigabit• 11: reserved

RO 00

Bit [12]: COPPER_DUPLEX_STATUSLink partner capability:

RO 0

continued...


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• 1: copper interface is capable of full-duplexoperation

• 0: copper interface is capable of half-duplexoperation

Bit [14]: ACK. Link partner acknowledge. A value of 1indicates that the device received three consecutivematching ability values from its link partner.

RO 0

Bit [15]: COPPER_LINK_STATUSLink partner status:• 1: copper interface link is up• 0: copper interface link is down

RO 0


0x06 an_expansion The PCS capabilities and auto-negotiation status. — —

Bit [1]: PAGE_RECEIVE. A value of "1" indicates thatthe partner_ability register has been updated. Thisbit is automatically cleared once it is read.

RO 0

Bit [0]: LINK_PARTNER_AUTO_NEGOTIATION_ABLE.A value of "1" indicates that the link partner supportsauto-negotiation.

RO 0

0x07 device_next_page

The PHY does not support the next page feature.These registers are always set to 0.

RO 0

0x08 partner_next_page

RO 0

0x09:0x0F Reserved — — —

0x10 scratch Provides a memory location to test read and writeoperations.

RW 0

Bit [31:16]: Reserved — —

0x11 rev The current version of the PHY IP core. RO Currentversion ofthe PHY


0x12:0x13 link_timer 21-bit auto-negotiation link timer.• Offset 0x12: link_timer[15:0]. Bits [8:0] are

always be set to 0.• Offset 0x13: link_timer[20:16] occupies the lower

5 bits. The remaining 11 bits are reserved andmust always be set to 0.

RW 0

0x14 if_mode Interface Mode Register — —

Bit [0]: SGMII_ENADetermines the PCS function operating mode. Settingthis bit to 1b'1 enables SGMII mode. Setting this bitto 1b'0 enables 1000BASE-X gigabit mode.

RW 0

Bit [1]: USE_SGMII_ANIn SGMII mode, setting this bit to 1b'1 configures thePCS with the link partner abilities advertised duringauto-negotiation. If this bit is set to 1b'0, the PCSfunction should be configured with the SGMII_SPEEDbits.

RW 0

continued...


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Bit [3:2]: SGMII_SPEEDWhen the PCS operates in SGMII mode (SGMII_ENA= 1) and is not programmed for automaticconfiguration (USE_SGMII_AN = 0), the followingencodings specify the speed:• 2'b00: 10 Mbps• 2'b01: 100 Mbps• 2'b10: Gigabit• 2'b11: ReservedThese bits are not used when SGMII_ENA = 0 orUSE_SGMII_AN = 1.

RW 0



0x400 usxgmii_control Control Register — —

Bit [0]: USXGMII_ENA:• 0: 10GBASE-R mode• 1: USXGMII mode

RW 0

Bit [1]: USXGMII_AN_ENA is used whenUSXGMII_ENA is set to 1:• 0: Disables USXGMII Auto-Negotiation and

manually configures the operating speed with theUSXGMII_SPEED register.

• 1: Enables USXGMII Auto-Negotiation, andautomatically configures operating speed with linkpartner ability advertised during USXGMII Auto-Negotiation.

RW 1

Bit [4:2]: USXGMII_SPEED is the operating speed ofthe PHY in USXGMII mode and USE_USXGMII_AN isset to 0.• 3’b000: Reserved• 3’b001: Reserved• 3’b010: 1G• 3’b011: 10G• 3’b100: 2.5G• 3’b101: 5G• 3’b110: Reserved• 3’b111: Reserved

RW 0


Bit [9]: RESTART_AUTO_NEGOTIATIONWrite 1 to restart Auto-Negotiation sequence The bitis cleared by hardware when Auto-Negotiation isrestarted.

RWC 0


0x401 usxgmii_status Status Register — —


Bit [2]: LINK_STATUS indicates link status forUSXGMII all speeds• 1: Link is established• 0: Link synchronization is lost, a 0 is latched

RO 0

continued...


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Bit [5]: AUTO_NEGOTIATION_COMPLETEA value of 1 indicates the Auto-Negotiation process iscompleted.

RO 0


0x402:0x404 Reserved — — —

0x405 usxgmii_partner_ability

Device abilities advertised to the link partner duringAuto-Negotiation

— —


Bit [7]: EEE_CLOCK_STOP_CAPABILITYIndicates whether or not energy efficient Ethernet(EEE) clock stop is supported.• 0: Not supported• 1: Supported

RO 0

Bit [8]: EEE_CAPABILITYIndicates whether or not EEE is supported.• 0: Not supported• 1: Supported

RO 0

Bit [11:9]: SPEED• 3'b000: 10M• 3'b001: 100M• 3'b010: 1G• 3'b011: 10G• 3'b100: 2.5G• 3'b101: 5G• 3'b110: Reserved• 3'b111: Reserved

RO 0

Bit [12]: DUPLEXIndicates the duplex mode.• 0: Half duplex• 1: Full duplex

RO 0

Bit [13]: Reserved — —

Bit [14]: ACKNOWLEDGEA value of 1 indicates that the device has receivedthree consecutive matching ability values from its linkpartner.

RO 0

Bit [15]: LINKIndicates the link status.• 0: Link down• 1: Link up

RO 0


0x406:0x411 Reserved — — —

0x412 usxgmii_link_timer

Auto-Negotiation link timer. Sets the link timer valuein bit [19:14] from 0 to 2 ms in approximately 0.05-ms steps. You must program the link timer to ensurethat it matches the link timer value of the externalNBASE-T PHY IP Core.

[19:14]:RW

[13:0]: RO

[19:14]:1F

[13:0]: 0

continued...


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The reset value sets the link timer to approximately1.6 ms.Bits [13:0] are reserved and always set to 0.


0x461 phy_serial_loopback

Configures the transceiver serial loopback in the PMAfrom TX to RX.

— —

Bit [0]• 0: Disables the PHY serial loopback• 1: Enables the PHY serial loopback

RW 0


Related Links

Intel Stratix 10 Multi-rate Ethernet PHY IP CoreFor detailed description of the configuration registers of the 1G/2.5G/5G/10G PHYIP.

8.4 Transceiver Reconfiguration

Table 38. Transceiver Reconfiguration Register Map

WordOffset Name Bits Description Access HW Reset

0x00 logical_channel_number

[9:0] The logical number of the reconfiguration block. RW 0x000

[31:10] Reserved

0x01 control [1:0] Specify the new operating speed:• 00: 1 Gbps• 01: 2.5 Gbps• 10: Reserved• 11: 10 Gbps

RW 0x00

[15:2] Reserved — 0x000

[16] Writing 1 to this bit when it is 0 starts thereconfiguration process. The bit clears when theprocess is completed.

RWC 0x0

[31:17] Reserved — 0x000000

0x02 status [0] When set to 1, indicates the reconfigurationprocess is in progress.

RO 0x0

[31:1] Reserved — —

8.5 TOD

Table 39. TOD Register Map

Byte Offset Name Bits Description Access HW Reset

0x0000 SecondsH [15:0] The upper 16 bits of the second field. RW 0x0

[31:16] Reserved. — —

continued...


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https://www.altera.com/documentation/dto1486572140811.html#dvf1486572597904

Byte Offset Name Bits Description Access HW Reset

0x0004 SecondsL 32 The lower 32 bits of the second field. RW 0x0

0x0008 NanoSec 30 The nanosecond field. RW 0x0

0x0010 Period [15:0] The time of day. The period in fractionalnanosecond.

RW n (2)

[19:16] The time of day. The period in nanosecond.

[31:20] Reserved. — —

0x0014 AdjustPeriod

[15:0] The offset adjustment period. The period infractional nanosecond.

RW 0x0

[19:16] The offset adjustment period. The period innanosecond.

[31:20] Reserved. — —

0x0018 AdjustCount

[19:0] The number of adjusted period in clock cycles. RW 0x0

[31:20] Not used. — —

(2) The default value for the period depends on the frequency of the PHY speed. For example, iffrequency is 125 MHz, the period is 8 ns (PERIOD_NS = 0x0008 and PERIOD_FNS = 0x0000).


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9 Document Revision History for Intel FPGA Low LatencyEthernet 10G MAC Design Example User Guide for IntelStratix 10 Devices

Document Version Intel QuartusPrime Version

Changes

2018.03.28 17.1 • Updated Figure: Clocking Scheme for 10G USXGMII Ethernet DesignExample.

Date Version Changes

November 2017 2017.12.04 • Updated Figure: Example Design Tab.• Added Hardware Testing, Test Cases, and Debug Signals topics for the

10BASE-R Ethernet Design Examplechapter.• Updated the description in the Hardware Testing topic for the following

Ethernet design examples:— 10M/100M/1G/2.5G/10G— 1G/2.5G with IEEE 1588v2 Feature— 1G/2.5G/10G with IEEE 1588v2 Feature— 10G USXGMII

• Added Changing to SFP+ Setting topic for 1G/2.5G/10G Ethernetdesign example with IEEE 1588v2 Feature chapter.

• Made editorial text and structure update.

2017.11.06 • Rebranded as Intel.• Renamed the document as Intel FPGA Low Latency Ethernet 10G MAC

Design Example User Guide for Intel Stratix 10 Devices.• Updated the Quick Start Guide section:

— Updated the "Directory and File Description" table.— Removed rtl directory from the "Directory and File Description"

table.— Changed heading title of the Design Parameters Description topic to

Design Example Parameters.— Updated the "Parameters in the Example Design Tab" table:

• Added Analog Voltage and Enable ADME support parametersand descriptions.

• Updated the descriptions for Generate File Format and SelectBoard parameters.

— Updated the Procedure subtopic under the Compiling and Simulatingthe Design topic.

— Updated the Procedure subtopic under the Compiling and Testingthe Design in Hardware topic.

• Updated entire 1G/2.5G/10G Ethernet Design Example chapter to 10M/100M/1G/2.5G/10G Ethernet Design Example chapter.

• Updated the 1G/2.5G Ethernet Design Example with IEEE 1588v2Feature for Intel Stratix 10 Devices topic.

• Added 10G USXGMII Ethernet Design Example chapter.• Added 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2

Feature chapter.

continued...

UG-20073 | 2018.03.28







• Updated the description in the "Features" topic for the 10GBASE-R,10M/100M/1G/2.5G/10G, 1G/2.5G with IEEE 1588v2 Feature, 1G/2.5G,1G/2.5G/10G with IEEE 1588v2 Feature, and 10G USXGMII ethernetdesign examples.

• Updated the "Design Component" table for the 10GBASE-R, 10M/100M/1G/2.5G/10G, 1G/2.5G with IEEE 1588v2 Feature, 1G/2.5G, 1G/2.5G/10G with IEEE 1588v2 Feature, and 10G USXGMII ethernetdesign examples.

• Updated the Hardware and Software Requirements topic for the10GBASE-R, 10M/100M/1G/2.5G/10G, 1G/2.5G with IEEE 1588v2Feature, 1G/2.5G, 1G/2.5G/10G with IEEE 1588v2 Feature, and 10GUSXGMII ethernet design examples.

• Updated Figures:— Example Design Tab— Block Diagram of the Hardware Setup— Block Diagram—10GBASE-R Design Example— Clocking and Reset Scheme for 10GBASE-R Design Example— Clocking Scheme for 10M/100M/1G/2.5G/10G Ethernet Design

Example— Reset Scheme for 10M/100M/1G/2.5G/10G Ethernet Design

Example— Clocking Scheme for 1G/2.5G Ethernet Design Example with IEEE

1588v2 Feature— Reset Scheme for 1G/2.5G Ethernet Design Example with IEEE

1588v2 Feature— Interface Signals of the 1G/2.5G Ethernet Design Example with IEEE

1588v2 Feature— Clocking Scheme for 1G/2.5G/10G Ethernet Design Example with

IEEE 1588v2 Feature— Reset Scheme for 1G/2.5G/10G Ethernet Design Example with IEEE

1588v2 Feature— Interface Signals of the 1G/2.5G/10G Ethernet Design Examples

with IEEE 1588v2 Feature— Clocking Scheme for 10G USXGMII Ethernet Design Example— Reset Scheme for 10G USXGMII Ethernet Design Example— Interface Signals of the 10G USXGMII Ethernet Design Example

• Updated the "RX Configuration and Status Registers" table: Updatedthe HW Reset value for 0x2004 from 1518 to 0x5EE(1518).

• Updated the Configuration Registers Description chapter:— Updated the PHY topic:

• Removed the "PMA Registers", "PCS Registers", and "Stratix 10GMII PCS Registers" tables.

• Added Register Map and Register Definitions subtopics.— Merged the 10G TOD and 1G TOD topics with the Master TOD and

changed heading title to ToD.— Updated "ToD Register Map" table: Added bits information.

• Made text updates throughout the document.

May 2017 2017.05.08 • Updated the Procedure topic in the Quick Start Guide chapter.• Added the Compiling and Testing the Design in Hardware topic in the

Quick Start Guide chapter.• Updated the Software Requirements topic in the 10GBASE-R Design

Example for Stratix 10 chapter.• Updated the Register Map table in the 10GBASE-R Design Example for

Stratix 10 chapter.• Updated the Clocking and Reset Scheme for 10GBASE-R Design

Example figure.• Added 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature

chapter.• Added 1G/2.5G/10G Ethernet Design Example chapter.

continued...

9 Document Revision History for Intel FPGA Low Latency Ethernet 10G MAC Design ExampleUser Guide for Intel Stratix 10 Devices

UG-20073 | 2018.03.28



• Added Interface Signals Description for Stratix 10 chapter.• Added Configuration Registers Description for Stratix 10 chapter.• Updated the description for csr_clk signal in the Clock and Reset

Interface Signals table.• Editorial fix to the Interface Signals and Configuration Registers topics

for 10GBASE-R Design Example chapter.• Updated document part number from UG-20016-S10 to UG-20073.

October 2016 2016.10.31 Initial release.

9 Document Revision History for Intel FPGA Low Latency Ethernet 10G MAC Design ExampleUser Guide for Intel Stratix 10 Devices

UG-20073 | 2018.03.28


Documents

Intel FPGA Low Latency Ethernet 10G MAC Design Example ... · 1 Quick Start Guide ... Intel FPGA Low Latency Ethernet 10G MAC Design Example User Guide for Intel Stratix 10 Devices