Integrated Circuits Laboratory Faculty of Engineering 28-January-2003 Decimation Filter A Design Perspective Presented by: Sameh Assem Ibrahim

Integrated Circuits Laboratory

Faculty of Engineering

28-January-2003

Decimation FilterDecimation FilterA Design PerspectiveA Design Perspective

Presented by: Sameh Assem Ibrahim

2/36 Integrated Circuits Laboratory


What is Decimation ?What is Decimation ?

Two types of sampling rate conversion

- Interpolation when F’ > F or T’ < T (inserting L-1 equidistant zero-valued samples between two consecutive samples of x[n] )

- Decimation when F’ < F or T’ > T (keeping every M-th sample of x[n] and removing M-1 in-between samples to generate y[m])

Decimation factor M

M = F’/F <1

A block diagram representation

Mx[n] y[m]



The Use of Decimation in ΣΔ ADCThe Use of Decimation in ΣΔ ADC

ΣΔ loopsAnalog

inputDecimator

Digital

FS

Analog

Output FN

FS is the high sampling rate used in the ΣΔ modulator

FN is the Nyquist Sampling Rate = 2 Fmax

FS >> FN

FS/FN = M

-1--1-

1 bit Multiple bits



The Use of Decimation in ΣΔ ADCThe Use of Decimation in ΣΔ ADC

Converts ΣΔ bits stream into PCM data of required resolution (16 bits in our case)

Reduces the sampling rate to Nyquist rate. This helps in:

* Preventing inefficient use of bandwidth

* Reduced speed of operation in the following circuits

Suppresses out of band noise

-2--2-



Can we just Decrease the Sampling Can we just Decrease the Sampling Rate? Rate?

ω

X(j ω)

-2πFmax 0 2πFmax 2πFS4πFS

FS > 2 Fmax

ω

X(j ω)

-2πFmax 0 2πFmax

2πFS 4πFS

FS < 2 Fmax

6πFS 8πFS 10πFS12πFS

Aliasing

-1--1-



Can we just Decrease the Sampling Can we just Decrease the Sampling Rate? Rate?

ω

X(j ω)

0

-2--2-

2πFS4πFS

ΣΔ (FS >> 2 Fmax)

2πFN

4πFN

6πFN

No Problem if FS is integer multiples of

FN

Really??

ω

X(j ω)

0 2πFS4πFS

ΣΔ (FS >> 2 Fmax)

πFS

Noise shaped by ΣΔ

2πFNProblem



Can we just Decrease the Sampling Can we just Decrease the Sampling Rate?Rate?

A decimation filter is needed

Design of a decimator is the design of its decimation filter

Decimation filter is a digital filter

It must have zeros at the integer multiples of the new sampling rate

The Block diagram including the filter

--33--

Mx[n] y[m]h[n]y[n]



Digital Filters BackgroundDigital Filters BackgroundThe Z-transformThe Z-transform

Z-transform is the discrete time counterpart of the Laplace transform

Used in the analysis of LTI systems

Used in the study of stability of a filter

n

nz]n[x)z(X

)z(X)z(H)z(Y

k

]k[h

Unit circle

Re{z}

Im{z}



Digital Filters BackgroundDigital Filters BackgroundSome Z-transform PropertiesSome Z-transform Properties

Linearity

Time shifting

Scaling in the z-domain

Time expansion

Convolution

First difference

Accumulation

)z(bX)z(aX]n[bx]n[ax 2121

)z(Xz]nn[x ono

)ze(X]n[xe oo ωjnωj

)z

z(X]n[xz

o

no

)z(Xrkn,0

rkn],r[x]n[x k

)k(

)z(X)z(X]n[x*]n[x 2121

)z(X)z1(]1n[x]n[x 1

)z(Xz1

1]k[x

1k



Digital Filters BackgroundDigital Filters BackgroundThe Discrete Fourier TransformThe Discrete Fourier Transform

Discrete Fourier transform is the discrete time counterpart of the continuous time Fourier transform

In z-domain:

Put r=1:

Used in estimating the frequency response of a filter

ωjrez

n

nωjωj e]n[x)e(X]}n[x{F

ωde)e(Xπ2

1)}e(X{F]n[x nωj

π2

ωjωj1



Digital Filters BackgroundDigital Filters BackgroundSignal Flow Graphs Basic ElementsSignal Flow Graphs Basic Elements

Operation SymbolTime domain Description

Frequency domain Description

Unit delay x[n] z-1 y[n] y[n]=x[n-1]

M-sample delay x[n] z-M y[n] y[n]=x[n-M]

Gain x[n] c y[n] y[n]=cx[n]

Gain and delay x[n] cz-1 y[n] y[n]=cx[n-1]

Sampling rate compressor

x[n] y[m]y[m]=x[Mm]

Sampling rate expander

x[n] y[m]

Input branch x[n] -- --

Output branch y[n] -- --

M

L

)e(Xe)e(Y ωjωjωj

)e(Xe)e(Y ωjωjMωj

)e(cX)e(Y ωjωj

)e(Xce)e(Y ωjωjωj

otherwise0

,..L2,L,0m]L/m[x]m[y )e(X)e(Y Lωjωj

1M

0l

M/)lπ2ω(jωj )e(XM

1)e(Y



Digital Filters BackgroundDigital Filters BackgroundSignal Flow Graphs OperationsSignal Flow Graphs Operations

x1[n]

x2[n] y[n]=x1[n]+x2[n]+x3[n]

y3[n]=x[n]

x3[n]

x[n]y1[n]=x[n]

y2[n]=x[n]

z-1

c1 c2

x[n] y[n]

y[n]=x[n]+c2x[n-1]+c1y[n-1]



Digital Filters BackgroundDigital Filters BackgroundBasic Elements ImplementationsBasic Elements Implementations

Delay units are implemented as D-FFs

Gain units are implemented as digital multipliers implemented in VHDL or through ALUs

Coefficients to be multiplied with are either stored in a ROM or have a generating digital circuitry if they have an easily implemented function

Adding branches can be done using VHDL adders or ALUs

Accumulators and first difference



Digital Filters BackgroundDigital Filters BackgroundSignal Flow CommutationSignal Flow Commutation

Two branch operations commute if the order of their cascade operation can be interchanged without affecting the input-to-output response of the cascaded system.



Digital Filters BackgroundDigital Filters BackgroundFIR vs. IIR FiltersFIR vs. IIR FiltersFIR IIR

The impulse response is non-zero for N samples only

The impulse response duration is infinite

They don’t contain any poles in the z-domain

Have both poles and zeros in the z-domain

Have no continuous time counterpart

Are easily derived from continuous time filters

Linear phase can be easily achieved

Linear phase can only be approximated

Always stable Must be checked for stability

Coefficients can be rounded to reasonable word lengths

This will result in large quantization noise

Higher order than IIR is always required

IIR filters are generally very efficient

Most Implemented ΣΔ ADCs use FIR implementation



Decimation Filter RealizationDecimation Filter Realization

Structures used can be classified into:

1. Direct Form Structures

2. Polyphase structures

3. Structures with time varying coefficients

Each of these can be implemented using FIR or IIR filters.

The choice depends on the application used

Structures 3 are particularly useful when considering conversion by factors of L/M (not our case)

Structures 1 and 2 can both be used



FIR Direct Form StructuresFIR Direct Form Structures

A direct implementation of the convolution equation

In many applications the FIR filter is designed to have linear phase

Consequently, the impulse response is symmetric

1

0

][][][N

k

knxkhny

]1[][ kNhkh



FIR Direct Form Structures for FIR Direct Form Structures for DecimatorsDecimators

Multiplications and additions are done at the low sampling frequency

1

0

][][][N

n

nMmxnhmy



Polyphase FIR Structures for Polyphase FIR Structures for DecimatorsDecimators

Savings of a factor of M in the storage requirements can be achieved by proper design of filters



Single Stage vs. Multiple Stages Single Stage vs. Multiple Stages

If M can be factored into the product

Then Decimation can be done in stages

I

iiMM

1

M1x[n] y[m]h[n] M2

FSFS FS/M1

FS/M1M2=FS/M

No Advantage



Filter Design ProcedureFilter Design Procedure

Most implemented ΣΔ ADCs use a two stages decimation filter

1st Stage

A Comb (sinck) Filter

2nd Stage

An FIR filter with symmetric

coefficients

The first stage is realized as a direct form structure

Reduces the sampling rate to 1/16 FS

Introduces zeros around multiples of the new sampling frequencies

These frequencies would alias into the required band and thus increases noise

The 2nd stage reduces sampling rate to the Nyquist frequency

Provides the sharp filtering necessary to reduce the frequency aliasing effect

Provides the passband response compensation for the droop introduced by the “comb-filter”

Provides linear phase relationship



Design of the Comb FilterDesign of the Comb Filter

A comb-filter of length M is an FIR filter with all M coefficients equal to one.

The transfer function of a comb-filter is

The filter is a simple accumulator which performs a moving average.

Using the formula for a geometric sum

-1--1-

)(

)()(

1

0 zX

zYzzH

M

n

n

)(

)(

1

1)(

1 zX

zY

z

zzH

M




This can be written as

Using commutation

-2--2-

Mzz

zXzY

1

1

1)()(

1

MX[z] Y(z)11

1 z

Mz 1

MX[z] Y(z)11

1 z

11 z



Design of the Comb FilterDesign of the Comb Filter-3--3-

The accumulation is done at the higher rate

The differentiation is done at the lower rate

2 registers only are required regardless of M

The filter should be properly scaled for unity gain. This can be done by dividing over M

The two’s complement number system should be used to avoid overflowing

MX[z] Y(z)11

1 z

11 z




The advantages of a comb filter are

1. No multipliers are required

2. No storage is required for filter coefficients

3. Intermediate storage is reduced by integrating at the high sampling rate and differentiating at the low sampling rate, compared to the equivalent implementation using cascaded uniform FIR filters

4. The structure of comb-filters is very “regular”

5. Little external control or complicated local timing is required

6. The same filter design can easily be used for a wide range of rate change factors, M, with the addition of a scaling circuit and minimal changes to the filter timing

-4--4-




A single comb filter will not give enough stop band attenuation

Cascaded comb filters can often meet requirements

The frequency response of a properly scaled M stage comb filter can be written as

-5--5-

NM

N

zz

)z(X)z(Y

1

1

11

N

S

SS )F/f(csin

)F/Mf(csin)F/f(H

M

FS/M4 cascaded comb filters



Design of the Comb FilterDesign of the Comb Filter-6--6-



Design of the Second Filter StageDesign of the Second Filter Stage

Better to be designed in two low pass filter stages

Stage 1 for the compensation of the droop in the passband introduced by the comb filter

Stage 2 gives the final decimation ratio and provides for the required attenuation in the stop band

MATLAB filter design and analysis tool can be used

Stage A

LPF FIR

(Compensator)

Stage B

LPF FIR



Design of the Design of the CompensatorCompensator

Compensates the droop of the comb filter

Decimates by 2Fixed point filter response

Filter specifications: (FIR)

- Stopband slope (60 dB) - 5th order Inverse sinc - Passband, stopband ripple

--11--

21 taps

Symmetric FIR



Design of the Design of the CompensatorCompensator--22--

Comb filter responseCompensation filter response addedCascaded response

Zoom in on passband



Design of the Design of the CompensatorCompensator--33--

zoomed

constant



Design of the Design of the CompensatorCompensator

Realized as polyphase structure

--44--



Design of the Last Filter StageDesign of the Last Filter Stage

Implemented as an FIR LPF

Gives the final attenuation in the stopband requiredFixed point filter response

63 taps

Symmetric FIR

--11--



Design of the Last Filter StageDesign of the Last Filter Stage--22--

Final frequency Response



Design of the Last Filter StageDesign of the Last Filter Stage

Realized as a polyphase filter

--33--



ReferencesReferences

1. R.E.Crochiere, L.R. Rabiner, “Multirate Digital Signal Processing”, Prentice-Hall, 1983

2. J.C.Candy, G.C.Temes, “Oversampling Delta-Sigma Data Converters, Theory, Design and Simulation”, IEEE Press, 1992

3. D.Orifino, “Designing Digital Radio Applications with Simulink®”, The MathWorks, 2002

4. “Principles of Sigma-Delta Modulation for Analog to Digital Converters”, Motorola

Documents

Integrated Circuits Laboratory Faculty of Engineering 28-January-2003 Decimation Filter A Design Perspective Presented by: Sameh Assem Ibrahim