Instruction Set Architectureorca.st.usm.edu/~pghosh/2.Instrunctionset_final.pdfMemory Addressing • Addressing Modes – Register – Immediate – Displacement – Register Indirect

Instruction Set Architecture

Instructor: Preetam GhoshInstructor: Preetam [email protected]

CSC 626/726 Preetam Ghosh

LanguageHLL : High Level Language Program written by Programming language like C, C++, Java.

Sentence a = b + c; d = a – e;

Assembly Language: The Pneumonic translation of Binary code into English Language. One to one correspondence between Binary Language and Assembly language MIPS is thebetween Binary Language and Assembly language. MIPS is the Assembly language used in the book.

Instruction add a, b, csub d, a, e

Binary Code: Language expressed by Binary numbers


y Code: gu ge e p essed by y u be sunderstood by the computer Hardware.

Instruction SetInstruction Set

software

instruction set

hardware


Computer OperationVariablesC Language Sentencecba +=eadcba

−=+=Expression SoftwareSoftware

Assembly Instruction (MIPS)bdd

Operand

eadsubcbaadd

,,,,

InstructionType

SoftwareSoftware

?yp

Function


1.Where is a, b, c, d and e2. Who is doing add and sub

Hardware Software InterfaceSoftwareSoftware

?SoftwareSoftware

?1.Where is a, b, c, d and e2. Who is doing add and subg

Computer ChipComputer ChipMemoryMemory

1

HardwareHardware234

RegisterRegisterALUALU


Data5Address

Hardware Software InterfaceComputer ChipComputer ChipMemoryMemory

1Base Register

a[1] $ 2

HardwareHardware

1234

RegisterRegisterALUALU

a[1]a[2]a[3]a[4]

$s2$s3

Data b45

Address

??

[ ]

??1. Where is Data

In Memory (a[1-4], b) Starting address at Base RegisterBase Registerfor an arrayIn Registers ($s2, $s3,…,$t0) Explicit address

2 Who Transfers Data between Memory and Registers


2. Who Transfers Data between Memory and Registers3. Who is the Controller of ALU

HLL to HardwareC Language statementC Language statement

[ ] [ ]812 AhA +=A: Arrayh: variable

A[8] A[8]=$s3+32

$s4

$s3 Base Register: address ofA[0]A[12]

variable h

A[12]=$s3+48$t0

MIPS InstructionMIPS Instruction( )

4 B t d t (32 bit )

( )

( )420

32

,$,$$$32,$

sstaddsslw


4 Bytes per data (32 bits) ( )30 $48,$ stsw

Machine Representation( )( )

020

30

,$,$$$32,$

tstaddstlw

( )30 $48,$ stswMachine is in Binary, but this expressions are not in binaryy, p yWe need Binary Translation. Machine LanguageMachine Language

Op Code (6) rs (5) rt (5) rd (5) shamt(5) function(6)

Op CodeOp Code: Operation of the instructionrsrs: The first source operand registertt Th d d i trtrt: The second source operand register

rdrd: Destination operand register. Gets results of the operationshamtshamt: Shift amount for shift instruction


functionfunction: Selects the functions within a opcode field.

Hexadecimal$$$dd

000000 10001 10010 01000 00000 100000

210 ,$,$$ sstadd

It is difficult to remember this large binary sequence.Hexadecimal conversion is used. It is a number system to the base 16.S 4 bit t b l d th 16 b lSo 4 bits represent one symbol and there are 16 symbols.

2

0001100000 =hex 0000 0010 0011 0010 0100 0000 0010 0000

2

2

1001900011

==

hex

hex 0 2 3 2 8 0 2 0

2

*1010=hexa 02328020hex

CSC 626/726 Preetam Ghosh21111=hexf

Instruction Set ArchitectureInstruction Set Architecture

• A computer architect must decide on the setA computer architect must decide on the set of instructions that are executable in hardware on their designed machine.g

• These instructions must:– satisfy the design goals of the target machine in y g g g

terms of cost and performance, and– support all the language constructs specified in

hi h l l bl l l l ba high-level or assembly-level language to be run on the target machine.


Instruction Set Architecture • A good interface:• A good interface:

–Lasts through many implementations (portability, compatibility)p y)–Is used in many different ways (generality)

–Provides convenient functionality to higher levels


y g–Permits an efficient implementation at lower levels

Architecture ThrustSome Important Questions:1. What is the nature of the programs

1. Simplicity Tanenbaump y2. Structured3. Integer or floating points

2 High Level Language Mapping (CISC)

Tanenbaum

2. High Level Language Mapping (CISC)1. Simplify compilation by easy mapping to instruction2. How to reduce code size VAX

3. Memory Size1. Moore’s Law on memory growth, memory addressing2. Memory limitation of embedded systemy y

Semantic Gap: Gap between High Level Language and Computer Architecture


Computer Architecture

Instruction set ArchitectureInstruction set ArchitectureOPCODE Operand-1 Operand-2 Operand-3

? : Where are these operandsWhat types of operandsHow to get access to these operands

1 Stack All operations on a Stack Operand Implicit

How to get access to these operands

1. Stack All operations on a Stack. Operand Implicit

2. Accumulator One operand and Result on Accumulator

3. Register-Memory Operand on Register and on Memory


4. Load-Store All Operand on explicit GPR

Evolution of Instruction Sets

Single Accumulator (EDSAC 1950)

Accumulator + Index Registers(Manchester Mark I, IBM 700 series 1953)

Separation of Programming Modelfrom Implementation

Hi h l l L B d C t f F ilHigh-level Language Based Concept of a Family(B5000 1963) (IBM 360 1964)

General Purpose Register Machines

Stack Processor Register-Memory

Complex Instruction Sets (CISC)


(VAX, Intel 1977-80)

History of STACK Processor

1965 : Burroughs B5000 stack processor for programminglanguage ALGOL TOS NTOS are only HW Registerlanguage ALGOL. TOS,NTOS are only HW Register

1968 : Burroughs B6500

1964-70: IBM & DEC’s ArgumentsStack machine performance depends on register speed, memory speed. There are too many copy operations.Intel 80x86 uses stack for floating point operation

1990: Proposal of Java Virtual Machine on Stack. No commercialimplementation.


Evolution of Instruction Sets• Unfortunately, there are no standards to follow in

designing an instruction set.designing an instruction set.• The trend up to early 80’s was based on the CISC(Complex

Instruction Set Computers) instruction set design p ) gphilosophy:–include many instructions in the set,–have complex instructions that carry out the job of several simpler instructions (e.g., loop instruction),–have many instruction formats and addressing modes,–have many different kinds of registers,


y g–...

Evolution of Instruction Sets• A CISC architecture causes:

–Size of the machine language programs?–Size of the machine language programs?• simpler (smaller) with less number of instructions to execute.

–Complexity of the machine architecture?p y• more complex (due to complex instructions), requiring more time for

execution of each instruction.

C il ti i ti ?–Compiler optimizations?• more complex (due to many choices in deciding which instructions and/or

addressing modes to use).


Evolution of Instruction Sets• Since the early 80’s the trend for new ISA design has been

based on the RISC(Reduced Instruction Set Computers)based on the RISC(Reduced Instruction Set Computers) instruction set design philosophy:

–Simplicity favors regularity• all instructions are of the same size• all instructions of the same type follow the same format


Evolution of Instruction Sets• RISC ISA design philosophies:

–Smaller is faster–Smaller is faster• small number of instructions• relatively small number of register types

–Good design demands compromise• only a few instruction formats to handle special needs

–Make the common case fast• most often executed instructions or heavily used features need to be

optimizedp

–Pipelining, single-cycle execution, compiler technology, etc.


Advantages & Disadvantages of different Instruction Architecture

Architecture Advantages Disadvantages

Si l di O d O d b i d iStack

Simple encoding,Operand and result Location fixed

Operand must be in correct order in the Stack.Operand has to be loaded on stack

AccumulatorSimple instruction as only oneOperand to be specified

Operation must be in correct order Have the correct operand onaccumulator

Register-MemoryLeast number of instruction Complex instruction set. Decoding

is complex. Potential of variablel th i t ti

LoadLoad--StoreStore

length instruction

Operand on Register, operandcan be used without additional

Larger Instruction and encodingcomplexity


instruction.

Re-look at Instruction set design-RISC

1980s : Ditzel & Patterson : RISC (Reduced Instruction Set)ArchitectureResearch OutputsResearch Outputs

1. 1975 IBM 801Project: Eckert Cocke .ECL based 24 bit registers not commercialized.

1 1980 B k l RISC I d RISC II P tt ’ t1. 1980 Berkeley : RISC-I and RISC –II: Patterson’s team, MOS based 32 bit registers. Targeted towards Smalltalk and LISP.

3. 1981 Stanford : MIPS Computer; Hennessy published explanation of RISC advantages over VAX

4. 1986 : HP converted its Minicomputer to RISC (HP4. 1986 : HP converted its Minicomputer to RISC (HP Precision Architecture)

5. 1987 : SUN SPRAC based on RISC-II6 1990 IBM RISC RS 6000


6. 1990 : IBM RISC RS 60007. 1998 : Alpha based MIPS 2000



Interpreting Address1. Little Endian(PDP-11,Intel 80x86)

07(PDP 11,Intel 80x86)2. Big Endian(IBM360/370,Motorola)

70

AlignmentByte Address : AyObject size : sByte address oriented memory will align if Mod[A,s] = 0

Addressing ModeEffective Address


PC – Relative addressing: Mainly used for control transfer


Memory Addressing• Addressing Modes

– Registerg– Immediate– Displacement– Register Indirect– Indexed

Di Ab l– Direct or Absolute– Memory Indirect

Autoincrement– Autoincrement– Auto decrement– Scaled


Addressing Modes


Addressing Modes


Addressing Modes


Addressing Modes


DSPDSP: Digital Signal ProcessingDSP: Digital Signal ProcessingSignal processing requires very high capacity to handle real time data.

– Iterative numeric algorithmsU d d h i l i l d l– Use dot products that require multiply and accumulate

– Stringent real time requirements– Streaming data from A/D converter as infinite stream, results to emit in real

time.– High data bandwidth– predictable memory access patternsp y p– Predictable program flow, a set of nested loops– Sensitive to small numeric error

Traditionally these functions were implemented on ASIC


GaAs, InP Technology gives the speed and power efficiency in ASIC. But these are not at present suitable for Chip design. Defect rate: 100+/cm2

DSP replaces ASIC design • Significant cost of custom ASIC design• Significant cost of custom ASIC design

– Custom mask costs millions of dollars– Lapse time high

No design flexibility– No design flexibility• CMOS Silicon Technology advanced to support

– High gate count per cell(100K/mm2)P l l i d f 3 l l 1 l [ P di i i d i– Power level going down from 3 volts to almost 1 volt [ Power dissipation drops in square law]

• Processor Technology for signal processing started making senseC t hit t– Custom processor architecture

– Memory on Chip– New addressing and complex instruction structure

M l i hi– Multi processor architecture• 1980: NEC mPD7710, ATT DSP1• 1982: Texas Instrument TMS32010


• 1997: Texas Instrument TMS320C62xx[VLIW,parallelism,RISC like instruction]

DSP Specialty


Multimedia Media Processor


New Addressing Modes for DSP & Media ProcessorsDSP & Media Processors


Addressing Modes Decisions










Usage of address Modes


Addressing mode of DSP


Operands• Integer• Two’s Complement• Single Precision floating point, Double Precision floating point,

IEEE 754 floating pointCh t (8 bit )• Character: (8 bits)

• Binary• Binary coded decimal or packed decimalBinary coded decimal or packed decimal• 3D type data

– Vertex (x,y,z,w) four components– triangle ( 3-vertices)– pixels 32 bits (RGB and A)

• DSP


• DSP– fixed point
























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Instruction Set Architectureorca.st.usm.edu/~pghosh/2.Instrunctionset_final.pdfMemory Addressing • Addressing Modes – Register – Immediate – Displacement – Register Indirect