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L02-1MIT 6.823 Spring 2020
Daniel SanchezComputer Science & Artificial Intelligence Lab
M.I.T.
Instruction Set Architecture & Hardwired, Non-pipelined ISA
Implementation
February 6, 2020
MIT 6.823 Spring 2020
The IBM 650 (1953-4)
February 6, 2020
[From 650 Manual, © IBM]
Magnetic Drum
(1,000 or 2,000
10-digit decimal
words)
20-digit
accumulator
Active instruction
(including next
program counter)
Digit-serial
ALU
L02-2
MIT 6.823 Spring 2020
Programmer’s view of a machine:IBM 650
February 6, 2020
A drum machine with 44 instructions
Instruction: 60 1234 1009• “Load the contents of location 1234 into the
distribution; put it also into the upper accumulator; set lower accumulator to zero; and then go to location 1009 for the next instruction.”
L02-3
MIT 6.823 Spring 2020
Programmer’s view of a machine:IBM 650
• Programmer’s view of the machine was inseparable from the actual hardware implementation
February 6, 2020
A drum machine with 44 instructions
Instruction: 60 1234 1009• “Load the contents of location 1234 into the
distribution; put it also into the upper accumulator; set lower accumulator to zero; and then go to location 1009 for the next instruction.”
L02-3
MIT 6.823 Spring 2020
Programmer’s view of a machine:IBM 650
• Programmer’s view of the machine was inseparable from the actual hardware implementation
• Good programmers optimized the placement of instructions on the drum to reduce latency!
February 6, 2020
A drum machine with 44 instructions
Instruction: 60 1234 1009• “Load the contents of location 1234 into the
distribution; put it also into the upper accumulator; set lower accumulator to zero; and then go to location 1009 for the next instruction.”
L02-3
MIT 6.823 Spring 2020
Compatibility Problem at IBM
L02-4February 6, 2020
MIT 6.823 Spring 2020
Compatibility Problem at IBM
L02-4February 6, 2020
By early 60’s, IBM had 4 incompatible lines of computers!
701 7094650 7074702 70801401 7010
MIT 6.823 Spring 2020
Compatibility Problem at IBM
L02-4February 6, 2020
By early 60’s, IBM had 4 incompatible lines of computers!
701 7094650 7074702 70801401 7010
Each system had its own• Instruction set• I/O system and Secondary Storage:
magnetic tapes, drums and disks• Assemblers, compilers, libraries,...• Market niche
business, scientific, real time, ...
MIT 6.823 Spring 2020
Compatibility Problem at IBM
L02-4February 6, 2020
By early 60’s, IBM had 4 incompatible lines of computers!
701 7094650 7074702 70801401 7010
Each system had its own• Instruction set• I/O system and Secondary Storage:
magnetic tapes, drums and disks• Assemblers, compilers, libraries,...• Market niche
business, scientific, real time, ...
MIT 6.823 Spring 2020
Compatibility Problem at IBM
L02-4February 6, 2020
By early 60’s, IBM had 4 incompatible lines of computers!
701 7094650 7074702 70801401 7010
Each system had its own• Instruction set• I/O system and Secondary Storage:
magnetic tapes, drums and disks• Assemblers, compilers, libraries,...• Market niche
business, scientific, real time, ...
IBM 360
MIT 6.823 Spring 2020
IBM 360: Design Premises Amdahl, Blaauw, and Brooks, 1964
The design must lend itself to growth and successor machines
• General method for connecting I/O devices
• Total performance - answers per month rather than bits per microsecond programming aids
• Machine must be capable of supervising itself without manual intervention
• Built-in hardware fault checking and locating aids to reduce down time
• Simple to assemble systems with redundant I/O devices, memories, etc. for fault tolerance
• Some problems required floating point words larger than 36 bits
L02-5February 6, 2020
MIT 6.823 Spring 2020
Processor State and Data Types
L02-6February 6, 2020
The information held in the processor at the end of an instruction to provide the processing context for the next instruction.
MIT 6.823 Spring 2020
Processor State and Data Types
L02-6February 6, 2020
The information held in the processor at the end of an instruction to provide the processing context for the next instruction.
Program Counter, Accumulator, ...
MIT 6.823 Spring 2020
Processor State and Data Types
L02-6February 6, 2020
The information held in the processor at the end of an instruction to provide the processing context for the next instruction.
Program Counter, Accumulator, ...
• The information held in the processor will be interpreted as having data types manipulated by the instructions.
MIT 6.823 Spring 2020
Processor State and Data Types
L02-6February 6, 2020
• If the processing of an instruction can be interrupted then the hardware must save and restore the state in a transparent manner
The information held in the processor at the end of an instruction to provide the processing context for the next instruction.
Program Counter, Accumulator, ...
• The information held in the processor will be interpreted as having data types manipulated by the instructions.
MIT 6.823 Spring 2020
Processor State and Data Types
L02-6February 6, 2020
• If the processing of an instruction can be interrupted then the hardware must save and restore the state in a transparent manner
The information held in the processor at the end of an instruction to provide the processing context for the next instruction.
Program Counter, Accumulator, ...
Programmer’s machine model is a contract between the hardware and software
• The information held in the processor will be interpreted as having data types manipulated by the instructions.
MIT 6.823 Spring 2020
Instruction Set
L02-7February 6, 2020
The control for changing the information held in the processor are specified by the instructions available in the instruction set architecture or ISA.
MIT 6.823 Spring 2020
Instruction Set
L02-7February 6, 2020
Some things an ISA must specify:
The control for changing the information held in the processor are specified by the instructions available in the instruction set architecture or ISA.
MIT 6.823 Spring 2020
Instruction Set
L02-7February 6, 2020
Some things an ISA must specify:
The control for changing the information held in the processor are specified by the instructions available in the instruction set architecture or ISA.
MIT 6.823 Spring 2020
Instruction Set
L02-7February 6, 2020
Some things an ISA must specify:• A way to reference registers and memory
The control for changing the information held in the processor are specified by the instructions available in the instruction set architecture or ISA.
MIT 6.823 Spring 2020
Instruction Set
L02-7February 6, 2020
Some things an ISA must specify:• A way to reference registers and memory• The computational operations available
The control for changing the information held in the processor are specified by the instructions available in the instruction set architecture or ISA.
MIT 6.823 Spring 2020
Instruction Set
L02-7February 6, 2020
Some things an ISA must specify:• A way to reference registers and memory• The computational operations available• How to control the sequence of instructions
The control for changing the information held in the processor are specified by the instructions available in the instruction set architecture or ISA.
MIT 6.823 Spring 2020
Instruction Set
L02-7February 6, 2020
Some things an ISA must specify:• A way to reference registers and memory• The computational operations available• How to control the sequence of instructions
• A binary representation for all of the above
The control for changing the information held in the processor are specified by the instructions available in the instruction set architecture or ISA.
MIT 6.823 Spring 2020
Instruction Set
L02-7February 6, 2020
Some things an ISA must specify:• A way to reference registers and memory• The computational operations available• How to control the sequence of instructions
• A binary representation for all of the above
The control for changing the information held in the processor are specified by the instructions available in the instruction set architecture or ISA.
ISA must satisfy the needs of the software:- assembler, compiler, OS, VM
MIT 6.823 Spring 2020
IBM 360: A General-Purpose Register (GPR) Machine• Processor State
– 16 General-Purpose 32-bit Registers
– 4 Floating Point 64-bit Registers
– A Program Status Word (PSW)
• PC, Condition codes, Control flags
L02-8February 6, 2020
MIT 6.823 Spring 2020
IBM 360: A General-Purpose Register (GPR) Machine• Processor State
– 16 General-Purpose 32-bit Registers
– 4 Floating Point 64-bit Registers
– A Program Status Word (PSW)
• PC, Condition codes, Control flags
• Data Formats
– 8-bit bytes, 16-bit half-words, 32-bit words,64-bit double-words
– 24-bit addresses
L02-8February 6, 2020
MIT 6.823 Spring 2020
IBM 360: A General-Purpose Register (GPR) Machine• Processor State
– 16 General-Purpose 32-bit Registers
– 4 Floating Point 64-bit Registers
– A Program Status Word (PSW)
• PC, Condition codes, Control flags
• Data Formats
– 8-bit bytes, 16-bit half-words, 32-bit words,64-bit double-words
– 24-bit addresses
• A 32-bit machine with 24-bit addresses
L02-8February 6, 2020
MIT 6.823 Spring 2020
IBM 360: A General-Purpose Register (GPR) Machine• Processor State
– 16 General-Purpose 32-bit Registers
– 4 Floating Point 64-bit Registers
– A Program Status Word (PSW)
• PC, Condition codes, Control flags
• Data Formats
– 8-bit bytes, 16-bit half-words, 32-bit words,64-bit double-words
– 24-bit addresses
• A 32-bit machine with 24-bit addresses
– No instruction contains a 24-bit address!
L02-8February 6, 2020
MIT 6.823 Spring 2020
IBM 360: A General-Purpose Register (GPR) Machine• Processor State
– 16 General-Purpose 32-bit Registers
– 4 Floating Point 64-bit Registers
– A Program Status Word (PSW)
• PC, Condition codes, Control flags
• Data Formats
– 8-bit bytes, 16-bit half-words, 32-bit words,64-bit double-words
– 24-bit addresses
• A 32-bit machine with 24-bit addresses
– No instruction contains a 24-bit address!
• Precise interrupts
L02-8February 6, 2020
MIT 6.823 Spring 2020
IBM 360: Initial Implementations (1964)
L02-9February 6, 2020
• Six implementations (Models, 30, 40, 50, 60, 62, 70)
• 50x performance difference across models
• ISA completely hid the underlying technological differences between various models
With minor modifications, IBM 360 ISA is still in use
Model 30 . . . Model 70
Memory Capacity 8K - 64 KB 256K - 512 KB
Memory Cycle 2.0µs ... 1.0µs
Datapath 8-bit 64-bit
Circuit Delay 30 nsec/level 5 nsec/level
Registers in Main Store in Transistor
Control Store Read only 1sec Dedicated circuits
MIT 6.823 Spring 2020
IBM 360: Fifty-five years later…z15 Microprocessor
L02-10February 6, 2020
• 9.2 billion transistors, 12-core design
• Up to 190 cores (2 spare) per system
• 5.2 GHz, 14nm CMOS technology
• 64-bit virtual addressing– Original 360 was 24-bit; 370 was a 31-bit extension
• Superscalar, out-of-order– 12-wide issue
– Up to 180 instructions in flight
• 16K-entry Branch Target Buffer– Very large buffer to support commercial workloads
• Four Levels of caches– 128KB L1 I-cache, 128KB L1 D-cache
– 4MB L2 cache per core
– 256MB shared on-chip L3 cache
– 960MB shared off-chip L4 cache
• Up to 40TB of main memory per system
September 2019Image credit: IBM
MIT 6.823 Spring 2020
Instruction Set Architecture (ISA) versus Implementation• ISA is the hardware/software interface
– Defines set of programmer visible state
– Defines data types
– Defines instruction semantics (operations, sequencing)
– Defines instruction format (bit encoding)
– Examples: MIPS, Alpha, x86, IBM 360, VAX, ARM, JVM
L02-11February 6, 2020
MIT 6.823 Spring 2020
Instruction Set Architecture (ISA) versus Implementation• ISA is the hardware/software interface
– Defines set of programmer visible state
– Defines data types
– Defines instruction semantics (operations, sequencing)
– Defines instruction format (bit encoding)
– Examples: MIPS, Alpha, x86, IBM 360, VAX, ARM, JVM
• Many possible implementations of one ISA– 360 implementations: model 30 (c. 1964), z15 (c. 2019)
– x86 implementations: 8086 (c. 1978), 80186, 286, 386, 486, Pentium, Pentium Pro, Pentium-4, Core i7, AMD Athlon, AMD Opteron, Transmeta Crusoe, SoftPC
– MIPS implementations: R2000, R4000, R10000, ...
– JVM: HotSpot, PicoJava, ARM Jazelle, ...
L02-11February 6, 2020
MIT 6.823 Spring 2020
Processor Performance
L02-12February 6, 2020
Time = Instructions Cycles TimeProgram Program * Instruction * Cycle
– Instructions per program depends on source code, compiler technology and ISA
– Cycles per instructions (CPI) depends upon the ISA and the microarchitecture
– Time per cycle depends upon the microarchitecture and the base technology
MIT 6.823 Spring 2020
Processor Performance
L02-12February 6, 2020
Time = Instructions Cycles TimeProgram Program * Instruction * Cycle
Microarchitecture CPI cycle time
Microcoded >1 short
Single-cycle unpipelined 1 long
Pipelined 1 short
– Instructions per program depends on source code, compiler technology and ISA
– Cycles per instructions (CPI) depends upon the ISA and the microarchitecture
– Time per cycle depends upon the microarchitecture and the base technology
MIT 6.823 Spring 2020
Processor Performance
L02-12February 6, 2020
Time = Instructions Cycles TimeProgram Program * Instruction * Cycle
Microarchitecture CPI cycle time
Microcoded >1 short
Single-cycle unpipelined 1 long
Pipelined 1 short
– Instructions per program depends on source code, compiler technology and ISA
– Cycles per instructions (CPI) depends upon the ISA and the microarchitecture
– Time per cycle depends upon the microarchitecture and the base technology
rest ofthis lecture
MIT 6.823 Spring 2020
Hardware Elements
• Combinational circuits– Mux, Demux, Decoder, ALU, ...
L02-13February 6, 2020
MIT 6.823 Spring 2020
Hardware Elements
• Combinational circuits– Mux, Demux, Decoder, ALU, ...
L02-13February 6, 2020
Sel
O
A0
A1
An-1
Mux...
lg(n)
MIT 6.823 Spring 2020
Hardware Elements
• Combinational circuits– Mux, Demux, Decoder, ALU, ...
L02-13February 6, 2020
Sel
O
A0
A1
An-1
Mux...
lg(n)
Sel
O0
O1
On-1
A
Dem
ux
...
lg(n)
MIT 6.823 Spring 2020
Hardware Elements
• Combinational circuits– Mux, Demux, Decoder, ALU, ...
L02-13February 6, 2020
Sel
O
A0
A1
An-1
Mux...
lg(n)
Sel
O0
O1
On-1
A
Dem
ux
...
lg(n)
A
Decoder
...
O0
O1
On-1
lg(n)
MIT 6.823 Spring 2020
Hardware Elements
• Combinational circuits– Mux, Demux, Decoder, ALU, ...
L02-13February 6, 2020
OpSelect
- Add, Sub, ...
- And, Or, Xor, Not, ...- GT, LT, EQ, Zero, ...
Result
Comp?
A
B
ALU
Sel
O
A0
A1
An-1
Mux...
lg(n)
Sel
O0
O1
On-1
A
Dem
ux
...
lg(n)
A
Decoder
...
O0
O1
On-1
lg(n)
MIT 6.823 Spring 2020
Hardware Elements
• Combinational circuits– Mux, Demux, Decoder, ALU, ...
L02-13February 6, 2020
• Synchronous state elements– Flipflop, Register, Register file, SRAM, DRAM
OpSelect
- Add, Sub, ...
- And, Or, Xor, Not, ...- GT, LT, EQ, Zero, ...
Result
Comp?
A
B
ALU
Sel
O
A0
A1
An-1
Mux...
lg(n)
Sel
O0
O1
On-1
A
Dem
ux
...
lg(n)
A
Decoder
...
O0
O1
On-1
lg(n)
MIT 6.823 Spring 2020
Hardware Elements
• Combinational circuits– Mux, Demux, Decoder, ALU, ...
L02-13February 6, 2020
• Synchronous state elements– Flipflop, Register, Register file, SRAM, DRAM
Edge-triggered: Data is sampled at the rising edge
Clk
D
Q
Enff
Q
D
Clk
En
OpSelect
- Add, Sub, ...
- And, Or, Xor, Not, ...- GT, LT, EQ, Zero, ...
Result
Comp?
A
B
ALU
Sel
O
A0
A1
An-1
Mux...
lg(n)
Sel
O0
O1
On-1
A
Dem
ux
...
lg(n)
A
Decoder
...
O0
O1
On-1
lg(n)
MIT 6.823 Spring 2020
Register Files
L02-14February 6, 2020
MIT 6.823 Spring 2020
Register Files
L02-14February 6, 2020
ff
Q0
D0
Clk
Enff
Q1
D1
ff
Q2
D2
ff
Qn-1
Dn-1
...
...
...
register
MIT 6.823 Spring 2020
Register Files
L02-14February 6, 2020
ReadData1ReadSel1
ReadSel2
WriteSel
Register file
2R+1W
ReadData2
WriteData
WEClock
rd1rs1
rs2
ws
wd
rd2
we
ff
Q0
D0
Clk
Enff
Q1
D1
ff
Q2
D2
ff
Qn-1
Dn-1
...
...
...
register
MIT 6.823 Spring 2020
Register Files
L02-14February 6, 2020
No timing issues when reading and writing the same register (writes happen at the end of the cycle)
ReadData1ReadSel1
ReadSel2
WriteSel
Register file
2R+1W
ReadData2
WriteData
WEClock
rd1rs1
rs2
ws
wd
rd2
we
ff
Q0
D0
Clk
Enff
Q1
D1
ff
Q2
D2
ff
Qn-1
Dn-1
...
...
...
register
MIT 6.823 Spring 2020
Register File Implementation
• Register files with a large number of ports are difficult to design– Area scales with ports2
– Almost all Alpha instructions have exactly 2 register source operands
– Intel’s Itanium GPR File has 128 registers with 8 read ports and 4 write ports!!
L02-15February 6, 2020
reg 31
ws clk
reg 1
wd
we
rs1rd1 rd2
reg 0
…
32
…
532 32
…
rs25
5
1
MIT 6.823 Spring 2020
A Simple Memory Model
• Reads and writes are always completed in one cycle– A Read can be done any time (i.e., combinational)
– If enabled, a Write is performed at the rising clock edge
(the write address and data must be stable at the clock edge)
L02-16February 6, 2020
MAGICRAM
ReadData
WriteData
Address
WriteEnable
Clock
MIT 6.823 Spring 2020
A Simple Memory Model
• Reads and writes are always completed in one cycle– A Read can be done any time (i.e., combinational)
– If enabled, a Write is performed at the rising clock edge
(the write address and data must be stable at the clock edge)
L02-16February 6, 2020
MAGICRAM
ReadData
WriteData
Address
WriteEnable
Clock
Later in the course we will present a more realistic model of memory
L02-51MIT 6.823 Spring 2020
Implementing MIPS:
Single-cycle per instructiondatapath & control logic
February 6, 2020
MIT 6.823 Spring 2020
The MIPS ISA
L02-18February 6, 2020
Processor State32 32-bit GPRs, R0 always contains a 032 single precision FPRs, may also be viewed as
16 double precision FPRsFP status register, used for FP compares & exceptionsPC, the program counterSome other special registers
Data types8-bit byte, 16-bit half word 32-bit word for integers32-bit word for single precision floating point64-bit word for double precision floating point
Load/Store style instruction setData addressing modes: immediate & indexedBranch addressing modes: PC relative & register indirectByte-addressable memory, big-endian mode
All instructions are 32 bits
MIT 6.823 Spring 2020
Instruction Execution
L02-19February 6, 2020
Execution of an instruction involves
MIT 6.823 Spring 2020
Instruction Execution
L02-19February 6, 2020
Execution of an instruction involves
1. Instruction fetch
MIT 6.823 Spring 2020
Instruction Execution
L02-19February 6, 2020
Execution of an instruction involves
1. Instruction fetch2. Decode
MIT 6.823 Spring 2020
Instruction Execution
L02-19February 6, 2020
Execution of an instruction involves
1. Instruction fetch2. Decode3. Register fetch
MIT 6.823 Spring 2020
Instruction Execution
L02-19February 6, 2020
Execution of an instruction involves
1. Instruction fetch2. Decode3. Register fetch4. ALU operation
MIT 6.823 Spring 2020
Instruction Execution
L02-19February 6, 2020
Execution of an instruction involves
1. Instruction fetch2. Decode3. Register fetch4. ALU operation5. Memory operation (optional)
MIT 6.823 Spring 2020
Instruction Execution
L02-19February 6, 2020
Execution of an instruction involves
1. Instruction fetch2. Decode3. Register fetch4. ALU operation5. Memory operation (optional)6. Write back
MIT 6.823 Spring 2020
Instruction Execution
L02-19February 6, 2020
Execution of an instruction involves
1. Instruction fetch2. Decode3. Register fetch4. ALU operation5. Memory operation (optional)6. Write back
And computing the address of the next instruction (next PC)
MIT 6.823 Spring 2020
Datapath: Reg-Reg ALU Instructions
L02-20February 6, 2020
6 5 5 5 5 60 rs rt rd 0 func rd (rs) func (rt)
31 26 25 21 20 16 15 11 5 0
MIT 6.823 Spring 2020
Datapath: Reg-Reg ALU Instructions
L02-20February 6, 2020
6 5 5 5 5 60 rs rt rd 0 func rd (rs) func (rt)
31 26 25 21 20 16 15 11 5 0
0x4
Add
clk
addrinst
Inst.
Memory
PC
MIT 6.823 Spring 2020
Datapath: Reg-Reg ALU Instructions
L02-20February 6, 2020
6 5 5 5 5 60 rs rt rd 0 func rd (rs) func (rt)
31 26 25 21 20 16 15 11 5 0
0x4
Add
clk
addrinst
Inst.
Memory
PC
MIT 6.823 Spring 2020
Datapath: Reg-Reg ALU Instructions
L02-20February 6, 2020
6 5 5 5 5 60 rs rt rd 0 func rd (rs) func (rt)
31 26 25 21 20 16 15 11 5 0
0x4
Add
clk
addrinst
Inst.
Memory
PC
MIT 6.823 Spring 2020
Datapath: Reg-Reg ALU Instructions
L02-20February 6, 2020
6 5 5 5 5 60 rs rt rd 0 func rd (rs) func (rt)
31 26 25 21 20 16 15 11 5 0
0x4
Add
clk
addrinst
Inst.
Memory
PC
inst<25:21>inst<20:16>
inst<15:11>
inst<5:0>
OpCode
zALU
ALU
Control
RegWrite
clk
rd1
GPRs
rs1rs2
wswd rd2
we
MIT 6.823 Spring 2020
Datapath: Reg-Reg ALU Instructions
L02-20February 6, 2020
6 5 5 5 5 60 rs rt rd 0 func rd (rs) func (rt)
31 26 25 21 20 16 15 11 5 0
0x4
Add
clk
addrinst
Inst.
Memory
PC
inst<25:21>inst<20:16>
inst<15:11>
inst<5:0>
OpCode
zALU
ALU
Control
RegWrite
clk
rd1
GPRs
rs1rs2
wswd rd2
we
MIT 6.823 Spring 2020
Datapath: Reg-Reg ALU Instructions
L02-20February 6, 2020
6 5 5 5 5 60 rs rt rd 0 func rd (rs) func (rt)
31 26 25 21 20 16 15 11 5 0
0x4
Add
clk
addrinst
Inst.
Memory
PC
inst<25:21>inst<20:16>
inst<15:11>
inst<5:0>
OpCode
zALU
ALU
Control
RegWrite
clk
rd1
GPRs
rs1rs2
wswd rd2
we
MIT 6.823 Spring 2020
Datapath: Reg-Reg ALU Instructions
L02-20February 6, 2020
RegWrite Timing?6 5 5 5 5 60 rs rt rd 0 func rd (rs) func (rt)
31 26 25 21 20 16 15 11 5 0
0x4
Add
clk
addrinst
Inst.
Memory
PC
inst<25:21>inst<20:16>
inst<15:11>
inst<5:0>
OpCode
zALU
ALU
Control
RegWrite
clk
rd1
GPRs
rs1rs2
wswd rd2
we
MIT 6.823 Spring 2020
Datapath: Reg-Imm ALU Instructions
L02-21February 6, 2020
6 5 5 16opcode rs rt immediate rt (rs) op immediate
31 26 25 2120 16 15 0
OpCode
0x4
Add
clk
addrinst
Inst.
Memory
PC
zALU
RegWrite
clk
rd1
GPRs
rs1rs2
wswd rd2
weinst<25:21>
inst<20:16>
inst<31:26> ALUControl
MIT 6.823 Spring 2020
Datapath: Reg-Imm ALU Instructions
L02-21February 6, 2020
6 5 5 16opcode rs rt immediate rt (rs) op immediate
31 26 25 2120 16 15 0
ImmExt
ExtSel
inst<15:0>
OpCode
0x4
Add
clk
addrinst
Inst.
Memory
PC
zALU
RegWrite
clk
rd1
GPRs
rs1rs2
wswd rd2
weinst<25:21>
inst<20:16>
inst<31:26> ALUControl
MIT 6.823 Spring 2020
Conflicts in Merging Datapath
L02-22February 6, 2020
ImmExt
ExtSelOpCode
0x4
Add
clk
addrinst
Inst.
Memory
PC
zALU
RegWrite
clk
rd1
GPRs
rs1rs2
wswd rd2
weinst<25:21>
inst<20:16>
inst<15:0>
inst<31:26> ALUControl
inst<15:11>
inst<5:0>
opcode rs rt immediate rt (rs) op immediate
6 5 5 5 5 60 rs rt rd 0 func rd (rs) func (rt)
MIT 6.823 Spring 2020
Conflicts in Merging Datapath
L02-22February 6, 2020
ImmExt
ExtSelOpCode
0x4
Add
clk
addrinst
Inst.
Memory
PC
zALU
RegWrite
clk
rd1
GPRs
rs1rs2
wswd rd2
weinst<25:21>
inst<20:16>
inst<15:0>
inst<31:26> ALUControl
inst<15:11>
inst<5:0>
opcode rs rt immediate rt (rs) op immediate
6 5 5 5 5 60 rs rt rd 0 func rd (rs) func (rt)
MIT 6.823 Spring 2020
Conflicts in Merging Datapath
L02-22February 6, 2020
ImmExt
ExtSelOpCode
0x4
Add
clk
addrinst
Inst.
Memory
PC
zALU
RegWrite
clk
rd1
GPRs
rs1rs2
wswd rd2
weinst<25:21>
inst<20:16>
inst<15:0>
inst<31:26> ALUControl
inst<15:11>
inst<5:0>
opcode rs rt immediate rt (rs) op immediate
6 5 5 5 5 60 rs rt rd 0 func rd (rs) func (rt)
MIT 6.823 Spring 2020
Conflicts in Merging Datapath
L02-22February 6, 2020
ImmExt
ExtSelOpCode
0x4
Add
clk
addrinst
Inst.
Memory
PC
zALU
RegWrite
clk
rd1
GPRs
rs1rs2
wswd rd2
weinst<25:21>
inst<20:16>
inst<15:0>
inst<31:26> ALUControl
inst<15:11>
inst<5:0>
opcode rs rt immediate rt (rs) op immediate
6 5 5 5 5 60 rs rt rd 0 func rd (rs) func (rt)
MIT 6.823 Spring 2020
Conflicts in Merging Datapath
L02-22February 6, 2020
ImmExt
ExtSelOpCode
0x4
Add
clk
addrinst
Inst.
Memory
PC
zALU
RegWrite
clk
rd1
GPRs
rs1rs2
wswd rd2
weinst<25:21>
inst<20:16>
inst<15:0>
inst<31:26> ALUControl
inst<15:11>
inst<5:0>
opcode rs rt immediate rt (rs) op immediate
6 5 5 5 5 60 rs rt rd 0 func rd (rs) func (rt)
Introducemuxes
MIT 6.823 Spring 2020
Datapath for ALU Instructions
L02-23February 6, 2020
opcode rs rt immediate rt (rs) op immediate
6 5 5 5 5 60 rs rt rd 0 func rd (rs) func (rt)
ImmExt
ExtSelOpCode
0x4
Add
clk
addrinst
Inst.
Memory
PC
zALU
RegWrite
clk
rd1
GPRs
rs1rs2
wswd rd2
we<25:21>
<20:16>
<15:0>
ALUControl
<15:11>
MIT 6.823 Spring 2020
Datapath for ALU Instructions
L02-23February 6, 2020
opcode rs rt immediate rt (rs) op immediate
6 5 5 5 5 60 rs rt rd 0 func rd (rs) func (rt)
BSrc
Reg / Imm
ImmExt
ExtSelOpCode
0x4
Add
clk
addrinst
Inst.
Memory
PC
zALU
RegWrite
clk
rd1
GPRs
rs1rs2
wswd rd2
we<25:21>
<20:16>
<15:0>
ALUControl
<15:11>
MIT 6.823 Spring 2020
Datapath for ALU Instructions
L02-23February 6, 2020
opcode rs rt immediate rt (rs) op immediate
6 5 5 5 5 60 rs rt rd 0 func rd (rs) func (rt)
BSrc
Reg / ImmRegDst
rt / rd
ImmExt
ExtSelOpCode
0x4
Add
clk
addrinst
Inst.
Memory
PC
zALU
RegWrite
clk
rd1
GPRs
rs1rs2
wswd rd2
we<25:21>
<20:16>
<15:0>
ALUControl
<15:11>
MIT 6.823 Spring 2020
Datapath for ALU Instructions
L02-23February 6, 2020
<31:26>, <5:0>
opcode rs rt immediate rt (rs) op immediate
6 5 5 5 5 60 rs rt rd 0 func rd (rs) func (rt)
BSrc
Reg / ImmRegDst
rt / rd
ImmExt
ExtSelOpCode
0x4
Add
clk
addrinst
Inst.
Memory
PC
zALU
RegWrite
clk
rd1
GPRs
rs1rs2
wswd rd2
we<25:21>
<20:16>
<15:0>
OpSel
ALUControl
<15:11>
MIT 6.823 Spring 2020
Datapath for Memory Instructions
L02-24February 6, 2020
Should program and data memory be separate?
Harvard style: separate (Aiken and Mark 1 influence)- read-only program memory- read/write data memory
Princeton style: the same (von Neumann’s influence)- single read/write memory for program and data
MIT 6.823 Spring 2020
Datapath for Memory Instructions
L02-24February 6, 2020
Should program and data memory be separate?
Harvard style: separate (Aiken and Mark 1 influence)- read-only program memory- read/write data memory
- Note: There must be a way to load the program memory
Princeton style: the same (von Neumann’s influence)- single read/write memory for program and data
MIT 6.823 Spring 2020
Datapath for Memory Instructions
L02-24February 6, 2020
Should program and data memory be separate?
Harvard style: separate (Aiken and Mark 1 influence)- read-only program memory- read/write data memory
- Note: There must be a way to load the program memory
Princeton style: the same (von Neumann’s influence)- single read/write memory for program and data
- Note: Executing a Load or Store instruction requires accessing the memory more than once
MIT 6.823 Spring 2020
Load/Store InstructionsHarvard Datapath
L02-25February 6, 2020
rs is the base registerrt is the destination of a Load or the source for a Store
6 5 5 16 addressing modeopcode rs rt displacement (rs) + displacement
31 26 25 21 20 16 15 0
MIT 6.823 Spring 2020
Load/Store InstructionsHarvard Datapath
L02-25February 6, 2020
rs is the base registerrt is the destination of a Load or the source for a Store
6 5 5 16 addressing modeopcode rs rt displacement (rs) + displacement
31 26 25 21 20 16 15 0
RegDst BSrc
“base”
disp
ExtSelOpCode OpSel
ALUControl
zALU
0x4
Add
clk
addrinst
Inst.
Memory
PC
RegWrite
clk
rd1
GPRs
rs1rs2
wswd rd2
we
ImmExt
MIT 6.823 Spring 2020
Load/Store InstructionsHarvard Datapath
L02-25February 6, 2020
rs is the base registerrt is the destination of a Load or the source for a Store
6 5 5 16 addressing modeopcode rs rt displacement (rs) + displacement
31 26 25 21 20 16 15 0
RegDst BSrc
“base”
disp
ExtSelOpCode OpSel
ALUControl
zALU
0x4
Add
clk
addrinst
Inst.
Memory
PC
RegWrite
clk
rd1
GPRs
rs1rs2
wswd rd2
we
ImmExt
MIT 6.823 Spring 2020
Load/Store InstructionsHarvard Datapath
L02-25February 6, 2020
rs is the base registerrt is the destination of a Load or the source for a Store
6 5 5 16 addressing modeopcode rs rt displacement (rs) + displacement
31 26 25 21 20 16 15 0
RegDst BSrc
“base”
disp
ExtSelOpCode OpSel
ALUControl
zALU
0x4
Add
clk
addrinst
Inst.
Memory
PC
RegWrite
clk
rd1
GPRs
rs1rs2
wswd rd2
we
ImmExt
MIT 6.823 Spring 2020
Load/Store InstructionsHarvard Datapath
L02-25February 6, 2020
rs is the base registerrt is the destination of a Load or the source for a Store
6 5 5 16 addressing modeopcode rs rt displacement (rs) + displacement
31 26 25 21 20 16 15 0
RegDst BSrc
“base”
disp
ExtSelOpCode OpSel
ALUControl
zALU
0x4
Add
clk
addrinst
Inst.
Memory
PC
RegWrite
clk
rd1
GPRs
rs1rs2
wswd rd2
we
ImmExt
clk
MemWrite
addr
wdata
rdataData
Memory
we
MIT 6.823 Spring 2020
Load/Store InstructionsHarvard Datapath
L02-25February 6, 2020
WBSrc
ALU / Mem
rs is the base registerrt is the destination of a Load or the source for a Store
6 5 5 16 addressing modeopcode rs rt displacement (rs) + displacement
31 26 25 21 20 16 15 0
RegDst BSrc
“base”
disp
ExtSelOpCode OpSel
ALUControl
zALU
0x4
Add
clk
addrinst
Inst.
Memory
PC
RegWrite
clk
rd1
GPRs
rs1rs2
wswd rd2
we
ImmExt
clk
MemWrite
addr
wdata
rdataData
Memory
we
MIT 6.823 Spring 2020
Load/Store InstructionsHarvard Datapath
L02-25February 6, 2020
WBSrc
ALU / Mem
rs is the base registerrt is the destination of a Load or the source for a Store
6 5 5 16 addressing modeopcode rs rt displacement (rs) + displacement
31 26 25 21 20 16 15 0
RegDst BSrc
“base”
disp
ExtSelOpCode OpSel
ALUControl
zALU
0x4
Add
clk
addrinst
Inst.
Memory
PC
RegWrite
clk
rd1
GPRs
rs1rs2
wswd rd2
we
ImmExt
clk
MemWrite
addr
wdata
rdataData
Memory
we
MIT 6.823 Spring 2020
MIPS Control Instructions
L02-26February 6, 2020
Conditional (on GPR) PC-relative branch
Unconditional register-indirect jumps
Unconditional absolute jumps
• PC-relative branches add offset4 to PC+4 to calculate the target address (offset is in words): 128 KB range
• Absolute jumps append target4 to PC<31:28> to calculate the target address: 256 MB range
• Jump-&-link stores PC+4 into the link register (R31)• Control transfers are not delayed
we will worry about the branch delay slot later
6 5 5 16opcode rs offset BEQZ, BNEZ
6 26opcode target J, JAL
6 5 5 16opcode rs JR, JALR
MIT 6.823 Spring 2020
Conditional Branches (BEQZ, BNEZ)
L02-27February 6, 2020
0x4
Add
clk
WBSrcMemWrite
addr
wdata
rdataData
Memory
we
RegDst BSrcExtSelOpCode
z
OpSel
clk
zero?
clk
addrinst
Inst.
Memory
PC rd1
GPRs
rs1rs2
wswd rd2
we
Imm
Ext
ALU
ALUControl
pc+4
RegWrite
MIT 6.823 Spring 2020
Conditional Branches (BEQZ, BNEZ)
L02-27February 6, 2020
0x4
Add
clk
WBSrcMemWrite
addr
wdata
rdataData
Memory
we
RegDst BSrcExtSelOpCode
z
OpSel
clk
zero?
clk
addrinst
Inst.
Memory
PC rd1
GPRs
rs1rs2
wswd rd2
we
Imm
Ext
ALU
ALUControl
Add
br
pc+4
RegWrite
MIT 6.823 Spring 2020
Conditional Branches (BEQZ, BNEZ)
L02-27February 6, 2020
0x4
Add
clk
WBSrcMemWrite
addr
wdata
rdataData
Memory
we
RegDst BSrcExtSelOpCode
z
OpSel
clk
zero?
clk
addrinst
Inst.
Memory
PC rd1
GPRs
rs1rs2
wswd rd2
we
Imm
Ext
ALU
ALUControl
Add
br
pc+4
RegWrite
MIT 6.823 Spring 2020
Conditional Branches (BEQZ, BNEZ)
L02-27February 6, 2020
0x4
Add
clk
WBSrcMemWrite
addr
wdata
rdataData
Memory
we
RegDst BSrcExtSelOpCode
z
OpSel
clk
zero?
clk
addrinst
Inst.
Memory
PC rd1
GPRs
rs1rs2
wswd rd2
we
Imm
Ext
ALU
ALUControl
Add
br
pc+4
RegWrite
MIT 6.823 Spring 2020
Conditional Branches (BEQZ, BNEZ)
L02-27February 6, 2020
0x4
Add
clk
WBSrcMemWrite
addr
wdata
rdataData
Memory
we
RegDst BSrcExtSelOpCode
z
OpSel
clk
zero?
clk
addrinst
Inst.
Memory
PC rd1
GPRs
rs1rs2
wswd rd2
we
Imm
Ext
ALU
ALUControl
Add
br
pc+4
RegWrite
MIT 6.823 Spring 2020
Conditional Branches (BEQZ, BNEZ)
L02-27February 6, 2020
0x4
Add
PCSrc
clk
WBSrcMemWrite
addr
wdata
rdataData
Memory
we
RegDst BSrcExtSelOpCode
z
OpSel
clk
zero?
clk
addrinst
Inst.
Memory
PC rd1
GPRs
rs1rs2
wswd rd2
we
Imm
Ext
ALU
ALUControl
Add
br
pc+4
RegWrite
MIT 6.823 Spring 2020
Conditional Branches (BEQZ, BNEZ)
L02-27February 6, 2020
0x4
Add
PCSrc
clk
WBSrcMemWrite
addr
wdata
rdataData
Memory
we
RegDst BSrcExtSelOpCode
z
OpSel
clk
zero?
clk
addrinst
Inst.
Memory
PC rd1
GPRs
rs1rs2
wswd rd2
we
Imm
Ext
ALU
ALUControl
Add
br
pc+4
RegWrite
MIT 6.823 Spring 2020
Conditional Branches (BEQZ, BNEZ)
L02-27February 6, 2020
0x4
Add
PCSrc
clk
WBSrcMemWrite
addr
wdata
rdataData
Memory
we
RegDst BSrcExtSelOpCode
z
OpSel
clk
zero?
clk
addrinst
Inst.
Memory
PC rd1
GPRs
rs1rs2
wswd rd2
we
Imm
Ext
ALU
ALUControl
Add
br
pc+4
RegWrite
MIT 6.823 Spring 2020
Register-Indirect Jumps (JR)
L02-28February 6, 2020
0x4
RegWrite
Add
Add
clk
WBSrcMemWrite
addr
wdata
rdataData
Memory
we
RegDst BSrcExtSelOpCode
z
OpSel
clk
zero?
clk
addrinst
Inst.
Memory
PC rd1
GPRs
rs1rs2
wswd rd2
we
Imm
Ext
ALU
ALUControl
PCSrc
br
pc+4
MIT 6.823 Spring 2020
Register-Indirect Jumps (JR)
L02-28February 6, 2020
0x4
RegWrite
Add
Add
clk
WBSrcMemWrite
addr
wdata
rdataData
Memory
we
RegDst BSrcExtSelOpCode
z
OpSel
clk
zero?
clk
addrinst
Inst.
Memory
PC rd1
GPRs
rs1rs2
wswd rd2
we
Imm
Ext
ALU
ALUControl
PCSrc
br
pc+4
rind
MIT 6.823 Spring 2020
Register-Indirect Jumps (JR)
L02-28February 6, 2020
0x4
RegWrite
Add
Add
clk
WBSrcMemWrite
addr
wdata
rdataData
Memory
we
RegDst BSrcExtSelOpCode
z
OpSel
clk
zero?
clk
addrinst
Inst.
Memory
PC rd1
GPRs
rs1rs2
wswd rd2
we
Imm
Ext
ALU
ALUControl
PCSrc
br
pc+4
rind
MIT 6.823 Spring 2020
Register-Indirect Jump-&-Link (JALR)
L02-29February 6, 2020
0x4
RegWrite
Add
Add
clk
WBSrcMemWrite
addr
wdata
rdataData
Memory
we
RegDst BSrcExtSelOpCode
z
OpSel
clk
zero?
clk
addrinst
Inst.
Memory
PC rd1
GPRs
rs1rs2
wswd rd2
we
Imm
Ext
ALU
ALUControl
31
PCSrc
br
pc+4
rind
MIT 6.823 Spring 2020
Register-Indirect Jump-&-Link (JALR)
L02-29February 6, 2020
0x4
RegWrite
Add
Add
clk
WBSrcMemWrite
addr
wdata
rdataData
Memory
we
RegDst BSrcExtSelOpCode
z
OpSel
clk
zero?
clk
addrinst
Inst.
Memory
PC rd1
GPRs
rs1rs2
wswd rd2
we
Imm
Ext
ALU
ALUControl
31
PCSrc
br
pc+4
rind
MIT 6.823 Spring 2020
Register-Indirect Jump-&-Link (JALR)
L02-29February 6, 2020
0x4
RegWrite
Add
Add
clk
WBSrcMemWrite
addr
wdata
rdataData
Memory
we
RegDst BSrcExtSelOpCode
z
OpSel
clk
zero?
clk
addrinst
Inst.
Memory
PC rd1
GPRs
rs1rs2
wswd rd2
we
Imm
Ext
ALU
ALUControl
31
PCSrc
br
pc+4
rind
MIT 6.823 Spring 2020
Register-Indirect Jump-&-Link (JALR)
L02-29February 6, 2020
0x4
RegWrite
Add
Add
clk
WBSrcMemWrite
addr
wdata
rdataData
Memory
we
RegDst BSrcExtSelOpCode
z
OpSel
clk
zero?
clk
addrinst
Inst.
Memory
PC rd1
GPRs
rs1rs2
wswd rd2
we
Imm
Ext
ALU
ALUControl
31
PCSrc
br
pc+4
rind
MIT 6.823 Spring 2020
Absolute Jumps (J, JAL)
L02-30February 6, 2020
0x4
RegWrite
Add
Add
clk
WBSrcMemWrite
addr
wdata
rdataData
Memory
we
RegDst BSrcExtSelOpCode
z
OpSel
clk
zero?
clk
addrinst
Inst.
Memory
PC rd1
GPRs
rs1rs2
wswd rd2
we
Imm
Ext
ALU
ALUControl
31
PCSrc
br
pc+4
rindjabs
MIT 6.823 Spring 2020
Absolute Jumps (J, JAL)
L02-30February 6, 2020
0x4
RegWrite
Add
Add
clk
WBSrcMemWrite
addr
wdata
rdataData
Memory
we
RegDst BSrcExtSelOpCode
z
OpSel
clk
zero?
clk
addrinst
Inst.
Memory
PC rd1
GPRs
rs1rs2
wswd rd2
we
Imm
Ext
ALU
ALUControl
31
PCSrc
br
pc+4
rindjabs
MIT 6.823 Spring 2020
Absolute Jumps (J, JAL)
L02-30February 6, 2020
0x4
RegWrite
Add
Add
clk
WBSrcMemWrite
addr
wdata
rdataData
Memory
we
RegDst BSrcExtSelOpCode
z
OpSel
clk
zero?
clk
addrinst
Inst.
Memory
PC rd1
GPRs
rs1rs2
wswd rd2
we
Imm
Ext
ALU
ALUControl
31
PCSrc
br
pc+4
rindjabs
MIT 6.823 Spring 2020
Absolute Jumps (J, JAL)
L02-30February 6, 2020
0x4
RegWrite
Add
Add
clk
WBSrcMemWrite
addr
wdata
rdataData
Memory
we
RegDst BSrcExtSelOpCode
z
OpSel
clk
zero?
clk
addrinst
Inst.
Memory
PC rd1
GPRs
rs1rs2
wswd rd2
we
Imm
Ext
ALU
ALUControl
31
PCSrc
br
pc+4
rindjabs
MIT 6.823 Spring 2020
Absolute Jumps (J, JAL)
L02-30February 6, 2020
0x4
RegWrite
Add
Add
clk
WBSrcMemWrite
addr
wdata
rdataData
Memory
we
RegDst BSrcExtSelOpCode
z
OpSel
clk
zero?
clk
addrinst
Inst.
Memory
PC rd1
GPRs
rs1rs2
wswd rd2
we
Imm
Ext
ALU
ALUControl
31
PCSrc
br
pc+4
rindjabs
MIT 6.823 Spring 2020
Harvard-Style Datapath for MIPS
L02-31February 6, 2020
0x4
RegWrite
Add
Add
clk
WBSrcMemWrite
addr
wdata
rdataData
Memory
we
RegDst BSrcExtSelOpCode
z
OpSel
clk
zero?
clk
addrinst
Inst.
Memory
PC rd1
GPRs
rs1rs2
wswd rd2
we
Imm
Ext
ALU
ALUControl
31
PCSrc
br
rindjabs
pc+4
MIT 6.823 Spring 2020
Hardwired Control is pure Combinational Logic
L02-32February 6, 2020
combinational logic
op code
zero?
ExtSel
BSrc
OpSel
MemWrite
WBSrc
RegDst
RegWrite
PCSrc
MIT 6.823 Spring 2020
ALU Control & Immediate Extension
L02-33February 6, 2020
Inst<31:26> (Opcode)
Decode Map
Inst<5:0> (Func)
ALUop
0?
+
OpSel
( Func, Op, +, 0? )
ExtSel
( sExt16, uExt16,
High16)
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
*
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
* Reg
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
* Reg Func
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
* Reg Func no
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
* Reg Func no yes
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
* Reg Func no yes ALU
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
* Reg Func no yes ALU rd
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
pc+4* Reg Func no yes ALU rd
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
pc+4* Reg Func no yes ALU rd
sExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
pc+4* Reg Func no yes ALU rd
sExt16 Imm
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
sExt16
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
sExt16 Imm
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
sExt16 Imm +
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
sExt16 Imm + no
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
sExt16 Imm + no yes
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
sExt16 Imm + no yes Mem
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
sExt16 Imm + no yes Mem rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
pc+4sExt16 Imm + no yes Mem rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
pc+4sExt16 Imm + yes no * *
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
pc+4sExt16 Imm + no yes Mem rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
sExt16
pc+4sExt16 Imm + yes no * *
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
pc+4sExt16 Imm + no yes Mem rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
sExt16 *
pc+4sExt16 Imm + yes no * *
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
pc+4sExt16 Imm + no yes Mem rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
sExt16 * 0?
pc+4sExt16 Imm + yes no * *
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
pc+4sExt16 Imm + no yes Mem rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
sExt16 * 0? no no * *
pc+4sExt16 Imm + yes no * *
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
pc+4sExt16 Imm + no yes Mem rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
brsExt16 * 0? no no * *
pc+4sExt16 Imm + yes no * *
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
pc+4sExt16 Imm + no yes Mem rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
sExt16 * 0? no no * *
brsExt16 * 0? no no * *
pc+4sExt16 Imm + yes no * *
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
pc+4sExt16 Imm + no yes Mem rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
pc+4sExt16 * 0? no no * *
brsExt16 * 0? no no * *
pc+4sExt16 Imm + yes no * *
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
pc+4sExt16 Imm + no yes Mem rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
* * *
pc+4sExt16 * 0? no no * *
brsExt16 * 0? no no * *
pc+4sExt16 Imm + yes no * *
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
pc+4sExt16 Imm + no yes Mem rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
* * * no no * *
pc+4sExt16 * 0? no no * *
brsExt16 * 0? no no * *
pc+4sExt16 Imm + yes no * *
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
pc+4sExt16 Imm + no yes Mem rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
jabs* * * no no * *
pc+4sExt16 * 0? no no * *
brsExt16 * 0? no no * *
pc+4sExt16 Imm + yes no * *
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
pc+4sExt16 Imm + no yes Mem rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
* * * no
jabs* * * no no * *
pc+4sExt16 * 0? no no * *
brsExt16 * 0? no no * *
pc+4sExt16 Imm + yes no * *
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
pc+4sExt16 Imm + no yes Mem rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
* * * no yes
jabs* * * no no * *
pc+4sExt16 * 0? no no * *
brsExt16 * 0? no no * *
pc+4sExt16 Imm + yes no * *
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
pc+4sExt16 Imm + no yes Mem rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
* * * no yes PC
jabs* * * no no * *
pc+4sExt16 * 0? no no * *
brsExt16 * 0? no no * *
pc+4sExt16 Imm + yes no * *
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
pc+4sExt16 Imm + no yes Mem rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
* * * no yes PC R31
jabs* * * no no * *
pc+4sExt16 * 0? no no * *
brsExt16 * 0? no no * *
pc+4sExt16 Imm + yes no * *
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
pc+4sExt16 Imm + no yes Mem rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
jabs* * * no yes PC R31
jabs* * * no no * *
pc+4sExt16 * 0? no no * *
brsExt16 * 0? no no * *
pc+4sExt16 Imm + yes no * *
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
pc+4sExt16 Imm + no yes Mem rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
* * *
jabs* * * no yes PC R31
jabs* * * no no * *
pc+4sExt16 * 0? no no * *
brsExt16 * 0? no no * *
pc+4sExt16 Imm + yes no * *
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
pc+4sExt16 Imm + no yes Mem rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
* * * no no * *
jabs* * * no yes PC R31
jabs* * * no no * *
pc+4sExt16 * 0? no no * *
brsExt16 * 0? no no * *
pc+4sExt16 Imm + yes no * *
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
pc+4sExt16 Imm + no yes Mem rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
rind* * * no no * *
jabs* * * no yes PC R31
jabs* * * no no * *
pc+4sExt16 * 0? no no * *
brsExt16 * 0? no no * *
pc+4sExt16 Imm + yes no * *
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
pc+4sExt16 Imm + no yes Mem rt
uExt16
MIT 6.823 Spring 2020
Hardwired Control Table
L02-34February 6, 2020
Opcode ExtSel BSrc OpSel MemW RegW WBSrc RegDst PCSrc
ALU
ALUi
ALUiu
LW
SW
BEQZz=0
BEQZz=1
J
JAL
JR
JALR
BSrc = Reg / Imm WBSrc = ALU / Mem / PC
RegDst = rt / rd / R31 PCSrc = pc+4 / br / rind / jabs
* * * no yes rindPC R31
rind* * * no no * *
jabs* * * no yes PC R31
jabs* * * no no * *
pc+4sExt16 * 0? no no * *
brsExt16 * 0? no no * *
pc+4sExt16 Imm + yes no * *
pc+4Imm Op no yes ALU rt
pc+4* Reg Func no yes ALU rd
sExt16 Imm Op pc+4no yes ALU rt
pc+4sExt16 Imm + no yes Mem rt
uExt16
MIT 6.823 Spring 2020
Single-Cycle Hardwired Control:Harvard architecture
L02-35February 6, 2020
We will assume • Clock period is sufficiently long for all of
the following steps to be “completed”:
1. instruction fetch2. decode and register fetch3. ALU operation4. data fetch if required5. register write-back setup time
tC > tIFetch + tRFetch + tALU+ tDMem+ tRWB
• At the rising edge of the following clock, the PC,the register file and the memory are updated
MIT 6.823 Spring 2020
Princeton challenge
L02-36February 6, 2020
• What problem arises if instructions and data reside in the same memory?
MIT 6.823 Spring 2020
Princeton challenge
L02-36February 6, 2020
At least the instruction fetch and a Load (or Store) cannot be executed in the same cycle
• What problem arises if instructions and data reside in the same memory?
MIT 6.823 Spring 2020
Princeton challenge
L02-36February 6, 2020
At least the instruction fetch and a Load (or Store) cannot be executed in the same cycle
• What problem arises if instructions and data reside in the same memory?
Structural hazard
MIT 6.823 Spring 2020
Princeton MicroarchitectureDatapath & Control
L02-37February 6, 2020
IR
0x4
clk
RegDst
PCSrcRegWrite
BSrc zero?
WBSrc
31
ExtSelOpCode
Add
rd1
GPRs
rs1rs2
wswd rd2
we
ImmExt
addr
wdata
rdataData Memory
z
ALU
Add
OpSel
ALUControl
clk
we
MemWrite
clk
PC
PCen
IRen AddrSrc
clk
MIT 6.823 Spring 2020
Princeton MicroarchitectureDatapath & Control
L02-37February 6, 2020
IR
0x4
clk
RegDst
PCSrcRegWrite
BSrc zero?
WBSrc
31
ExtSelOpCode
Add
rd1
GPRs
rs1rs2
wswd rd2
we
ImmExt
addr
wdata
rdataData Memory
z
ALU
Add
OpSel
ALUControl
clk
we
MemWrite
clk
PC
PCen
IRen AddrSrc
clk
Fetch phase
MIT 6.823 Spring 2020
Princeton MicroarchitectureDatapath & Control
L02-37February 6, 2020
IR
0x4
clk
RegDst
PCSrcRegWrite
BSrc zero?
WBSrc
31
ExtSelOpCode
Add
rd1
GPRs
rs1rs2
wswd rd2
we
ImmExt
addr
wdata
rdataData Memory
z
ALU
Add
OpSel
ALUControl
clk
we
MemWrite
clk
PC
PCen
IRen AddrSrc
clk
Fetch phase
MIT 6.823 Spring 2020
Princeton MicroarchitectureDatapath & Control
L02-37February 6, 2020
IR
0x4
clk
RegDst
PCSrcRegWrite
BSrc zero?
WBSrc
31
ExtSelOpCode
Add
rd1
GPRs
rs1rs2
wswd rd2
we
ImmExt
addr
wdata
rdataData Memory
z
ALU
Add
OpSel
ALUControl
clk
we
MemWrite
clk
PC
PCen
IRen AddrSrc
clk
Fetch phase
= PC
MIT 6.823 Spring 2020
Princeton MicroarchitectureDatapath & Control
L02-37February 6, 2020
IR
0x4
clk
RegDst
PCSrcRegWrite
BSrc zero?
WBSrc
31
ExtSelOpCode
Add
rd1
GPRs
rs1rs2
wswd rd2
we
ImmExt
addr
wdata
rdataData Memory
z
ALU
Add
OpSel
ALUControl
clk
we
MemWrite
clk
PC
PCen
IRen AddrSrc
clk
Fetch phase
= PC
MIT 6.823 Spring 2020
Princeton MicroarchitectureDatapath & Control
L02-37February 6, 2020
IR
0x4
clk
RegDst
PCSrcRegWrite
BSrc zero?
WBSrc
31
ExtSelOpCode
Add
rd1
GPRs
rs1rs2
wswd rd2
we
ImmExt
addr
wdata
rdataData Memory
z
ALU
Add
OpSel
ALUControl
clk
we
MemWrite
clk
PC
PCen
IRen AddrSrc
clk
Fetch phase
= PC
MIT 6.823 Spring 2020
Princeton MicroarchitectureDatapath & Control
L02-37February 6, 2020
IR
0x4
clk
RegDst
PCSrcRegWrite
BSrc zero?
WBSrc
31
ExtSelOpCode
Add
rd1
GPRs
rs1rs2
wswd rd2
we
ImmExt
addr
wdata
rdataData Memory
z
ALU
Add
OpSel
ALUControl
clk
we
MemWrite
clk
PC
PCen
IRen AddrSrc
clk
Fetch phase
= PC
MIT 6.823 Spring 2020
Princeton MicroarchitectureDatapath & Control
L02-37February 6, 2020
IR
0x4
clk
RegDst
PCSrcRegWrite
BSrc zero?
WBSrc
31
ExtSelOpCode
Add
rd1
GPRs
rs1rs2
wswd rd2
we
ImmExt
addr
wdata
rdataData Memory
z
ALU
Add
OpSel
ALUControl
clk
we
MemWrite
clk
PC
PCen
IRen AddrSrc
clk
Fetch phase
on
= PC
MIT 6.823 Spring 2020
Princeton MicroarchitectureDatapath & Control
L02-37February 6, 2020
IR
0x4
clk
RegDst
PCSrcRegWrite
BSrc zero?
WBSrc
31
ExtSelOpCode
Add
rd1
GPRs
rs1rs2
wswd rd2
we
ImmExt
addr
wdata
rdataData Memory
z
ALU
Add
OpSel
ALUControl
clk
we
MemWrite
clk
PC
PCen
IRen AddrSrc
clk
Fetch phase
on
off
= PC
MIT 6.823 Spring 2020
Princeton MicroarchitectureDatapath & Control
L02-37February 6, 2020
IR
0x4
clk
RegDst
PCSrcRegWrite
BSrc zero?
WBSrc
31
ExtSelOpCode
Add
rd1
GPRs
rs1rs2
wswd rd2
we
ImmExt
addr
wdata
rdataData Memory
z
ALU
Add
OpSel
ALUControl
clk
we
MemWrite
clk
PC
PCen
IRen AddrSrc
clk
Fetch phase
on
off
off
= PC
MIT 6.823 Spring 2020
Princeton MicroarchitectureDatapath & Control
L02-37February 6, 2020
IR
0x4
clk
RegDst
PCSrcRegWrite
BSrc zero?
WBSrc
31
ExtSelOpCode
Add
rd1
GPRs
rs1rs2
wswd rd2
we
ImmExt
addr
wdata
rdataData Memory
z
ALU
Add
OpSel
ALUControl
clk
we
MemWrite
clk
PC
PCen
IRen AddrSrc
clk
Fetch phase
on
offoffoff
= PC
MIT 6.823 Spring 2020
Two-State Controller:Princeton Architecture
L02-38February 6, 2020
fetch phase
execute phaseAddrSrc=ALU
IRen=offPCen=onWen=on
AddrSrc=PCIRen=onPCen=offWen=off
A flipflop can be used to remember the phase
MIT 6.823 Spring 2020
Hardwired Controller:Princeton Architecture
L02-39February 6, 2020
oldcombinational
logic(Harvard)
op code
zero?
ExtSel, BSrc, OpSel, WBSrc, RegDest,PCsrc1, PCsrc2
MemWrite
IR
newcombinational
logic
PCenIRenAddrSrc
S
1-bit Toggle FF I-fetch / Execute
RegWrite
.
.
.
Wen
MIT 6.823 Spring 2020
Clock Rate vs CPI
L02-40February 6, 2020
Is it possible to design a controller for the Princeton architecture with CPI < 2 ?
CPI = Clock cycles Per Instruction
Suppose tM >> tRF+ tALU + tWB
tC-Princeton = 0.5 * tC-Harvard
CPIPrinceton = 2CPIHarvard = 1
No difference in performance!
Stay tuned!
tC-Princeton > max {tM , tRF+ tALU+ tM + tWB}tC-Princeton > tRF+ tALU+ tM + tWB
tC-Harvard > tM + tRF + tALU+ tM+ tWB
